UNITED STATES PATENT AND TRADEMARK OFFICE
`
`__________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`CREE, INC.
`Petitioner
`
`v.
`
`DOCUMENT SECURITY SYSTEMS, INC.
`Patent Owner
`__________________
`Case No. IPR2018-_____
`U.S. Patent No. 7,256,486
`__________________
`DECLARATION OF MICHAEL PECHT PH.D. IN SUPPORT OF
`U. S. PATENT NO. 7,256,486 UNDER
`35 U.S.C. §§ 311-319 AND 37 C.F.R. § 42.100 ET SEQ.
`
`Cree Ex. 1003
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`
`TABLE OF CONTENTS
`
`Page
`
`INTRODUCTION .......................................................................................... 1
`I.
`II. MY EXPERIENCE AND QUALIFICATIONS ............................................ 1
`III. STATUS AS INDEPENDENT EXPERT WITNESS .................................. 10
`IV. MATERIALS CONSIDERED AND BASIS OF OPINIONS ..................... 11
`V. DESCRIPTION OF THE RELEVANT FIELD AND THE
`RELEVANT TIMEFRAME ......................................................................... 11
`VI. THE PERSON OF ORDINARY SKILL IN THE RELEVANT FIELD
`IN THE RELEVANT TIMEFRAME .......................................................... 12
`VII. OVERVIEW OF THE ’486 PATENT AND STATE OF PRACTICE ....... 13
`VIII. UNPATENTABILITY BASED ON PRIOR ART IN THE PRESENT
`PROCEEDINGS ........................................................................................... 16
`A. GROUND 1: CLAIMS 1-3 ARE OBVIOUS BASED ON
`JAPANESE PATENT APPLICATION PUBLICATION NO.
`2003-17754 (“ROHM”) ALONE OR IN VIEW OF U.S.
`PATENT NO. 5,376,580 (“KISH”) ................................................... 19
`1.
`CLAIM 1 .................................................................................. 21
`2.
`CLAIM 2 .................................................................................. 25
`3.
`CLAIM 3 .................................................................................. 27
`B. GROUND 2: CLAIMS 1-3 ARE OBVIOUS BASED ON
`JAPANESE PATENT APPLICATION PUBLICATION NO.
`2001-352102 MATSUSHITA IN VIEW OF U.S. PATENT
`NO. 5,523,589 EDMOND 589........................................................... 28
`1.
`CLAIM 1 .................................................................................. 31
`2.
`CLAIM 2 .................................................................................. 33
`3.
`CLAIM 3 .................................................................................. 35
`IX. SIGNATURE ................................................................................................ 36
`
`
`
`i
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`I.
`
`INTRODUCTION
`I, Michael Pecht, of 7027 Hunter Lane, Hyattsville, Maryland, USA,
`1.
`
`have been retained by Jones Day on behalf of Cree, Inc. to provide an analysis of
`
`the scope and content of U.S. Patent No. 7,256,486 (“the ’486 patent”) relative to
`
`the state of the art at the time of the earliest application underlying the ’486 Patent.
`
`In particular, my analysis relates only to claims 1-3. I have also been retained to
`
`provide analysis regarding what a person of ordinary skill in the art related to
`
`packaging for semiconductor-based light emitting devices would have understood
`
`at the time of the earliest application underlying the ’486 Patent.
`
`2.
`
`This report summarizes the opinions I have formed to date. I reserve
`
`the right to modify my opinions, if necessary, based on further review and analysis
`
`of information that I receive subsequent to the filing of this report, including in
`
`response to positions taken by Document Security Systems, Inc. or its experts that I
`
`have not yet seen.
`
`II. MY EXPERIENCE AND QUALIFICATIONS
`3.
`I am a licensed Professional Engineer in the State of Maryland.
`
`4.
`
`I have a BS in Physics, an MS in Electrical Engineering, and an MS
`
`and PhD in Engineering Mechanics from the University of Wisconsin at Madison.
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`5.
`
`I worked as a civil servant electrical technician for 4 years to pay my
`
`way through college. After graduation, I spent one year working as a NASA
`
`contractor on the Astro-1 space telescope.
`
`6.
`
`Since my Ph.D., I have had over thirty years of additional experience
`
`in the area of electronics, generally including the area of electronic materials,
`
`packaging, design, and testing. I have extensive, hands-on experience with
`
`electronic components, including LED packages. I have served as a professor in
`
`Electrical Engineering, as a Chair Professor in Mechanical Engineering and a
`
`Professor of Applied Mathematics, Statistics, and Scientific Computation, and I
`
`have taught numerous undergraduate and graduate classes on electronic packaging,
`
`including the packaging of LED components. In addition, I have taught formal
`
`courses on electronics components including LED packages for numerous
`
`companies and professional organizations, such as the IEEE, SMTA, and the U.S.
`
`military.
`
`7.
`
`I am a Fellow of three of the largest professional engineering
`
`societies: the Institute of Electrical and Electronics Engineers, Inc. (“IEEE”), the
`
`International Microelectronics Packaging Society (“IMAPS”), the American
`
`Society of Mechanical Engineers (“ASME”), and the Fellow of the Society of
`
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`Automotive Engineering (“SAE”). These professional societies address electronic
`
`components including LED components.
`
`8.
`
`I am the founder and Director of CALCE Electronic Products and
`
`Systems Center at the University of Maryland, which is funded by over 150 of the
`
`world’s leading electronics companies. The focus of the center is on electronic
`
`components and products. My center has over 120 professionals and one of the
`
`largest electronics testing and analysis laboratories in the world, including state of
`
`the art equipment and methods to analyze and test LEDs.
`
`9.
`
`I have consulted with over eighty major international electronics
`
`companies, including with companies on the subject of electronics components and
`
`in particular LEDs. Examples of companies I have consulted with include: Osram,
`
`Philips, Dell, Huawei, Nortel, Nokia, Ericson, and Emerson.
`
`10.
`
`I have also served on various National Academy of
`
`Science/Engineering (NAE / NAS) Committees (invited to participate), including
`
`the committee for reliability growth (how to improve US military weapon
`
`systems), the committee to investigate electronics printed circuit board
`
`manufacturing in the U.S., and the committee to examine US research needs in
`
`materials engineering.
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`11.
`
`I also served as an expert for congressional investigations, including
`
`the Committee on Energy & Commerce to investigate automotive reliability and
`
`safety issues: Toyota sudden acceleration (2009 - 2010) and GM ignition – air bag
`
`recalls and NHTSA responses (2014).
`
`12.
`
`I also served as an U.S. FDA expert, taught courses on electronics,
`
`and aided the FDA in assessing the capability maturity assessment of
`
`manufacturers of medical devices, the techniques used to qualify devices.
`
`13.
`
`I served as chief editor of the IEEE Transactions on Reliability for
`
`eight years and on the advisory board of IEEE Spectrum. I also served as chief
`
`editor for Microelectronics Reliability for over 16 years and as an associate editor
`
`for the IEEE Transactions on Components and Packaging Technology. I am
`
`currently the Editor in Chief for IEEE Access.
`
`14.
`
`I have written over thirty books and over 700 articles on various
`
`subjects related to semiconductor packaging and components including LEDs.
`
`Some of my publications (articles and book chapters) on LEDs include:
`
`
`
`Bo Sun, Xiaopeng Jiang, Kam-Chuen Yung, Jiajie Fan, and Michael
`
`Pecht. “A Review of Prognostic Techniques for High-Power White
`
`LEDs”. IEEE Transactions on Power Electronics, vol. 32, No. 8,
`
`August 2017.
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`
`
`M.-H. Chang, P. Sandborn, M. Pecht, W. K. C. Yung, and W. Wang.
`
`“A Return on Investment Analysis of Applying Health Monitoring to
`
`LED Lighting Systems”, Microelectronics Reliability, Vol. 55, pp.
`
`527- 537, 2015.
`
`
`
`M.-H. Chang, C. Chen, D. Das, and M. Pecht. “Anomaly Detection of
`
`Light-Emitting Diodes Using the Similarity-Based-Metric Test,”
`
`IEEE Transactions on Industrial Informatics, Vol. 10, No. 3, pp. 1852-
`
`1863, August 2014.
`
`
`
`M. Pecht, D. Das, and M.-H. Chang. “Introduction to LED Thermal
`
`Management and Reliability,” Thermal Management for LED
`
`Applications, Solid State Lighting Technology and Application
`
`Series, Vol. 2, pp. 3-14, 2014.
`
`
`
`Fan, J., K-C Yung, and M. Pecht. “Prognostics of Chromaticity State
`
`for Phosphor-converted White Light Emitting Diodes using an
`
`Unscented Kalman Filter Approach,” IEEE Trans. on Device and
`
`Materials Reliability, Vol. 14, No. 1, pp. 564-573, Mar. 2014.
`
`
`
`Pecht, M. and M.-H. Chang. Failure Mechanisms and Reliability
`
`Issues in LEDs, Chapter 3, in Solid State Lighting Reliability:
`
`Components to Systems, Springer Science, pp. 43-110, 2013.
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`
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`Pecht, M., D. Das, and M.-H. Chang, Introduction to LED Thermal
`
`Management and Reliability, Chapter 1, in Thermal Management for
`
`LED Applications, Springer Science + Business Media, pp. 3-14,
`
`2013.
`
`
`
`Song, X., M. H. Chang and M. Pecht. “Rare-Earth Elements in
`
`Lighting and Optical Applications and Their Recycling,” The Journal
`
`of the Minerals, Metals & Materials Society (JOM), Vol. 65, No. 10,
`
`pp. 1276-1282, Aug. 2013.
`
`
`
`
`
`Chang, M-H, D. Das, P.V. Varde, and M. Pecht. “Light Emitting
`
`Diodes Reliability Review,” Microelectronics Reliability, Vol. 52, No.
`
`5, pp. 762-782, May 2012.
`
`Fan, J., K-C Yung, and M. Pecht. “Lifetime Estimation of High-
`
`Power White LED using Degradation-Data-Driven Method,” IEEE
`
`Trans. on Device and Materials Reliability, Vol. 12, No. 2, pp. 470-
`
`477, Jun. 2012.
`
`
`
`Fan, J., K.C. Yung, and M. Pecht. “Comparison of Statistical Models
`
`for the Lumen Lifetime Distribution of High Power White LEDs,”
`
`Proc. of IEEE 2012 Prognostics and System Health Management
`
`Conference (PHM-2012 Beijing), Beijing, May 23-25, 2012.
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`
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`J. Fan, K. C. Yung, and M. Pecht. “Physics-of-Failure-Based
`
`Prognostics and Health Management for High-Power White Light-
`
`Emitting Diode Lighting,” IEEE Transactions on Device and
`
`Materials Reliability, Vol. 11, No. 3, pp. 407-416, September 2011.
`
`
`
`M.-H. Chang, D. Das, and M. Pecht. “Junction Temperature
`
`Characterization of High Power Light Emitting Diodes,” IMAPS Mid-
`
`Atlantic Microelectronics Conference 2011, Atlantic City, New
`
`Jersey, June 23-24, 2011.
`
`
`
`J. Fan, K.C. Yung, and M. Pecht. “Failure Modes, Mechanisms, and
`
`Effects Analysis for LED Backlight Systems used in LCD TVs,”
`
`Prognostics and System health management Conference 2011,
`
`Shenzhen, China, pp. 1-5, May 24 – 25, 2011.
`
`
`
`
`
`
`
`Y. Li, M, Pecht, S. Zhang, and R. Kang. “Return on Investment of a
`
`LED Lighting System,” Prognostics and System Health Management
`
`Conference 2011, Shenzhen, China, pp. 1-5, May 24 – 25, 2011.
`
`M.-H. Chang, D. Das, S.W. Lee, and M. Pecht. “Concerns with
`
`Interconnect Reliability Assessment of High Power Light Emitting
`
`Diodes (LEDs),” SMTA China South Technical Conference 2010,
`
`Shenzhen, China, pp. 63-69, Aug. 31- Sep. 2, 2010.
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`
`
`
`
`Niu, G., D. Lau, and M. Pecht. “Prognostics and Health Management
`
`for Next Generation LED Lighting Systems,” Int’l J. of Condition
`
`Monitoring and Diagnostic Engineering Management, 2009.
`
`Niu, G., M. Lu, D. Lau, and M. Pecht. “Prognostics-based
`
`Qualification for LED Lighting Systems,” 4th Int’l Microsystems,
`
`Packaging, Assembly and Circuits Technology Conference (IMPACT
`
`2009), Taipei, Taiwan, Oct. 21-23, 2009.
`
`
`
`J. Xie and M. Pecht. “Reliability Prediction Modeling of
`
`Semiconductor Light Emitting Device,” IEEE Transactions on Device
`
`and Materials Reliability, Vol. 3, No. 4, pp. 218-222, December 2003.
`
`15.
`
`Since the LED diode (die) is a semiconductor, my experience in
`
`semiconductor packaging (which thus includes LED packaging) is also directly
`
`related and includes:
`
`
`
`
`
`Pecht, M., R. Agarwal, P. McCluskey, T. Dishongh, S. Javadpour, and
`
`R. Mahajan, Electronic Packaging Materials and their Properties,
`
`CRC Press, Boca Raton, FL, 1999.
`
`Hannemann, R., Kraus, A., and M. Pecht, Semiconductor Packaging –
`
`A Multidisciplinary Approach, John Wiley, New York, NY, 1997.
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`
`
`
`
`
`
`16.
`
`17.
`
`Pecht, M., Nguyen, L., and E. Hakim, Plastic Encapsulated
`
`Microelectronics: Materials, Processes, Quality, Reliability, and
`
`Applications, John Wiley, New York, NY, 1995.
`
`Pecht, M., Soldering Processes and Equipment, John Wiley, New
`
`York, NY, 1993.
`
`Pecht, M., Handbook of Electronic Package Design, Marcel Dekker,
`
`New York, NY, 1991.
`
`I currently have 8 U.S. patents.
`
`In 1997, I received the ISHM / IEPS William D. Ashman Memorial
`
`Achievement Award for numerous contributions to academia and the electronics
`
`packaging industry. In 1999, I received the 3M Research Award for research work
`
`in the electronics area that has made significant contributions to the scientific
`
`understanding of material properties and their complex behavior. In 2008, I was
`
`awarded the IEEE Reliability Society’s Lifetime Achievement Award. In 2010, I
`
`received the IEEE Exceptional Technical Achievement Award. In 2015 I was
`
`awarded the IEEE Components, Packaging, and Manufacturing Award.
`
`18. A copy of my curriculum vitae is included herein after my signature.
`
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`III.
`
`STATUS AS INDEPENDENT EXPERT WITNESS
`19. As noted above, I have been retained in this matter by Jones Day on
`
`behalf of Cree, Inc. to provide an analysis of the scope and content of U.S. Patent
`
`No. 7,256,486 (“the ’486 patent”) relative to the state of the art at the time of the
`
`earliest application underlying the ’486 Patent. In particular, my analysis relates
`
`only to claims 1-3. I have also been retained to provide analysis regarding what a
`
`person of ordinary skill in the art related to packaging for semiconductor-based
`
`light emitting devices would have understood at the time of the earliest application
`
`underlying the ’486 Patent.
`
`20.
`
`I am being compensated at the rate of $500 per hour for my work and
`
`$550 for any testimony. My fee is not contingent on the outcome of any matter or
`
`on any of the technical positions I explain in this declaration. I have no financial
`
`interest in Petitioner.
`
`21.
`
`I have been informed that Document Security Systems, Inc. (“Patent
`
`Owner”) owns the ’486 Patent. I have no financial interest in the Patent Owner or
`
`the ’486 Patent nor to my recollection have I ever had any contact with the Patent
`
`Owner, or the listed inventors of the ’486 Patent.
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`IV. MATERIALS CONSIDERED AND BASIS OF OPINIONS
`22. My opinions are based on more than 30 years of working with
`
`electronic packages and LEDs, as well as my teaching and research experience.
`
`My opinions are also based on investigation and study of the relevant materials,
`
`including the patents at issue and their file history, and the prior art. In the course
`
`of forming my opinions I have reviewed all the exhibits of record.
`
`23.
`
`I may rely upon these materials and/or additional materials to rebut
`
`arguments raised by the patent owner. Further, I may also consider additional
`
`documents and information in forming any necessary opinions – including
`
`documents that may not yet have been provided to me.
`
`24. My analysis of the materials relevant to this proceeding is ongoing
`
`and I will continue to review any new material as it is provided. This report
`
`presents only those opinions I have formed to date. I reserve the right to revise,
`
`supplement, and/or amend my opinions stated herein based on new information
`
`and on my continuing analysis of the materials already provided.
`
`V.
`
`DESCRIPTION OF THE RELEVANT FIELD AND THE RELEVANT
`TIMEFRAME
`I have carefully reviewed the ’486 Patent. For convenience, all of the
`25.
`
`information that I considered in arriving at my opinions is listed in Appendix A.
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`26. Based on my review of these materials, I believe that the relevant field
`
`for purposes of the ’486 Patent is packaging of semiconductor devices (die) and in
`
`particular semiconductor based light emitting diodes (LED) semiconductor
`
`devices.
`
`27.
`
`I believe the relevant timeframe for my analysis is approximately
`
`2003, which is the year during which the ’486 Patent was originally filed.
`
`28. As described above, I have extensive experience in the relevant field,
`
`including experience relating to the packaging of semiconductor light emitting
`
`semiconductor die. Based on my experience, I have an established understanding
`
`of the relevant field in the relevant timeframe.
`
`VI. THE PERSON OF ORDINARY SKILL IN THE RELEVANT FIELD
`IN THE RELEVANT TIMEFRAME
`I have been informed that “a person of ordinary skill in the relevant
`29.
`
`field” is a hypothetical person to whom an expert in the relevant field could assign
`
`a routine task with reasonable confidence that the task would have been
`
`successfully carried out. I have been informed that evidence of the level of
`
`ordinary skill in the art can be determined based on information about the field
`
`including: the types of problems encountered, known solutions, the speed of
`
`innovation, sophistication, and the educational level of active workers. I have
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`considered these types of information along with my own background working
`
`with students and other professionals in the field to reach my conclusion.
`
`30.
`
`It is my opinion that the person of ordinary skill in the art at the
`
`relevant would have had at least Bachelor’s Degree in mechanical or electrical
`
`engineering and at least two years of experience in the design of LED packages. A
`
`higher level of education, such as a Master’s Degree, in electrical engineering,
`
`could substitute for work experience and additional work experience could
`
`substitute for a degree.
`
`31. Based on my experience, I have an understanding of the capabilities
`
`of a person of ordinary skill in the relevant field. I have supervised, directed, and
`
`instructed many such persons over the course of my career.
`
`VII. OVERVIEW OF THE ’486 PATENT AND STATE OF PRACTICE
`32. A light emitting diode (LED) is a semiconductor device (also called a
`
`semiconductor die or chip) that emits light when powered. To protect the fragile
`
`semiconductor device and its connections, to aid in thermal management of the
`
`relatively high heat that is generated, and to aid in mounting the LED to a printed
`
`circuit board (PCB) or some other assembly, the LED die is packaged. The
`
`packaging of semiconductor devices is well known with a history of over 60 years,
`
`and I have authored and edited many books in this subject, the first being in 1991,
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`Handbook of Electronic Package Design, Marcel Dekker, New York, NY, 1991,
`
`and also the book Hannemann, R., Kraus, A., and M. Pecht, Semiconductor
`
`Packaging – A Multidisciplinary Approach, John Wiley, New York, NY, 1997.
`
`33.
`
`The traditional LED package consists of the LED die, which is
`
`mounted on a substrate (via a die bonding electrode), and electrically connected
`
`and routed around the substrate via a metal trace on one side of the substrate. The
`
`top of the die is connected to another electrode on the substrate via a wire bond,
`
`which in turn is routed around the substrate to the bottom of the substrate. The two
`
`(ground and power)1 parts of the routing trace on the bottom side of the substrate,
`
`serve as pads for surface mounting to a PCB, often with solder. The package is
`
`encapsulated with an optically transparent material to protect the die and the wire
`
`bond from moisture and mechanical damage (see Fig below showing a traditional
`
`LED package surface mounted to a PCB).
`
`1 Like a light bulb, only an electrical power and an electrical ground
`
`connection are needed.
`
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`34.
`
`The ’486 Patent pertains to a semiconductor package (e.g. packaging
`
`device (100)) where an LED semiconductor die (250) is mounted on a substrate
`
`110 (via die bonding electrode 130), and electrically connected to the bottom of the
`
`substrate by plated through holes (120 and 122). One plated through hole (120)
`
`electrically connects the die to ground and the other (122) connects the die to
`
`power via a wire bond (254). The package is encapsulated with an optically
`
`transparent material 252, and can be surface mounted to a PCB by terminals 140
`
`and 142, with solder. (See Fig 2 of the ’486 Patent below).
`
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`35. A key stated goal of the ’486 Patent is to provide a semiconductor
`
`packaging device that is smaller than the traditional LED package (to find an
`
`alternative to the wrap-around leads) and thus is comparable in volume with the
`
`semiconductor die and that is compatible with conventional printed circuit board
`
`assembly processes. Ex. 1001 (’486 patent) at 1:39-48.
`
`VIII. UNPATENTABILITY BASED ON PRIOR ART IN THE PRESENT
`PROCEEDINGS
`36.
`I am informed by counsel and understand that statutory and judicially
`
`created standards must be considered to determine the validity of a patent claim. I
`
`have reproduced the legal standards relevant to this declaration below, as provided
`
`to me by counsel as I understand them.
`
`37.
`
`I understand that a patent claim is invalid if it is anticipated or
`
`obvious.
`
`38. Anticipation: I understand that for a patent claim to be “anticipated”
`
`by the prior art, each and every limitation of the claim must be found, expressly or
`
`inherently, in a single prior art reference as recited in the claim. I understand a
`
`claim limitation not expressly found in a prior art reference is inherent if the prior
`
`art necessarily functions in accordance with, or includes, the claim limitation. Mere
`
`probability that a limitation is included is not sufficient to establish inherency.
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`39. Obviousness: I understand that a patent claim is not patentable for
`
`obviousness under 35 U.S.C. § 103 “if the differences between the subject matter
`
`sought to be patented and the prior art are such that the subject matter as a whole
`
`would have been obvious at the time the invention was made to a person having
`
`ordinary skill in the art to which said subject matter pertains.” 35 U.S.C. § 103. I
`
`understand that obviousness may be based on one reference and/or a combination
`
`of references. I understand that the combination of familiar elements according to
`
`known methods is likely to be obvious when it does no more than yield predictable
`
`results.
`
`40.
`
`I understand that when a patented invention is a combination of
`
`known elements, the Board must determine whether there was an apparent reason
`
`to combine the known elements in the fashion claimed by the patent at issue by
`
`considering the teachings of prior art references, the effects of demands known to
`
`people working in the field or present in the marketplace, and the background
`
`knowledge possessed by a person having ordinary skill in the art.
`
`41.
`
`I understand that a patent claim composed of several limitations is not
`
`proven obvious merely by demonstrating that each limitation was independently
`
`known in the prior art. I understand that identifying a reason those elements would
`
`have been combined can be important because inventions in many instances rely
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`upon building blocks long since uncovered, and claimed discoveries almost of
`
`necessity will be combinations of what, in some sense, is already known. I
`
`understand that it is improper to use hindsight in an obviousness analysis and that a
`
`patent’s claims should not be used as a “roadmap.”
`
`42.
`
`I also understand all prior art references are to be looked at from the
`
`viewpoint of a person having ordinary skill in the art at the time the invention was
`
`made.
`
`43.
`
`I understand that obviousness analysis requires consideration of: (1)
`
`the scope and content of the prior art; (2) the differences between the claims and
`
`the prior art; (3) the level of ordinary skill in the pertinent art; and (4) any objective
`
`indicia of non-obviousness, such as commercial success, long-felt but unresolved
`
`need, failure of others, industry recognition, copying, and unexpected results.
`
`44.
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`I understand that in order to prove that a claimed invention is not
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`patentable for obviousness, a petitioner must (1) identify the differences between
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`the claim and particular disclosures in the prior art references, singly or in
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`combination, (2) specifically explain how the prior art references could have been
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`combined in order to arrive at the subject matter of the claimed invention, and (3)
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`specifically explain why a person having ordinary skill in the art would have had
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`reasons to so combine the prior art references.
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`A.
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`45.
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`GROUND 1: CLAIMS 1-3 ARE OBVIOUS BASED ON
`JAPANESE PATENT APPLICATION PUBLICATION NO.
`2003-17754 (“ROHM”) ALONE OR IN VIEW OF U.S. PATENT
`NO. 5,376,580 (“KISH”)
`Japanese Patent Application Publication No. 2003-17754 (“Rohm”) is
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`entitled “Surface Mount Type Semiconductor Device” and pertains to a
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`semiconductor, light-emitting device (LED) package. In Rohm, an LED chip (die)
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`30 is mounted on substrate 12 (via a die bonding electrode 18) and electrically
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`connected to the bottom of the substrate by plated through holes (14 and 16). Ex.
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`1008 (“Rohm”) Abstract, Claim 1, ¶13, ¶14; see id. Figure 1. One plated through
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`hole (14 or 16) electrically connects the LED chip to a relatively negative voltage
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`and the other connects the LED chip to a relatively positive voltage. The package
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`is encapsulated with an optically transparent material 34, and can be surface
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`mounted to a printed circuit board (PCB) via pads 42a and 42b. (See Rohm Fig 1a
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`below). Id ¶¶ 7, 15, 19. A key stated goal of Rohm is to provide a semiconductor
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`packaging device that is smaller than the traditional LED package (to find an
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`alternative to the wrap-around leads of the prior art).
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`46. An LED chip 30 is connected by a bottom electrode (not pictured in
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`Figure 1) to mounting pad 18, and by wire 32 to bonding pad 20. Wire 32 is
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`connected to LED chip 30 by an electrode 30a. Ex. 1008 (Rohm) ¶16. The LED is
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`connected in a vertical arrangement, whereby one of the top and bottom surface is
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`connected to a relatively negative voltage via a cathode connection and the other is
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`connected to a relatively positive voltage via an anode connection.
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`47. Metallization layers are frequently and commonly used to provide
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`electrodes (electrical connections) to the types of components disclosed by Rohm.
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`See also Ex. 1001 (describing the metallization layer as “background” to the ’486
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`patent). This is true as a matter of convention—a metal electrode is a natural and
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`obvious choice for a conductive element in order to provide current to an LED.
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`48.
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`For example, U.S. Patent No. 5,376,580 (“Kish”) discloses a variety
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`of LEDs with two electrodes—one on the top surface and one on the bottom. See,
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`e.g., Ex. 1010 (Kish) Figs. 7, 12, 14, 15, 7:48-55; 9:64-66; 10:53-55; 13:30-33. The
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`patent states that these are “metallized electrodes for applying voltage to LEDs,”
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`id. at 5:19-21, and goes on to describe that formation (of upper and lower metal
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`electrodes) as “standard.” Id. at 7:48-55; see also id. at 9:64-66; 10:53-55; 13:30.
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`Indeed, like the ’486 patent, Kish depicts an LED with metalized layer electrodes
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`at its top (142) and bottom (144) surfaces. See, e.g., Id. at Figure 14, 7:48-55;
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`10:53-55; 13:30-33.
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`49. Moreover, U.S. Patent 6,791,119 (“Slater”) teaches that metal
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`electrodes are advantageous in the context of LEDs because metal with a reflective
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`surface reflects light that would otherwise be lost. Ex. 1012 (Slater) at 18:33-67.
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`Rather than be absorbed into a mounting pad, metalized layer electrodes reflect
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`light back in the direction the device intends to direct it.
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`50.
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`Thus, an ordinarily skilled artisan would have considered it well-
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`known, even “standard,” that metallized layers could be used as conductive
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`electrodes to provide current to LEDs.
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`CLAIM 1
`1.
`51. Claim 1 recites:
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`1. A semiconductor device, comprising:
`[a] a substantially planar substrate having opposed major surfaces;
`[b] an electrically conductive mounting pad located on one of the major
`surfaces of the substrate;
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`[c] a light emitting diode (LED) having a metallized bottom major surface
`that is mounted on the electrically conductive mounting pad, the metallized
`bottom major surface comprising one of an anode and a cathode of the LED;
`[d] a first electrically conductive connecting pad located on the other of the
`major surfaces of the substrate; and
`[e] a first electrically conductive interconnecting element extending through
`the substrate and electrically inter-connecting the mounting pad and the first
`electrically conductive connecting pad.
`The preamble of claim 1 recites “[a] semiconductor device.” Rohm,
`52.
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`too, is directed to a semiconductor device. This is disclosed in the title of Rohm
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`“Surface Mount Type Semiconductor Device” as well as in Claim 1, and
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`paragraphs 1, 6, and 7.
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`53.
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`The first element of claim 1 recites “a substantially planar substrate
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`having opposed major surfaces.” Figure 1 of Rohm shows a substantially planar
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`substrate, which is disclosed as “an insulating substrate 12.” Ex. 1008 (Rohm)
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`¶ 13. The substantially planar substrate 12 has opposed major surfaces on its top
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`and bottom, as “[t]he planar shape of the substrate 12 is rectangular.” Ex. 1008
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`(Rohm) ¶17. The planar substrate is also shown in figure 1 and is described, for
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`example, in the Abstract, Claim 1, and in paragraph 14.
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`54.
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`The second element of claim 1 recites “an electrically conductive
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`mounting pad located on one of the major surfaces of the substrate.” This
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`limitation is encompassed in Rohm, which discloses a “die bonding electrode 18 to
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`which the LED chip 30 is bonded” sitting atop substrate 12. Ex. 1008 (Rohm) ¶23;
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`see also id. at Abstract, Claim 1, ¶14. In Rohm, “a bottom surface electrode of
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`LED chip 30” is electrically connected to the die bonding electrode 18. Ex. 1008
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`¶16. Thus, because there must be an electrical current from the die to the ground on
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`the circuit board, die bonding electrode 18 (indeed all electrodes) must be
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`electrically conductive.
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`55.
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`The third element of claim 1 recites “a light emitting diode (LED)
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`having a metallized bottom major surface that is mounted on the electrically
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`conductive mounting pad, the metalized bottom major surface comprising one of
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`an anode and a cathode of the LED.” This element is echoed in Rohm which states
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`that “[a] top surface light-emitting type LED chip 30 is placed on and die-bonded
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`to the top surface of the die bonding electrode 18. A bottom surface electrode of
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`this LED chip 30 and the die bonding electrode 18 are electrically connected.” Ex.
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`1008 (Rohm) ¶16. Though Rohm does not actually state that the electrode is a
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`metalized layer, it would have been well known and obvious to a person of
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`ordinary skill in the art to use a metalized layer for that purpose. See ¶¶ 47-49
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`above (discussing the Kish and Slater patents and describing electrodes formed
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`from metalized layers as “standard”). In other words, LED chip 30 is electrically
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`connected to die bonding electrode 18 by the electrodes on each component. In an
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`electrical connection between two electrodes, one electrode is considered
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`positively charged (this is known as the cathode) and one electrode is considered
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`negatively charged (the anode). Thus, as in claim 1 of the ’486 patent, the
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`metalized bottom major surface of the LED chip 30 in Rohm functions as “one of
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`an anode and a cathode of the LED.”
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`56.
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`The fourth element of claim 1 recites “a first electrically conductive
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`connecting pad located on the other of the major surfaces of the substrate.”
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`Relative to the mounting pad, which is on top of the substrate the other major
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`surface of the substrate is the bottom. So too for Rohm, in which the die bonding
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`electrode 18 is on top of the substrate, and a conductive connecting pad containing
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`an electrode—”surface mount electrode 22”—is located underneath. Ex. 1008
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`(Rohm) Abstract, Claim 1; id. at ¶¶ 7, 14.
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`57.
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`The fifth element of claim 1 recites “a first electrically conductive
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`interconnecting element extending through the substrate and electrically
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`intercon