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`SOLID-STATE #74362.985
`CIRCUITS /
`Ee ESTARS PS
`FAST
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`9844834
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`14/01/7093
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`BOSTON SPA LS23 ?°BR
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`Volume 43:Number 12(2@88:Dec.)
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`IEEE JOURNALOF SOLID-STATE CIRCUITS
`The IEEE JOURNAL OF SOLID-STATE Circurts is published by the IEEE Solid-State Circuits Society. All LEEE members are eligible for membership and will receive this JOURNAL
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`

`

`IEEE JOURNAL OF
`SOLID-STATE
`CIRCUITS
`
`A PUBLICATION OF THE IEEE SOLID-STATE CIRCUITS SOCIETY
`
`
`
`DECEMBER 2008
`
`VOLUME43
`
`NUMBER12
`
`JSCBC
`
`(ISSN 0018-9200)
`
`SPECIAL ISSUE ON THE 2008 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC)
`
`Introduction to the SpecialIssue on the 2008 IEEEInternational Solid-State Circuits Conference ..........cccccccccccecececsecececee se.
`satay apne ibaa tease onacaaein ea wing canst pen: nay Yona wales ana Rca Sle TR TRH alata SRO es S. Tsukamoto, §.-1 Liu, S. Heinen, R. Thewes, and J. Lee
`
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`A Noise-Coupled Time-Interleaved Delta-Sigma ADC With 4.2 MHz Bandwidth, —98 dB THD, and 79 dB SNDR ssesie ti ceswcssvoace
`A aniaL AT NEeSEERRRT SRN OSA AMeECeMeEE ESOC K. Lee, J. Chae, M. Aniva, K. Hamashita, K. Takasuka, S. Takeuchi, and G. C. Temes
`A 14-b 100-MS/s Pipelined ADC With a Merged SHA and First MDAC.... B.-G. Lee, B.-M. Min, G. Manganaro, and J. W. Valvano
`An Over-60 dB True Rail-to-Rail Performance Using Correlated Level Shifting and an OpampWith Only 30 dB Loop Gain ..........
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`A 150 MS/s 133 pW 7 bit ADC in 90 nm Digital CMOS «2.0.20. oo cece cece ecececcececcucecenccuceccecce G. Plas and B, Verbruggen
`Highly Interleaved 5-bit, 250-MSample/s, 1.2-mW ADC With Redundant Channels in 65-nm CMOS ......0....cccccccccceeeceeeesccee.
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`264]
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`A 52 GHz Phased-Array Receiver Front-End in 90 nm Digital CMOS 00.0.0... 0c. ccecceccccucceusecuuceccccuuceueceeeecececeeecencceecce,
`iaae INES RA eESr K. Scheir, 8. Bronckers, J. Borremans, P. Wambacq, and Y. Rolain
`A Scalable 6-to-18 GHz Concurrent Dual-Band Quad-BeamPhased-Array Receiver in CMOS ...........cccccececcecececceeceeececesee,
`cmasgnnce ag dg ADURETT EL MUS MELT ITIS ORC dienes eo 5S. Jeon, ¥.-J. Wang, H. Wang, F Bolin, A. Natarajan, A. Babakhani, and A. Aajimiri
`Transmitter Architectures Based on Near-Field Direct Antenna Modulation ........... A. Babakhani, D, B. Rutledge, and A. Hajimiri
`A Compact Wideband Front-End Using a Single-Inductor Dual-Band VCO in 90 nmDigital CMOS .......0..00c.--cececceeeeeesceee ee.
`cigs wala wie W Ware aretaraatnemeare gewialawenaeeee J. Borremans, A. Bevilacqua, S. Bronckers, M. Dehan, M. Kuijk, P. Wambacq, and J. Craninckx
`The BLIXER, a Wideband Balun-LNA-I/Q-Mixer Topology ......::scssseeeeeecreeeeneeeuuscueceueceesstueseusstuesiteeceescsrseeeeccesccee.
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`Class-C Harmonic CMOS VCOs, With a General Result on Phase Noise ............ccccecececececececees A. Mazzanti and P. Andreani
`Terahertz CMOS Frequency Generator Using Linear Superposition Technique ........000.........cccsessesevececsceesecceceueseceeccccee.
`MERINOwae EEE D. Huang, T. R. LaRocca, M.-C. F Chang, L. Samoska, A, Fung, R. Campbell, and M. Andrews
`A 56-65 GHz Injection-Locked Frequency Tripler With Quadrature Outputs in 90-nm CMOS............. W. L. Chan and J. R. Long
`A Fully-Integrated Quad-Band GSM/GPRS CMOS Power Amplifier ........00..00..ccccccccccescceveeuesecsauscssetesestuteceseeseccsee.
`eracarestigceraeinieeareacneemersd lit gree
`I, Aoki, S. Kee, R. Magoon, R. Aparicio, F. Bohn, J. Zachan, G. Hatcher, D. McClymont, and A. Hajimiri
`2747
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`7—_—_—_—_"eha»,ll
`ANALOG AND WIRELESS COMMUNICATION PAPERS
`
`2651
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`2706
`2716
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`2730
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`A Field-Programmable Analog Array of 55 Digitally Tunable OTAsin a Hexagonal Lattice 20.0... ooo... ceececececcuccecceccecceucecce.
`Me errr errr er rrr rrr Rrra J. Becker, F. Henrici, S$. Trendelenburg, M. Ortmanns, and Y. Manoli
`A Current-Feedback Instrumentation Amplifier With 5 j:V Offset for Bidirectional High-Side Current-Sensing ......cccc;eeceseeneures
`cca eeeuuaeeetvnccecnneetseteteeecuneennaeeseeeeetenseessueeeesenseeetsreteeneteeeeunaaees J. F. Witte, J. H. Huijsing, and K. A. A. Makinwa
`
`2759
`
`2769
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` "
`
`IEEE
`
`iii
`
`

`

`OOOO
`A Low-Noise Wide-BW 3.6-GHz Digital A Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter
`and Quantization Noise Cancellation 2.0.20... 0.0... ..ccccecccceceececuseuueveeuucuaenuee C.-H. Hsu, M. Z. Straayer and M. H. Perrott
`Spurious Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4 GHz Fractional-N PLL ...........c000ceceeeceeeeeeeeneeeeeees
`SARA eR RRR NS RRR RINE REELS Ep EN eae ana TalON a Ma Tee oU alata td BaTRMET SEES GEES SET SEER. laniog SSS K. J. Wang, A. Swaminathan, and £ Galton
`Load-Independent Control of Switching DC-DC Converters With Freewheeling Current Feedback .........0.cc0ecesesereceeeeceeee teens
`Stegrrea ane ea rae y uN REET ER PRERIOIST pTSG TEs dee naenenencanemenuaeaecas ¥-J. Woo, H.-P. Le, G.-H. Cho, G.-H. Cho, and S.-1, Kim
`A 10 MHz Bandwidth, 2 mV Ripple PA Regulator for CDMA Transmitters .................-+ W-Y. Chu, B. Bakkaloglu, and 8. Kiaei
`A Pulse-Based Ultra-Wideband Transmitter in 90-nm CMOS for WPANS...........ccceccecececeeeeees M. Demirkan and R. R. Spencer
`A Fully Integrated 14 Band, 3.1 to 10.6 GHz 0.13 jm SiGe BICMOS UWBRE Transceiver ..........csceccecsuceceneeueccceseeetseecess
`{VieNTS O. Werther, M. Cavin, A. Schneider. R. Renninger, B. Liang, L. Bu, ¥. Jin, J. Rogers, and J. Marcincavage
`UWBFast-Hopping Frequency Generation Based on Sub-Harmonic HUjCCON LOCKIBE: siscsecsnsenernnnenecaneeenensncenersens unease sneies
`srnmaebneds aeeheenens td PULTE CANA Aa eeneens S. Dal Toso, A. Bevilacqua, M. Tiebout, 8. Marsili, C. Sandner, A. Gerosa, and A, Neviani
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`A Low-Power WCDMA Transmitter With an Integrated Notch Filter .............0..ccccceceeeceececeusveuees A. Mirzaei and H. Darahi
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`K. Gang, B. Vakili-Amini, J. A. Hwang, S. Chen, M. Terrovitis, B. Kaczynski, §, Limotyrakis, M. P. Mack, H. Gan, M. Lee, R. Chang,
`H. Dogan, S. Abdollahi-Alibeik, B. Baytekin, K. Onodera, S. Meniis, A. Chang, ¥. Rajavi, 8. H. Jen, D. K. Su, and B. A. Wooley
`A Single-Chip CMOSBluetooth v2.1] Radio SoC ........ccecscssccuceucecesceccoscuceecnsctseecuucucuuecsensaectsauctsseeavanses WW Si,
`D. Weber, S. Abdollahi-Alibeik, M. Lee, R. Chang, H. Dogan, H. Gan, Y, Rajavi, S. Luschas, 8. Ozgur, P. Husted, and M. Zargavi
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`2776
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`2798
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`2882
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`2896
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`aW
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`Bandwidth occ cceccesese M. Kossel, C. Menolfi, J. Weiss, P. Buchmann, G. von Bueren, L. Rodoni, T. Morf, T. Toifl, and M. Schmatz
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`A 40-Gb/s CDR Circuit With Adaptive Decision-Point Control Based on Eye-Opening Monitor Feedback ............000c cece eeeee ees
`da aie eter Cee RIE Ree Le ae MEy emeTRNNNR WHat SicatalateneTe ete TONS H. Noguchi, N. Yoshida, H. Uchida, M. Ozaki, §. Kanemitsu, and S. Wada
`A 901m CMOS DSP MLSD Transceiver With Integrated AFE for Electronic Dispersion Compensation of Multimode Optical Fibers
`AUTO GDIS 0... ee cece ec eee cece e ccc ee ec ec ee eneesneeeeeseee ener eneeeucabavegeuauneessntesntneaeueseenseseetsttntneateneens O. E. Agazzi,
`M. R. Hueda, D. E. Crivelli, H. §. Carrer, A. Nazemi, G. Luna, F. Ramos, R, Lopez, C. Grace, B. Kobeissy, C. Abidin, M. Kazemi,
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`Low-Spur, Low-Phase-Noise Clock Multiplier Based on a Combination of PLL and Recirculating DLL With Dual-Pulse R ing Oscillator
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`2967
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`A 5: W/Channel Spectral Analysis IC for Chronic Bidirectional Brain-MachineInterfaces ............---.ececccceceeeeeeecececceceee..
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`A 200 y)W Eight-Channel EEG Acquisition ASIC for Ambulatory EEG Systems.........2.2.ccceceececececususausscessetseereuasusavenes
`Sen ene eee eee een tect rena eens e eet eneseseneetuaeseeecnevenueennaseus R. F. Yazicioglu, P. Merken, R. Puers, and C. Van Hoof
`A Mode-Matching SA Closed-Loap Vibratory Gyroscope Readout Interface With a 0.004°/s/\/Hz Noise Floor Over a 50 Hz Band...
`3039
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`This material may be protected by Copyright law (Title 17 U.S. Code)
`
`

`

`2810
`
`IEEE JOURNALOFSOLID-STATECIRCUITS, VOL. 43, NO. 12, DECEMBER 2008
`
`'
`
`oe ee cee ctee
`
`DSP
`
`
`7
`| 2 s§
`=
`5
`Modulator
`
`
`| 2 = a
`RF envelope
`
`
`ies
`£24. g
`oO ©
`oO
`Var)
`5
`|
`
`
`RF output
`-
`to antenna
`
`RF
`Carrier, ®,
`
`Fig. 2, Typical polar modulation based transmitter block diagram.
`
`CDMAPSD(dBc)
`Composite
`PSD‘(dBc)
`
`CDMAenvelope
`
`Frequency (MHz)
`(b)
`
`Fig. 3. Power spectral density (PSD) of(a) composite CDMAsignaland(b) its
`extracted envelope.
`
`using an accurate current sensing technique, efficiency and lin-
`earity of the supply modulator is further optimized. The organ-
`ization ofthis paper is as follows: Section II describes the op-
`eration of the PA supply modulator and techniques for perfor-
`mance optimization. Section III details the circuit level imple-
`mentations ofthe lincar amplifier, switch-mode regulator and
`current sensing circuit. The measurement setup and results are
`presented in Section IV, followed by a conclusion in Section V.
`
`II. DESIGN OF MASTER-SLAVE PA REGULATOR
`
`A, Operation
`Fig. 4 showsthe block diagram ofthe proposed master-slave
`linear and switch-mode combined supply modulator loaded
`
`with a PA. A high GBW linear amplifier in voltage follower
`configuration ensures that output node V,(é) tracks the refer-
`ence envelope voltage A(t). A current sensing circuit, high gain
`transimpedance amplifier and switch-mode regulator forms a
`global feedback control loop that suppresses the current output
`from the linear amplifier within the switch-mode regulator
`bandwidth, Consequently, a large portion of the load current is
`provided by the switch-mode regulator. The lower efficiency
`linear amplifier sources small amounts of output current Jjj,(€)
`to cancel out switch-moderegulator ripple and high frequency
`signal content. The transient response ofcurrents at the output
`of the switch-mode regulator J,,,(é), the linear amplifier Jy, (é)
`and combined master-slave supply modulator J,(t) is shown
`in Fig. 5. Assuming an infinite GBW linear amplifier,
`this
`architecture will generate a ripple free output current [,(¢) to
`the load. However, due to finite GBW ofthe linear amplifier,
`only the ripple energy within the linear amplifier is cancelled.
`This tradeoff between GBW of linear amplifier and ripple size
`will be discussed later,
`To gain further insight on the operation of master-slave
`supply modulators,
`the current-mode frequency response of
`the linear amplifier, switch-mode regulator, and their com-
`bined response are analyzed. The steady state output current
`of switch-mode regulator J,,,, can be defined by the linear
`regulator current J}; as follows:
`
`Ign =
`
`iy
`1
`fie jy beEy
`
`where nis the current sense ratio, A,j, is the transimpedance
`gain, S,. is the slope of the ramp in the switch-mode regulator
`and /?, is the equivalent PA load resistance. The sensed current
`is amplified by the transimpedance amplifier, comparator and
`the voltage divider formed by equivalentseries resistance (ESR)
`of the loading inductor and resistive component /?, of the PA
`load. The second-order LC filter and the ESR set the dominant
`
`pole location of the frequency response.
`From (1), we can derive the transfer function of the combined
`output current [, as follows:
`
`l
`2
`iy
`SO ey pe
`A
`Ek
`i+ 2Abin
`
`(2)
`
`

`

`CHUet al.: PA REGULATOR FOR COMA TRANSMITTERS
`
`2811
`
`Envelope
`Alte
`
`Supply Modulator
`
`
`
`Class AB
`ranslinea
`
`Biasing
`
`
`amp
`Class AB Output} Volt
`Switch
`Mode Output
`
`
`Fig. 4. The proposed master-slave linear and switch-mode PA regulator block diagram.
`
`Current Loop
`Response, K(f)
`
`
`
`
`Linear
`Amplifier
`
`
`
`
`PA Load
`
`
`lealt)AGATA |e
`la) APSA 0
`
`
`I,tt)
`
`Fig. 5. Simplified block diagramofthe proposed regulator showingripple cancellation.
`
`is the
`where Arepresents the input envelope signal and Ajj,
`open loop gain of the linear amplifier. The switch-mode regu-
`lator output current J.,, can be shown as
`
`Tem _
`l
`
`1
`
`l
`
`a
`
`
`
`Current(mA}
`
`700
`600
`
`1
`
`andfinally the linear amplifier output currentJjj,, is represented
`by
`fin_n+ S,-(L+s?+L-C) 1
`
`
`(4)
`A”
`Atia
`, 1+ = ‘
`As shown in (3) and (4),
`the output current response ofthe
`switch-mode amplifier has a two-poletransfer function forming
`a second-order low-pass characteristic, while the output current
`responseof the linear amplifier has a two-zero transfer function
`that contains a second-order high-pass characteristic. At low fre-
`quencies, the linear amplifier current output is suppressed and
`the switch-mode regulator dominates the output current. Con-
`versely, at high frequencies, the switch-mode regulator current
`responsestarts rolling off and the linear amplifier takes over the
`output current. The switch-mode regulator and linear amplifier
`current response combine and forma flat frequency response for
`the master-slave regulator. The frequency where switch-mode
`regulator current responserolls off and linear amplifier current
`response takes overis called transition frequency, fi. This [re-
`quency plays an important role on efficiency optimization and
`will be discussed in the next section.
`
`100
`
`1K
`
`1M
`
`Frequency (Hz)
`
`Fig. 6, Current-mode frequency response ofthe linear amplilier, the switch-
`mode regulator and the master-slave combined regulator.
`
`Fig. 6 plots the current-mode frequency responseofthe linear
`amplifier, switch-mode regulator and master-slave regulator. As
`predicted in the mathematical analysis, second-order low-pass
`and high-pass characteristics were obtained. The resulted flat
`output current responseis suitable for high linearity implemen-
`tation. In addition, the overall bandwidth extended by the linear
`amplifier makes the supply modulator suitable for wide band-
`width signal transmission.
`
`

`

`2812
`
`IEEE JOURNALOF SOLID-STATE CIRCUITS, VOL. 43, NO. 12.DECEMBER 2008
`
`
`
`Low F,
`
` Frequency
`(a)
`
`lem €f)
`
`lan (FS
`
`PSD(dBe),Current(mA)
`
`
`PSD(dBc),Current(mA)
`
`_ 20
`
`i)
`
`
`{ Af|
`
`aa
`
`Qono
`ao
`sawu
`
`2 5e£z
`
`tne
`~&#50
`
`0
`
`10
`
`40
`
`30
`20
`Frequency (MHz)
`(a)
`rs20 |
`
`sai
`
`oO
`
`o
`
`z Q
`
`2 -80)
`o
`|
`
`o
`-20 |
`o
`|
`60 at
`:
`a
`-40|
`5
`yallVet
`zm
`
`
`-120 |
`
`0 40~°&#5010 20 30
`
`
`
`Frequency (MHz)
`(b)
`
`Fig. 7. Ripple energy fora 10 dBm. 100 kHz SSB suppressedcarrier modula-
`tion waveformfor (a) a synchronousrectifier versus (b) a hysteretic controller.
`
`B. Performance Optimization
`
`Master—slave regulator configuration is commonly used for
`audio amplifiers, and for these applications a switch-mode
`regulator is typically configured in hysteretic control mode.
`Hysteretic controllers do not need a clocked comparator; instead
`they use a window comparator, and frequency of operation
`depends onthe load conditions. The loop response ofhysteretic
`controllers is quite fast during load transients. However, this
`variable frequency operation generates wideband spurious
`emissions at the regulator output. This in turn increases the AC
`power from the linear amplifier since more ripple energy falls
`within class-AB amplifier bandwidth. The two powerspectral
`density plots in Fig. 7 represent the ripple energy for a 10 dBm,
`100 kHz single sideband (SSB) suppressed carrier modulation
`waveform for a synchronous rectifier versus a hysteretic con-
`troller. As shown in this figure. the integrated ripple energy
`within the class-AB bandwidth is much higherfor a hysteretic
`controller. For wideband modulation schemes,
`this analysis
`shows that synchronousrectifiers are a better choice for low
`power, low spurious emissions design.
`To optimize the efficiency of a PA supply modulator, two
`properties of the envelope signals should be considered: the
`power level probability density function (PDF) discussed in
`Fig.
`| and powerspectral density (PSD). As shown in Fig. 3,
`
`
`High F,
`Frequency
`(b)
`
`Fig. 8. Portion of CDMA spectrumamplified by linear amplifier and switch-
`mode regulator at (a) low fy and (b) high fr.
`
`the envelope PSD contains high DC content and most ofthe
`envelope energy is accumulated at frequencies less than 2 MHz
`with a small portion of the envelope energyrolling offat higher
`frequencies, The bandwidth specifications of the switch-mode
`regulator can be relaxed further reduce the switching losses and
`use the linear amplifier to amplify the high frequency portion
`of the signal. However,as the bandwidth ofthe high efficiency
`switch-mode regulator becomes too low,
`the low efficiency
`linear amplifier dominates the output current, reducing overall
`efficiency. Fig. 8 showsthe portions of the envelope spectrum
`amplified by the linear amplifier and switch-mode regulator
`with different transition frequencies fr. Fig. 9 shows that peak
`efficiency of the supply modulator with a 20 dBm, 400 kHz
`SSB suppressed carrier modulated input waveform is achieved
`at 100 kHz fr.
`As discussed earlier, output ripple is another critical spec-
`ification requirement for PA supply modulator design due to
`stringent ACPR and spurious emission requirements. [8].
`In
`the proposed master-slave linear and switch-mode regulator,
`a significant portion of current ripple from the switch-mode
`
`

`

`2813
`
`Vo
`
`Vow
`
`T
`
`
`— Vewn -D — Vow
`Ve D
`Vy
`
`Veet
`
`Ramp
`V(t)
`
`“MW ‘omparator
`
`c
`
`G.= Ve
`“Vet
`
`Fig. 11. Gain calculation in comparator. D is the duty cycle of Vawm(t)-
`
`A(l)
`
`
` Current
`
`Sensor
`
`
`Comparator
`[
`
`Linear Model
`
`
`
`. 12. Linear model for master-slave linear and switch-mode regulator,
`
`a8
`
`008
`
`;
`Transimpedance
`amplifier
`
`1008Lo Comparator
`
`odB
`
`LC fiter
`
`400B
`
`es
`sv
`
`Combined
`response
`
`Individual block and the combined frequency responses in switch-
`Fig. 13.
`mode regulator feedback loop.
`
`0 dB and used —55 dBe per 30 kHz bandwidth ACPR require-
`ments to extract a maximum ripple specification of 2 mVp,
`at the overall regulator output [8]. As shown in Fig. 10(c), as
`the linear regulator unity gain-bandwidth increases, the voltage
`ripple at
`the output reduces, with the expense of reduced
`efficiency and increased linear regulator power consumption.
`For a given 2 mV,, ripple specification at a typical 16 dBm
`output power level, a linear regulator unity gain-bandwidth of
`100 MHz is selected.
`
`C. Switch-Mode Regulator Feedback Loop
`
`The switch-mode regulator feedback loop includes a current
`sensing circuit, an error amplifier, a comparator, power stage and
`a low-passfilter and is designed with maximum loop gain for
`
`CHUet al.: PA REGULATOR FOR CDMA TRANSMITTERS
`
`48
`
` -+fBs&§Efficiency(%)
`
`10
`
`100
`
`1000
`
`Transition frequency F, (kHz)
`
`Fig. 9. Efficiency optimization of a 20 dBm, 400 kHz SSB suppressed carrier
`modulation envelope waveformby varying transition frequencyfy.
`
`rso
`
`(mV)
`Outputripple
`
` 0
`
`
`Outputripple(mV)
` Output
`
`ripple(mV)
`
`0
`
`20
`
`60
`40
`Inductance (uH)
`
`80
`
`100
`
`:
`-
`9 10MHz
`Switching frequency (MHz)
`
`100
`
`>
`
`0
`
`50
`100
`Supply modulator BW (MHz)
`
`150
`
`10, Peak-to-peak output voltage ripple versus
`Fig,
`(b) switching frequency, and (c) linear amplifier GBW.
`
`(a)
`
`load inductor,
`
`regulator is cancelled by the linear amplifier. This results in a
`much smaller residue voltage and currentripple at the PA drain.
`Output inductor and switching frequency also play an important
`role on output ripple value. Fig. 10(a) and (b) shows output
`ripple versus load inductor and switching frequency for the
`proposed composite regulator. Since both ripple frequency and
`output filter corner is determined by the transition frequency,
`these parameters cannot be used for ripple optimization. There-
`fore, the effectiveness ofcurrent ripple cancellation depends on
`the GBWof the linear amplifier. For the ripple specification, we
`have assumed a worst case PA power supply rejection (PSR) of
`
`

`

`2814
`
`IEEE JOURNAL OF SOLID-STATECIRCUITS. VOL. 43, NO. 12. DECEMBER 2008
`
`
`
`Output Stage
`
`Rail-to-rail
`Input Stage
`
`Class AB
`Translinear Biasing
`
`Fig. 14. Rail-to-rail input linear class-AB amplifier with common-source outputstage in voltage follower configuration for ripple cancellation and master-slave
`supply modulator bandwidth extension.
`
`
`| linkt)=lougt{tlout)
`— lgn(t)
` V(t) : voltage is set
`
`
`by linear amplifier
`
`To PALoad
`
`Fig. 15. Switch-mode regulator in master-slave supply modulatorfor high efficiency amplification.
`
`accurate envelope tracking and highest linear amplifier output
`current suppression. For AC analysis, a linear model is utilized.
`As shownin Fig. 11, linearized gain of the comparator is defined
`by the ratio ofits output voltage swing to the amplitude ofits
`rampinput. Viwm(#) is the switching version of V, (¢) that has
`equal magnitude but containsstronger and more high-frequency
`harmonics. A linear model is obtained and Fig. 12 shows the
`linearized model of the system.
`In the comparator design a ramp voltage swing of 0.3 V is
`used,yielding an equivalent gain of 10. This gain is optimized
`in such a way that there is minimum penalty to the loop band-
`width and phase margin. The disadvantage of using a smaller
`ramp voltage is the increased comparator response time. This
`delay results in degradation in envelope tracking accuracy of the
`switch mode output current and consumes morelinear amplifier
`output current to correct the time delayerrors. Furthermore, ex-
`cess comparator delays degrade the phase margin ofthe feed-
`back loop around the combined regulator. In this design, with
`the switching frequency of the supply modulator at 10 MHz
`and a comparator BW of 96 MHz, the comparator achieves a
`response time ofless than 6 ns. The delay introduces a phase
`shift of less than 1° and requires almost no extra current from
`the linear amplifier.
`To ensure the stability of the feedback loop in the switch-
`mode regulator, the bandwidth of the switch-mode regulating
`
`loop should be at least ten times less than the switching fre-
`quency. The limited operating bandwidth filters the high fre-
`quency contents ofthe output current ripple and preventsinsta-
`bility. To minimize current use from the linear amplifier, close
`loop gain should be high. Thereis also a gain-attenuation at the
`outputofthe switch-moderegulator: the ESR andresistive load
`form a voltage divider that degrades the loop gain. Small ESR
`is preferred to minimize attenuation and power losses.
`Fig. 13 plots the frequency response ofcach block inside the
`switch-mode regulating loop. It showsthat the total current to
`voltage conversion gain of current sensing and transimpedance
`stage is approximately 30 dB, followed by a comparator gain of
`10 dB yielding an in-band gain of 40 dB. The transimpedance
`error amplifier and comparator are designed to have wide BW.
`Their poles should place beyond the GBW ofthe switch-mode
`regulator. The loading inductor sets the GBWofthe close loop
`below switching frequency.
`
`If]. Cigcuir IMPLEMENTATION
`
`A. Linear Amplifier
`
`A two-stage class-AB amplifier with a common-source
`output stage, as shown in F