11 IB I I 11111111111111111! I
`
`US005796376A
`[111 Patent Number:
`(45) Date of Patent:
`
`5,796,376
`Aug. 18, 1998
`
`United States Patent 1191
`Banks
`
`[54] ELECTRONIC DISPLAY SIGN
`
`[75)
`
`Inventor: Archie A. Banks. Prince Edward
`Island. Canada
`
`[73) Assignee: CIE Research, Inc •. Prince Edward
`lslaod. Canada
`
`[21) Appl. No.: 422,701
`Apr. 14 , 1995
`
`[22) Filed:
`
`Related U.S. Application Data
`
`[51]
`
`(63) Cootinuation of Ser. No. 406.660. Mar. 20. 1995. abaJl(cid:173)
`doued. which is a couti.nualioo of Ser. No. 149.714. Nov. 9.
`1993. abandoned. which is a continuatie>n of Ser. No.
`809.670. Dec. 18. 1991. abaodooed.
`Int. Cl.6
`••.......•.......•••..•..••••... B41J 2/JOS: B4IJ 2101:
`B41J 3/00: B41J 29/38
`[52] U.S. Cl ...................................... 34S/82; 345/1: 345/4:
`345/903
`[58) Field of Search ............................. 345/82. l. 2. 4----o.
`345/903: 84IJ 2/105. 2/01. 3/00. 29/56
`
`[56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`5/1974 Ogle .
`3 ,811 ,071
`4,006,476 2/1977 Rommey .
`4,384,279
`5/1983 Fujita .
`4/1984 Ichikawa et al . .
`4,445,132
`
`4581.612
`4.745.-1().1
`4.771.278
`4.825201
`4.833542
`4.897.651
`4.901.155
`5.079.636
`5.136.695
`
`-I/ 1986 Jones .
`5/1988 Kallenberg .
`9/ 1988 Pooley .
`-111989 Watanabe et al
`511989 Hara et al . .
`111990 DeMonle .
`2/1990 Hara et al ..
`1/1992 Brody .
`811992 Goldshlag et al ..
`
`FOREIGN PATENT DOCUMEJ\'TS
`
`0242742 10/1987 European Pal. Off . .
`0247377 12/1987 European Pal. Off ..
`3513607 10/1986 Germany .
`
`Primary Examiner- Mark R. Powel.I
`Assistant Examiner-Vivek Srivastava
`Anome)\ Agent. or Fi~Andrus. Sceales. Starke &
`Sawall
`
`[57)
`
`ABSTRACT
`
`An electtoruc display sign constructed around a system bus
`architeclUie is disclosed. The elcctronk display sign is
`preferably a modular construction wherein a number of
`m odules are connected together to form a large display sign
`which is capable of displaying images at rates which exceed
`thirty frames a second. Display data is fonnaned and trans(cid:173)
`mined to display modules by a sign controller which resides
`on one of the panels. Each display panel is preferably
`provided with its own power source.
`
`30 Claims, 7 Drawing Sheets
`
`22
`
`Sign
`Controller
`
`20
`)
`
`24
`
`SYSTEM BUS
`28-·--·· ·mspiaf Display
`Panel2
`Panel 1
`
`•
`
`26
`
`26
`
`•
`
`Display
`Panel N
`
`26
`
`(cid:47)(cid:50)(cid:58)(cid:40)(cid:54) 1014, Page 1
`
`VIZIO Ex. 1014 Page 0001
`
`

`

`U.S. Patent
`
`Aug. 18, 1998
`
`Sheet 1 of 7
`
`5,796,376
`
`22
`
`Sign
`Controller
`
`SYSTEM BUS
`
`20
`
`)
`
`24
`
`28······ -~~~~f ( Display
`Panel2
`26 FIG. 1
`
`26
`
`•
`
`•
`
`Display
`Panel N
`
`26
`
`r - - - - -
`
`30
`
`Display
`Generator
`
`L __
`
`26
`26
`24 Bus 1 Panel1
`- -
`- !Panel 321
`26
`26
`Bus 2
`Panel 1 - -
`- !Panel 321
`26
`26
`Panel 1 - -
`- !Panel 32r
`26
`26
`Panel 1 - -
`- !Panel 32r
`
`Bus3
`
`Bus 4
`
`22
`
`Sigri
`Controller
`
`24
`
`32
`
`External
`Control
`
`FIG. 2
`
`(cid:47)(cid:50)(cid:58)(cid:40)(cid:54) 1014, Page 2
`
`VIZIO Ex. 1014 Page 0002
`
`

`

`U.S. Patent
`
`Aug. 18, 1998
`
`Sheet 2 of 7
`
`5,796,376
`
`42
`
`CPU
`
`34
`Display &
`Scratch Pad
`Memory
`(DRAM)
`
`40
`
`DUART
`
`44
`Program
`Memory
`
`22
`
`..... (_EP,.....,RO,.....M ....... ) )_~----.
`
`.__ _
`
`Bus
`___. - - - - -~ .---- Driver #1
`CONTROLLER BUS
`48 ..__,---=-----,
`Bus
`----- Driver #2
`
`Parallel
`lntertace
`
`OMA
`
`Timer
`
`36
`
`38
`
`46
`FIG. 3
`
`Bus
`---~ Driver #3
`48 <-r---::----. 2 4
`Bus
`- - - Driver #4
`
`(cid:47)(cid:50)(cid:58)(cid:40)(cid:54) 1014, Page 3
`
`VIZIO Ex. 1014 Page 0003
`
`

`

`U.S. Patent
`
`Aug. 18, 1998
`
`Sheet 3 of 7
`
`5,796,376
`
`CPU ---
`4~
`
`5~2
`
`IN
`Address/
`Data Bit
`1ouT
`
`MSB 9-bit
`FIFO Read MSB
`MSB
`
`-Bit 9
`
`Bit 1 Out
`
`)
`
`50 s Read LSB
`
`9-bit
`FIFO
`LSB
`
`LSB
`
`Bit 9
`
`Bit 9 Out
`
`FIG. 4
`
`8 bit Bus
`)
`24
`
`State
`Machine
`
`LED_DS
`~
`LED_AS
`~
`Reset
`~
`
`)
`54
`
`LED
`Panel
`Display
`
`26
`
`58 ~~- .--~----. 56
`Panel ___ Power
`Controller
`Supply
`
`24
`
`24
`
`Bus In
`
`Bus Out
`
`FIG. 5
`
`(cid:47)(cid:50)(cid:58)(cid:40)(cid:54) 1014, Page 4
`
`VIZIO Ex. 1014 Page 0004
`
`

`

`24
`AJD BUS IN
`
`BUS
`BUFFER
`
`60
`
`62
`
`LOAD
`BUFFER
`
`60
`64
`
`70
`
`68
`
`66
`
`LATCH
`REFRESH
`PIXELS 1-84 ARRAY PANEL DATA BUFFER
`
`PANEL DATA
`
`PANEL
`RAM
`
`RAM ADDRESS CONTROLLER
`
`74
`DODOO
`76
`DODOO
`
`LATCH CONTROL
`._SE-CT-OR-1-_J8 DRRSIV2E3R2S ~---------,;-;:;:;,:;:;:;;:;-;~; : - - - - - -__ J
`SECTOR DRIVE
`
`~
`58
`
`72
`
`FIG. 6
`
`(cid:47)(cid:50)(cid:58)(cid:40)(cid:54) 1014, Page 5
`
`VIZIO Ex. 1014 Page 0005
`
`

`

`U.S. Patent
`
`Aug. 18, 1998
`
`Sheet S of 7
`
`5,796,376
`
`COL. 1
`
`78
`
`78
`
`80
`ROW 1 >-----I »----+--+---+-____,
`80
`ROW 2 - - » - - - -+ - - -+ - - - - - '
`80
`ROW 3 - - >----4----+-------'
`80
`ROW 4 >----t ..,... _ ____________ __,
`
`FIG. 7
`
`(cid:47)(cid:50)(cid:58)(cid:40)(cid:54) 1014, Page 6
`
`VIZIO Ex. 1014 Page 0006
`
`

`

`U.S. Patent
`
`Aug. 18, 1998
`
`Sheet 6 of 7
`
`5,796,376
`
`- -~~ -
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`I
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`(cid:47)(cid:50)(cid:58)(cid:40)(cid:54) 1014, Page 7
`
`VIZIO Ex. 1014 Page 0007
`
`

`

`U.S. Patent
`
`Aug. 18, 1998
`
`Sheet 7 of 7
`
`5,796,376
`
`<O
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`(cid:47)(cid:50)(cid:58)(cid:40)(cid:54) 1014, Page 8
`
`VIZIO Ex. 1014 Page 0008
`
`

`

`J
`ELECTRONIC DISPLAY SIGN
`
`5.796.376
`
`This application is a continuation of Ser. No. 08/406.660.
`filed Mar. 20. 19'J5. now abandoned which was a file
`wrapper continuation of Ser. No. 08/149.7 14. filed Nov. 9.
`1993. which was a file wrapper continuation of Se.r. No.
`07/809.670. filed Dec. 18. 1991. now abandoned.
`The present invention relates 10 electronic display signs
`and in particular to a novel modular electronic display sign
`which may include one or more display panels that are 10
`connected to a sign controller by a system bus.
`
`BACKGROUND OF THE INVENTION
`
`2
`by switching XY coordinates of a voltage grid which powers
`the display sign. Although this architecture appears to permit
`the construction of a sign which yields an improved perfor(cid:173)
`mance over the more traditional shift register circuit it is
`5 nonetheless a complicated system which requires the switch(cid:173)
`ing of substantial amounts of power. Advances in LED
`technology have made electronic display signs more attrac(cid:173)
`tive because new high inte nsity red LEDS which are now
`wide!>· available from a number of suppliers output at least
`fifteen candellas of light energy. Signs constructed with
`these new LEDS are clearly visible in daylight conditions
`permi"ing outside installations of display signs which are
`effective at any time of day. The currenUy available sign
`technology is not very conducive to the exploitation of the
`tS improved power of LEDS because the lack of speed and
`Hexibility of the display sign does not permit very innova(cid:173)
`tive use of such signs as advertising tools. There therefore
`exists a need for a fast. powerful electronic display sign
`architecture which permits the innovative use of electronic
`io display signs as an entertaining advertising medium.
`
`Electronic display signs of a type which display images or
`text messages as points of light arewelJ knowo in the art.
`Such signs are commonly seen in public places. Display
`signs of this type generally use LEDs (light ernittiog diodes)
`as light sources because of their long term re.liability and low
`power consumption.
`Normally electronic display signs comprise a panel of
`light sources arranged in a matrix panern of rows and
`columns. Such signs are usually relatively small but large
`signs having a dimension of at least 10 feet (3.3 meters) per
`side are sometimes constructed. Because of their size and
`complexity large display signs are difficult and expensive to
`construct. The construction of large display signs also pre(cid:173)
`seots special design problems because of their power con(cid:173)
`sumption requirements since illuminating a lacge number of
`independent light sources requires a considerable electric 30
`power supply and robust switching equipme nt.
`Traditionally. large display signs have been constructed
`around an electric circuit which includes shift registers foe
`powering oo selected light sources in rapid ~uccession in
`order to minimize the power consumption and power
`switching requirements of the sign. There are some disad(cid:173)
`vantages to using shift register circuits in such, app.licatioos.
`however. First. signs built with shift registe:r circuits are
`relatively slow and only genuinely effective foe displaying
`scrolli.og. flashing or static character data. True animation 40
`and/or a simultaneous full power on of each LED in the
`matrix are not possible. Signs powered by shift registers are
`therefore limited in their ability to display images for visual
`effect
`In order to facilitate the assembly. transpo.111 and iostalla(cid:173)
`tioo of large display sigos. it is desirable to desigo such signs
`as modular units which may be iotercoDDected to form a sign
`of a desired modular dimension. Modular display signs are
`known. Gennan patent 35 13 607 which issued to Lumioo
`Licht Elektronik GmbH on Oct. 23. l 986. discloses a 50
`modular sign (shown in FIG. I of that patent) which
`comprises a plurality of display panels that may be inter(cid:173)
`connected in juxtaposition to form a sign of a larger modular
`dimeosioo.
`European patent application no. 0 247 377 which was ss
`filed by Lumino Licht Electroni.k GmbH and published on
`Oct. l l. 1989. describes a circuit board used for iotercoo(cid:173)
`nectiog LEDs in a matrix pattern for use i o a modular
`display sign.
`European patent application no. 0 242 742. wa.s also filed 60
`by Lumioo Licht Elektronik GmbH and published oo Aug.
`30. 19&9. This patent application is entitled (in Eoglish
`translation) Circuit Arrangemeot for Selectively Controlling
`Function Modules by a Bus-System. The patent describes an
`electronic display sign architecture wherein microprocessors 65
`associated with .. function modules" are sig nalled and con(cid:173)
`trolled by limed voltage drops on an electronic bus effected
`
`25
`
`35
`
`SUMMARY OF THE INVENTION
`It is an object of the present invention to provide an
`electronic display sign having a system bus architecture 10
`accommodate the high speed transfer of display and control
`data over relatively long dista.oces.
`It is a further object of the present invention to provide an
`electronic display sign wherein at least one display panel is
`controlled by a sign controller which transmits data signals
`over a system bus i.n order to effect and control the display
`of au image on the at least ooe display panel.
`It is a further object of !he invention to provide a large
`modular electronic display sign which can be manufactured
`and supplied at reasonable cost.
`It is yet a further object of the invention to provide an
`electronic display sign which is capable of full video ani(cid:173)
`mation.
`It is yet a further object of the invention to provide an
`electronic display sign of a modular design. each module
`having local display. local refresh. and local control capa(cid:173)
`bilities.
`II is a further object of the invention to provide an
`electronic display sign of a modular design wherein each
`45 module may be adjusted for steradiaocc matching in the
`event that a module requires replacement and a replacement
`module from the same LED production batch as the original
`sign cannot be obtained.
`In accordance with the present invention there is provided
`an electrooic display sign which comprises at least one
`display node having a display swface which supports a
`plurality of light sources for displaying images as discrete
`poiots of light;
`at least one cootrol node for controlling !he display of
`images by the at least one display node using addressed data
`signals and control signals;
`and at least ooe sign system bus for transferring the
`addressed data signals and control signals from the at least
`one control node to the at least one display node.
`The electronic display sign io accordance with !he inven(cid:173)
`tion is preferably constructed io accordance with a modular
`design whereby one or more display panels are intercon-
`nected in a juxtaposed relationship to yield a sign having a
`desired dimension. Each display sign is provided with at
`least one sign controller which operates a control program to
`format and aportion data representative of that portion of an
`
`(cid:47)(cid:50)(cid:58)(cid:40)(cid:54) 1014, Page 9
`
`VIZIO Ex. 1014 Page 0009
`
`

`

`5.796.376
`
`3
`image to be displayed by each display panel. Each display
`panel is connected 10 the sign controller by a sign system bus
`which is used for the transmission of addressed display and
`control signals. Each display panel is provided with its own
`power supply which drives the LEDs on the display panel.
`This pennits the use of fast. efficient electric switching
`components that permit a multiplexed power scheme in
`which o nly a portion of the LEDs on each pane.I are driven
`at any point in time but the multiplexed power frequency is
`so rapid that all LEDs on a panel appear to be continuously
`lit. if desired. The multiplex scheme greatly reduces the
`number of individual LED drivers required and therefore
`reduces the cost of each panel.
`The present invention therefore provides ao electronic
`display sign of a modular design which perm.its a user to
`select a sign of an appropriate size with the understanding
`that the size of the sign may be enlarged as need or funds
`pennit. The invention also provides the capability of a large
`scale electronic display sign which is capable of full video
`animation at display rates well in excess of thirty frames/
`second.
`
`15
`
`4
`include as many as 128 display panels 26 which yields a
`display sign that is approximately 13 feet 4 inches
`(approximately 4.3 m) square. A sign of this size bas a total
`of 65.536 (64K) light elements. Much larger and much
`smaller signs can. of course. be built in accordance with the
`sign system architecture taught hereinafter. Those skilled in
`the art will recognize that the limit of the size of the
`preferred embodiment is due to hardware and software
`limitations which are minor i n nature and readily overcome.
`10 Theoretically. using multiple sign controllers 22 and a
`plurality of sign system buses 24. the size of the display sign
`20 is unlimited. Nonetheless. for practical purposes. a dis•
`play surface of 13 fee.t 4 i nches square is considered to be
`adequate for most applications.
`FIG. 2 shows a block diagram of the conceptual archi-
`tecture of a large electronic sign in accordance with the
`invention. As is apparent. the sign includes a total of 12&
`display panels 26 connected in groups of thirty-two panels
`each 10 four sign system buses 24. as will be explained in
`20 more detail in relation to FIGS. S and 6. In order to facilitate
`flexible and convenient operation. the sign is connected to a
`display generator 30 which in tum includes an external
`control 32. Io accordance with the preferred embodiment of
`BRIEF DESCRIYflON OF TIIE DRAWINGS
`the invention. the display generator 30 and the external
`A preferred embodiment of the present invention will now 25 control 32 comprise a personal computer equipped with
`be explained by way of example only and with reference to
`software which is capable of generating a bitmap represen-
`tation of the sign display. The software preferably permits
`the following drawings. wherein:
`the use of a bitmap editor where the user may create graphics
`FIG. 1 is a block diagram of the architecture of an
`electronic display sign in accordance with the invention;
`using a mouse in a freehand style. The bitmap editor also
`FIG. 2 is a block diagram of a preferred embodiment of 30 preferably permits a user t~ ~lac~ b(t.map re~esentations of
`an electronic display sign in accordance with the invention;
`ASCD characters at a position 1Ddicated with a mouse or
`FIG. 3. which appears on the first page of the drawings.
`pointer on a di~~ed pad. The software is pr<:f erabtr also
`is a block diagram of a preferred embodiment of a sign
`capable of buildin.g. scro~. ~1splays. crc~tlllg display
`controller in accordance with the invention;
`seque?'es. and recet~g digtt.tz~d scanner 1:'11'3ges. an~or
`• 35 graphic files and fonnaling such unages for display LD pixel
`•
`•
`FIG. 4 1s a ~lock d!agr~ of a preferred bus controller lD
`form on the electronic display sign 20.
`FIG. 3 shows a detailed schematic diagram of the pre-
`accordan~ with the .mvent1on:
`.
`.
`.FIG. S .1s a bl?C" diagram of a display panel m accordance
`ferred embodiment of the sign controller 22. The two main
`functions performed by the sign controller are the acquisi-
`with the 10ven11on;
`FIG. 6 is a block diagram of a display panel controller in 40 lion of raster images from the display generator 30 and the
`output of the raster image data to the display panels 26 (see
`accordance with the invention:
`FIG. 7 is a simplified sche.matic of a LED power circuit
`FIG. 2). The two processes arc performed concurrently by
`for a display panel in accordance with the invention;
`the sign controller. Raster image data is received from the
`display generator 30 and is stored in a d~narnic RAM buffer
`FIG. 8 is a front elevallooal view of a typical display panel
`45 34. A concurrent process reads the raster unage data from the
`constructed in accordance with the invention·
`.
`.
`.
`' •
`RAM memory 34 and outpulS the data to the display panels
`F1G. 9 1s a cross-sectional view taken along lines 1>- 1> of
`I
`·
`•
`,.., In d
`t
`abl
`·
`·
`th
`......
`od
`th di
`• FIG
`or er o en
`e aruma11on on an e ectroruc sign. c
`l
`h
`8
`1
`sp ay. pane s own ~ ·
`; a
`.
`sign controller must output raster image data to the di.splay
`e
`FIG .. 10 ,s a rear elevattonal of four of the display ~anels
`panels 26 at 24 frames or more per second. A display sign
`s~own 10 F1G. 8 connected together to form a small display 50 20 in accordance with the invention will output raster image
`data at a rate well in excess of thirty frames/sec. To meet that
`sign.
`animation data rate the sign controller 22 (as taught herein)
`requires four sign sy stem buses 24 to support a very large
`sign of 126 display panels. Those slcilled in the alt will
`ss realize that the acrual number of sign system buses 24
`required will depend on the speed of the bus processors.
`Each sign system bus 24 has a data transfer rate of 350
`kbytes/sec. Each display panel 26 is conoected to a sign
`system bus 24 and receives display data in 64 byte blocks.
`60 as will be explained below in more detail.
`The preferred embodiment of the sign controller shown in
`FIG. 3 includes two interfaces to receive display information
`from an ei1teroal display generator 30. The display informa(cid:173)
`tion consists of display data. sign controller commands. and
`65 memory addressing information. The display information
`may be received via a parallel interface 36 which can be
`connected to a PC parallel centronics port to accommodate
`
`DETAR.ED DESCRIPTION OF A PREFERRED
`EMBODIMENT
`FIG. 1 shows a block diagram of the design concept of an
`electronic display sign. generally referred to by reference
`numeral 20. in accordance with the invention. lo its simplest
`form. an electronic display sign in accordan.ce with the
`invention includes a sign controller 22. a sign sys tem bus 24.
`and a display panel 26. In accordance with the preferred
`embodiment of the invention. the display panel 26 has a
`display surface which supports 512 light sources arranged in
`16 rows of 32 columns. Each light source 28 is preferably a
`light emitting diode (LED). The preferred LED is a high
`intensity red LED which outputs at least 15 candellas of light
`energy. Such LEDs are available from a number of suppliers.
`An electronic sign in accordance with the invention may
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`5.796.~76
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`5
`a maximum data exchange rate of about 20 kilobytes a
`second. assuming average load on the CPU of the PC and the
`sign controller. This rate will not support a real-time display
`data rate of tllirty frames/sec. A DUARr 40 is provided for
`asynchronous communication which pennit~ data transfer
`from any RS232 source.
`A dynamic memory access (DMA) controller 38 handles
`data movement between the communication interfaces 36.
`40 and the display memory 34. The DMA controller 38
`preferably operates in cycle-steal mode and uses fly-by
`transfers (single write cycle time). The data movement
`operations of the DMA controller are controlled by a sign
`controller central processing unit (CPU) 42. The CPU 42
`may be any suitable microprocessor. An acceptable model is
`the Motorola MC68010Pl0 microprocessor but many other
`models are also suitable. The primary function of the CPU
`42 is to output display data from the display memory to the
`display panels Ui. As noted above. the CPU 42 must be
`capable of driving the largest sign configuration at a rate of
`about thirty frames/sec. The CPU 42 is responsible for 20
`calculating the display panel and bus driver addresses for
`each 64 byte image data block. The CPU 42 is also respon(cid:173)
`sible for the frame timing of the images. Commands for the
`CPU run-time operation are placed in memory by the
`external controller 32. The sign controller commands
`include a user defined variable associated with each display
`image that controls the frame display rate for the image. The
`CPU 42 uses the variable to control the frame timing of the
`images. The control commands therefore determi.oe defin(cid:173)
`able frame display rate for each image.
`Toe controller includes up to 512 kilobytes of EPROM
`memory 44 which is used 10 store the software program that
`controls and ooordinates the activities of the sign controller.
`EPROM memory 44 may be funher expanded to store
`start-up or display sequences which may be iteratively
`performed if communication with the display generator 30 is
`disabled.
`A display memory 34 allocated in the dynamic RA."lvf
`preferably comprises at least 8 Megabytes of addressable
`space although the sign may be operated with less RAM
`memory and therefore less display memory 34.
`The sign controller 22 is also preferably provided with a
`timer 46 to serve as a timing source for the CPU 42. An
`appropriate timer is usually available as an integral pan of
`the parallel interface 36.
`Finally. the sign controller 22 is preferably provided with
`four sign system bus drivers 48. The bus drivers 48 provide
`current drive capability to each sign system bus 24. The
`display panels 26. as will be e xplained in detail with
`reference to AGS. 5 and 6 are daisy-chained together using
`standard ribbon cable. The bus signals are buffered at each
`display panel lo keep the sign system bus driver fao out low
`and to compensate for any cable losses. The standard sign
`system bus is preferably unidirectional and includes 8
`address/data bits. a data strobe. and an address strobe. All
`panel bus buffers are permanently enabled.
`AG. 4 shows a block diagram of a sign system bus driver
`48 which is constructed with standard TTL components. The
`sign system bus drivers 48 have multiplexed address and
`data capability with address and data strobes. All fouc sign
`system bus drivers run concurrently with a maximum data
`transfer rate of 350 kilobytes/sec. each. The combined data
`transfer rate of the sign controller 22 therefore exceeds 1.2
`megabytes per second. This data transfer rate permits the
`electronic display sign 20 to display well in excess of thirty
`frames/second. thereby achieving full video animation. Each
`
`6
`sign system bus driver 48 includes a four kilobyte by 9-bit
`wide first-in-firs1--0u1 device (FIFO) 50. an address coder 52.
`and a state machjoe 54 (field programmable gale array). A
`single state machine 54 preferably runs all four sign system
`buses 24.
`The CPU 42 retrieves data from display memory 34 (see
`FIG. 3) and computes an address for each M byte block of
`data (the data for one display panel refresh) based on the
`location of that display panel 26 in the electronic display
`10 sign 20. The CPU 42 loads a byte of data into the FIFO SO
`and sets the 9th FIFO bit using the address coder 52. H the
`data moved to FIFO 50 is an address indicating the desti(cid:173)
`nation of a block of display data 10 follow. FIFO bit 9 is set
`to 1 to indicate an address. otherwise. FIFO bit 9 is set to 0
`to indicate a data byte. The state machine 54 is res ponsible
`15 for timing on the display panel bus 24. It also reads bit 9 of
`each FIFO byte and drives the data strobe of the standard
`ribbon cable high if bit 9 indicates a data byte or drives the
`address strobe of the standard ribbon cable high if FIFO bit
`9 indicates an address byte.
`AG. 5 is a block diagram of the components of a display
`panel 26. Each display panel 26 is provided with a power
`supply 56 and a panel control card 58. The power supply S6
`is preferably a high quality switching power supply capable
`of supplying at least 16 amps at 5 volts DC. Power supplies
`25 with less current capacity may be substituted but the cost
`advantages are not significant and the added reliability of a
`quality power supply is preferred. Since each display panel
`is preferably supplied with its own DC power supply. a 120
`volt AC power distribution system is required for the sign.
`30 Using an efficient switching DC power supply. each display
`panel 26 will require between 0.8 and l ampere of AC
`current. in a worst case assumi ng that high intensity red
`LEDs are used. to power all the LEDs oo the display panel.
`The display panel control card SS consumes negligible
`3s power. Assuming a sign that includes one hundred twenty(cid:173)
`eight display panels 26. the worst case current draw would
`be in the order of 125 amperes at 120 volts AC. An electric
`service for a sign must therefore be capable of supplying
`about one ampere per display panel.
`Appropriate electrical connectors must be mounted exter-
`nally of a sign for a given multiple of display panels. Ideally.
`each of those connectors (not illustrated) will accommodate
`the connection of a cable which can supply 20 amperes of
`AC current at 120 volts AC. A connector of this type will be
`45 required for each group of about 22 panels. A full size sign
`would therefore require 5 or 6 connectors of 20 amps each.
`Such connectors are well known in the art and widely
`available. Electrical power may be distributed to the panels
`using daisy-chain connectors for transferring power fro m
`so display panel to display panel. a technique which is also well
`known in the art. Fuse protection (not illustrated) should be
`provided on each display panel 26 to prevent damage due to
`power surges and the like.
`FIG. 6 shows a block diagram of the display panel control
`ss ca.rd 58. The display panel control card 58 is a circuit board
`which is physically affixed to a skeleton frame or the like on
`the rear of each display panel 26. Each display panel 26
`preferably includes a total of 512 lEDs arranged in a grid of
`16 rows by 32 columns. A multiplexing scheme in which
`60 only '·.th of the LEDs are driven at any one time is used.
`This scheme reduces the number of LED drivers required. In
`order to avoid any reduction in lumination brightness. the
`LEDs are driven al a peak current of 160 mA. The •,;, duty
`cycle ensures an average current of 20 mA for each LED.
`65 The multiplex.ing frequency operates at 1000 Hz. The actual
`power switching of LEDs is explained below in more detail
`with reference co AG. 7.
`
`40
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`5.796.376
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`7
`The display panel control card 58 is responsible for
`accepting display data and brightness data from the sign
`controller via a sign system bus 24. Each display panel
`control card 58 has a permanently enabled bus buffer 641 to
`keep the sign system bus fan out low and cornpen sate for any 5
`cable losses. Propagation delay introduced by these buffers
`is negligible. The panel data bus 24 is preferably unidirec(cid:173)
`tional and includes 8 address/data bits. a data strobe and an
`address strobe. as explained above. If an address strobe is
`received by the bus buffer. the accompanying signal is 10
`analyzed as follows: 1) the bits 1-5 are sent to an address
`decoder circuit (notillustrated) which compares the address
`encoded in those 5 bits with the settings of the DIP switches
`on a panel address selector 74. If the address decoder
`detenuines a match. the subsequent 64 bytes of data trans- 15
`milted on the sign system bus 24 are loaded into load buffer
`62 and consequently i.nto panel RAM memory 66. 2)The 6th
`and 7th bit of an address byte determine the brightness of the
`panel display. This permits display brightness to be adjusted
`with every panel refresh. 3) The 8th bit is a "broadcast bit". 20
`If lhe 8th bi1 of an address byte is set 10 " l". all panels load
`the subsequent 64 bytes of data. regardless of the actual
`address value in the first five bits of the address byte. This
`permits a very fast refresh of an entire sign. All of these
`operations are managed by a panel controller 641. The panel 25
`controller loads data from panel RAM 66 to a re.fresh buffer
`68 and subsequently to a latch array 70 where sixty-four
`latches are set in accordance with the data.
`The LEDs on each display panel 26 are divided into eight
`sectors. each comprising 64 pixels. The panel controller 64 30
`generates timillg signals for the eight display panel sectors
`and the pixels within each sector. A sector drive circuitry 72
`generates a I kHz refresh frequeocy for the sectors and also
`controls a pulse width of a pixel drive power pulse. The
`pulse width of the pixel drive power pulse controls the duty 35
`cycle of the drive signal to each LED. providing the bright(cid:173)
`ness control for the sign. The power pulse width is also
`controlled by calibration switches 76 as shall be discussed
`below. The RAM controller operates in two basic modes. a
`refresh mode and a data acquisition mode. The controller is 40
`in refresh mode unless it is acquiring data from the panel
`data bus 24. In refresh mode it reads data very quickly 8
`bytes at a time from the display panel RAM 66. An 8 byte
`read is performed each time a sector drive is changed at the
`I kHz refresh rate.
`When an address match is detected on the display panel
`bus 24. the display panel controller 64 immediately writes
`the n~t 64 bytes of data on the panel bus into the panel
`RAM 66 using the data strobe as its clock. This 64 byte write
`period requires about twenty microseconds of real time.
`While performing a data write cycle. the sign refresh is
`disabled.
`As noted above. the power drive pulse width for the LEDs
`on the display panel U is controlled by the sector driver
`circuitry 72. Those skilled in the an are familiar with
`problems of steradiance matching in LED applications. It is
`well known that LEDs from different production batches are
`not always matched in brightness. When constr