PCMCIA System Architecture
`
`As shown in figure 11—], the C18 is read by PC Card client drivers during card
`initialization to determine the configuration options supported by the card.
`The PC Card client accesses the CIS via card and socket services. Once the
`
`card type and resource requirements have been read from the CIS, the PC
`Card client driver programs the HBA and configures the PC Card, again via
`card and socket services. No further access is typically made to the CIS after
`the card has been initialized. The memory or 1/0 device can now be accessed
`via the host expansion bus, as would any other expansion device. Note that
`the C15 is only accessed by programs that are PCMCIA aware. Most applica-
`tion programs have no knowledge that
`they are accessing devices
`implemented in PC Card packages.
`
`Configuration and
`Event Notification
`Software
`
`Hardware
`
`Run-Time
`Software
`
`PC Card Enablers
`
`(PCMCIA Int! 5;Event Ptocessing} II
`
`II
`
`
`
`
`Operating
`System
`
` Host System Applications
`
` Card Services
` hisrig-:3"v'S'IisagmaH
`
`uoueozmorvwane
`
`
`
` PCMCIA
`Socket Services
`
`Host Bus Adapter
`
`\l.
`
`Device Drivers
`
`(Run-Time Code}
`
`I
`
`Figure 11-1. PCMCIA Software Plow
`
`
`
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`Chapter 11: The Card Information Structure (CIS)
`
`
`
`The Card Information Structure (CIS)
`
`The C15 is mapped into the attribute memory address space starting at ad-
`dress zero as illustrated in figure 1142. The CIS consists of a linked list of data
`blocks, or tuples, that describe the function and characteristics of a PC Card.
`Configuration software accesses this data to determine the characteristics and
`configuration requirements of a given PC Card. Tuples are identified by a
`unique code which in the first byte of each tuple.
`
`Note that CIS data is mapped only to even locations within the attribute ad-
`dress space;
`thus,
`information is returned only on the lower data path
`(D7:DO). This simplifies card designs for accommodating eight-bit host sys-
`tems that connect only to the lower data path.
`
`Attribute Memory
`Address Space
`
`SFFFFFE _
`—
`. —
`: —
`i _
`Tuple4 {1h
`16
`
`TUple3
`
`14
`
`22
`
`—
`
`_
`1D .5135.—
`
`E ms—
`
`
`
`_
`
`c A
`
`8
`
`Tuplee
`
`—
`5 -E_
`
`Tupuei
`
`4 —
`2
`
`—
`
`0
`
`Figure 11-2. Example CIS Layout Consisting ofa Linked List of Four Tupies
`
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`PCMCIA System Architecture
`
`
`Tuples
`
`A tuple is defined in Webster's Ninth New Collegiate Dictionary as a "set of
`elements." A tuple in PCMCIA terminology refers to a defined set of data
`items that characterize some facet of a PC Card. The PCMCIA standard speci-
`fies tuples intended to be used by PC Card designers for providing
`information about their device. Tuples provide information such as the PC
`Card's device speed and size. Tuple information is most often used by con—
`figuration software to determine the configuration requirements of the card.
`However, other tuples provide information that can be used by utility pro-
`grams and applications to ascertain additional capabilities of the card.
`
`Tuple Format
`
`All tuples have a general format defined by PCMCIA (refer to table 11-1). The
`first one-byte element (entry 0) of every tuple is a tuple type code that defines
`the tuple's function. The second entry (entry 1) of every tuple is a one—byte
`link value (in hex) that specifies the number of additional bytes remaining in
`the tuple. The number and definition of these remaining bytes depends on the
`type of tuple.
`
`
`
`
`
`Table 11-1. Basic Tuple Format
`
`Standard Tuple Format
`
`TPLTCODE
`
`Tuple type code 0001). See table 11—7 for tu-
`ple codes.
`
`L_LINK
`
`Link to next tuple (number of bytes (in hex)
`remaining in tuple)
`
`T_PLDATA
`
`Tuple specific data block (definition format
`and length defined by individual tuples).
`
`
`
`
`
`
`The CIS consists of a linked list of tuples. Each tuple specifies a link value that
`identifies the start of the next tuple. Processing software can read the CIS en-
`tries and interpret
`the meaning of the tuples that contain configuration
`information for the PC Card.
`
`The exact set of tuples incorporated into the CIS depends primarily on the
`type of card and its capabilities. For example, the Device Information Tuple
`
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`Chapter 11: The Card Information Structure (CIS)
`
`may contain all the information needed to determine the resources required
`by a simple SRAM card, while other card types might require numerous tu-
`ples to define the configuration of the card.
`
`A Sample Tuple
`
`Consider the information provided by the Device Information tuple shown in
`table 11-2. This tuple defines a 100ns SRAM card containing 1MB of memory.
`The first byte within the tuple contains a value of 01h defining this tuple as a
`device information tuple. The second byte (03h) specifies the number of bytes
`remaining in the tuple. The device information tuple contains two bytes
`within the tuple's data area. One that defines the memory card type, speed,
`size, and whether the write-protect switch affects the range of memory being
`defined, and one that defines the size of the memory device.
`
`The memory card device type is specified in the tuple as a hexadecimal code
`value. In this example, the device code is a 6h. As shown in table 11-3, a de-
`vice code of 6h identifies the card as SRAM. Similarly, the SRAM'S cycle time
`is specified with a speed code of 4h. This indicates a device speed of 100ns as
`shown in table 11-4. The size of the device can be determined by reading the
`unit size code and multiplying the unit size by the number of units specified.
`The unit size code of 5h, specifies memory banks of 512KB (refer to table 11-5)
`and the number of units field contains a 1h, indicating two memory units are
`implemented for a total size of 1MB. Finally, the tuple is terminated by FFh.
`This tuple includes a termination byte because the data within the tuple can
`vary in length (is. more than one memory device can be described by the
`Device Information tuple). The termination bytes make it easier for parsing
`software to recognize the end of variable length tuples. Tuples that do not
`vary in length do not define a termination byte.
`
`Table 11-2. Example Device Information Tuple for an SRAM Card
`
`
`
`
`
` Device Information Tuple
`
`
`
`
`“‘Device Type=bits 7:4 (6h) ; WP=bit 3 (0);Speed=bits 2:0(4h)
`*Device Size: # of units [bits 7:3 (1)] times unit size [bits 2:0 (5h)]
`
`
`
`Tuple Code (01h)
`
`Link to next tuple (3h)
`
`
`
`FFh (marks end of device into field)
`
`* Refer to the following tables for an interpretation.
`
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`PCMCIA System Architecture
`
`Table 116. Device Type Codes
`
`
`
`
`
`
`
`-——
`Name
`DTYPE NULL
`No memory device. Generally used to desig-
`nate a hole in the address space. If used, speed
`field should be set to 011.
`
`
`
` DTY PE_EEPROM
`
`DTYPE ROM
`
`mm mm
`m mom
`
`DTYPE FLASH
`
`DTYPE SRAM
`
`——
`
`I-
`
`__——
`
`DTYPE DRAM
`8 ch —
`DTYPE_FUNCSPEC
`
`Masked ROM
`
`EEPROM
`Flash EPROM
`
`Static RAM UEIDA has Nonvolatile RAM)
`
`Dynamic RAM GEIDA has Volatile RAM)
`
`Function-specific memory address range. In-
`cludes memory-mapped
`l/O registers,
`dual-ported memory, communication buffers,
`etc, which are not intended to be used as genw
`eral-purpose memory.
`
`
`
`
`
`
`
`
`
`
`
`
`——
`
`
`
`DSPEED_NULL
`
`DSPEED_100NS
`
`DSPEED_250NS
`
`DSPEED ZODNS
`
`DSPEED 1 50NS
`
`150
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`Chapter 11: The Card Information Structure (CIS)
`
`Table 116. Unit Size Codes
`
`512 bytes
`2 K
`
`
`
`8 K
`32 K
`
`
`128 K
`512 K
`
`2 M
`
`
`Reserved
`
`The Configuration Table
`
`I/O devices require that the CIS contain a configuration table that is not re-
`quired by memory cards. This table consists of multiple entries each of which
`describes a set of configuration options that the PC Card needs for normal op-
`eration. A comparison can be made between each configuration table entry
`and each possible switch and jumper setting required when configuring an
`ISA card. Each configuration table entry reflects the possible resource combi-
`nations that the PC Card can be configured for.
`
`The Configuration Entry Tuple
`
`Figure 11-3 illustrates a C15 that c0ntains a configuration table. Directly pre—
`ceding the configuration table is the configuration tuple that specifies which
`configuration registers are implemented by the PC Card and where they are
`mapped within attribute memory address space. The configuration tuple also
`specifies the index number of the last entry within the configuration table. As
`illustrated in figure “ll-3, the configuration table consists of a series of configu-
`ration table entry tuples (CFI‘ABLEgENTRY). Each entry contains up to seven
`data structures that describe operational characteristics of the PC Card. These
`structures include:
`
`1. A power description byte — the power parameters specified within this
`structure may apply to Vcc only, Vcc and Vppl and Vpp2 (Vppl =Vpp2),
`or separately to Vcc, Vppl, and Vpp2. The specific power parameters de-
`
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`PCMCIA System Architecture
`
`scribed by the structure are also selectable as defined by the parameter
`selection byte within the power description structure.
`2. Configuration timing informatiori ~— this structure defines the maximum
`length of time that the PC Card will keep READY deasserted and the
`maximum duration of the WAIT# signal.
`IIO address space description — defines up to sixteen ranges of I/O ad-
`dress space required by the PC Card for this configuration. The structure
`defines the exact base 1/ 0 address and the number of address locations
`
`3.
`
`4.
`
`within the range
`Interrupt request description — specifies the system interrupt request
`line required for this configuration. A single IRQ can be specified or a
`group of LRQs can be defined, any of which will satisfy the configuration
`requirements. Also included in the description is information that defines
`the deliver mode (level or pulse), whether interrupt sharing is supported,
`and alternative interrupt signal definitions (i.e. NMI, I/ 0 check, bus error,
`vendor specific interrupt).
`5. Memory address space description — specifies up to eight ranges of
`memory address space required for this configuration. Both the Host
`processor address and the PC Card address can be specified. When both
`the host and PC Card address are the same, no address translation is re-
`quired since the host address is directly mapped into the common
`memory address space. If no host address range is specified, then any
`range of host address space can be used and mapped by the HBA to the
`specified range within common memory address space. A base address
`and range value are specified for each block of addresses needed for this
`configuration.
`6. Miscellaneous information structure — contains information regarding
`support for special features required by this configuration. Two bytes are
`defined by the PC Card standard. The first byte identifies the PC Cards
`support for power down (for power management software), whether the
`SPKR# pin is used, and the number of identical PC Cards that are sup-
`ported for the max twins cards option (e.g. support for multiple ATA
`drives). The second byte defines support for DMA, including the DMA
`transfer size and specifies which pin the PC Card uses for DREQ#.
`7. Subtuple information — permits definition of additional information re—
`lating to this configuration. Subtuples are included as extensions to the
`configuration table entry tuple and may include information such as the
`operation system for which the c0nfiguration was intended and the physi—
`cal device being implemented in this configuration.
`
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`Chapter 11: The Card Information Structure (CIS)
`
`
`
`Tuple 5
`
`Tuple 4
`
`TuIeS
`Tule2
`
`Config Table
`Entr 3
`
`Contig Table
`Entr 3
`Config Table
`Entr 2
`
`Contig Table
`Entryr 1
`
`Configuration
`Registers
`
`.
`.
`Configuration Table
`
`Configuration Tuple
`
`Other
`CIS
`Tuples
`
`Tools 1
`
`Figure 11-3. The Configuration Table Consists ofo Number of Entries, Describing the
`Configuration Options Supported by the PC Card.
`
`Table 11-6 shows the format of the configuration table entry tuple. The actual
`structures that are implemented within this tuple are specified by the feature
`selection byte.
`
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`PCMCIA System Architecture
`
`Table 11—6. Format of the Configuration Table Entry Tuple
`
`
`
`
`Description of Entry
`
`
`
`
`
`T'PL_CODE Configuration Entry tuple code (CISTPLgCFTABLE_ENTRY, lBh)
`Link to next tuple (n-1, {2 minimum!)
`TPL_LINK
`
`
`
`
`
`the entry, specifies whether the interface byte will follow, and specifies
`
`
`whether this entry is a default entry or not.
`
`
`Interface description byte — this field is present only when the interface
`
`bit of the Configuration-table index byte is set
`
`
`
`
`
`
`
`
`
`
`Feature selection byte indicates the optional structures present
`
`Power description structure
`
`Configuration timing information structure
`
`I / 0 address space description structure
`
`Interrupt request description structure
`
`Memory address space description structure
`
`Miscellaneous information structure
`
`Additional information about the configuration in subtuple format
`
`
`
`
`
`
`.
`
`Interpreting the Configuration Table
`
`When parsing software (usually a card services client driver) processes an en-
`try within the configuration table, it must determine if the resources specified
`are available. (Refer to the chapter entitled, “Client Drivers” for a discussion
`of resource acquisition.) If all resources that have been requested are available
`then the configuration is satisfied and no additional configuration table entries
`need be evaluated. If however, one or more of the resources required to sat-
`isfy the configuration are not available, then parsing software must evaluate
`subsequent entries in an attempt to find alternative system resources that will
`satisfy the PC Card’s configuration requirements.
`
`The first entry within the configuration table is typically specified as a default
`entry. Default entries indicate that all configuration information specified
`within the entry should be retained even in the event that the full configura—
`tion was not satisfied. For example consider the configuration table illustrated
`in figure 11-4. The first entry is a default entry that specifies a power struc-
`ture, a configuration timing structure, an I/O address space structure, an
`interrupt request structure and a miscellaneous information structure. As-
`
`
`
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`Chapter 11: The Card Information Structure (CIS)
`
`sume that parsing software was able to satisfy all configuration information
`specified by this entry except the interrupt request line. Software then pro-
`ceeds in the following manner:
`
`1. Since this is a default entry, all resources successfully acquired are re—
`tained. This eliminates the need to re-specify all the parameters that apply
`globally to the card’s configuration regardless of which I/O address space
`and [KO line is assigned to the card. In this example, since the entire con-
`figuration was not satisfied, parsing software proceeds to the next entry,
`attempting to find alternative resources that the PC Card can use.
`
`2. Assume that entry 2 is not a default entry and contains only an I/O ad-
`dress structure and IRQ structure. Parsing software recognizing a non-
`default entry knows it must successfully acquire all configuration options
`specified, and if unable to do so must release the partial configuration by
`returning the resources previously acquired. Furthermore, since a pair of
`resources is being requested, the parsing software recognizes that the [/0
`address space acquired when attempting to satisfy the previous default
`entry must be released in favor of the new I/O address space and IRQ
`lines specified by this entry. If both configuration options are acquired
`successfully, then the configuration is completed. If not, the incomplete
`configuration is released and parsing software proceeds to the next entry.
`
`3. Assume that entry 3 is not a default entry and contains another set of I/O
`addresses and another IRQ line. Once again parsing software attempts to
`acquire both resources, and if not successful must release any resource
`acquired and proceed to the next entry. As before, if both are acquired the
`configuration is cornplete.
`
`4. Entry 4 is the last configuration entry and contains the final I /0 address
`space and IRQ options for configuring the PC Card. If these resources
`cannot both be acquired, then the parsing software must report to the user
`that the card cannot be configured.
`
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`

`PCMCIA System Architecture
`
`Configuration
`Table
`
`Interrupt Structure
`
`Entry 4
`
`Entry 3
`
`Entry 2
`
`Emwt
`
`MD Add r. Structure
`
`Non-default Entryr
`
`Interrupt Structure
`
`HO Addr. Structure
`
`Non-detault Entry
`
`Interrupt Structure
`
`a0 Addr. Structure
`
`Non-deiault Entry
`
`Misc. Structure
`
`Detault Entry
`
`Interrupt Structure
`
`Ir‘O Addr. Structure
`
`Timing Structure
`
`Power Structure
`
`Figure 11-4. Example Configuration Table with One Default and Four Non-Default
`Entries
`
`Once parsing software has obtained the configuration resources from the sys-
`tem it must configure the HBA and PC Card so that they respond to the
`resources. Parsing software uses the index number of the configuration table
`entry that specifies the successful configuration when configuring the PC
`Card. The index number is written into the PC Card’s configuration option
`register, telling the PC Card which set of configuration options were success-
`fully acquired.
`
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`Chapter 11: The Card Information Structure (CIS)
`
`Multiple Function PC Cards
`
`Mum-function PC Cards require a separate CIS and configuration register set
`for each function within the card. As illustrated in figure 11~5, a global C15 is
`required when implementing a multi-function PC Card. The global CIS con-
`tains a long link multi-function tuple (LONGLINK_MFC) that lists the entry
`points of each function’s C15. The first entry Within the target CIS must con-
`tain a LINKTARGET tuple to verify the correct start address specified by the
`LONGLINK‘MFC tuple. Note that the configuration registers used by each
`function are identified by the configuration tuple within each CIS.
`FFFFFFF
`
`Function 3
`
`Contig‘ Regs.
`Function 2
`Config. Regs.
`
`Function 1
`Contfg. Regs.
`
`
`
`LiNICI'AFIGEI'
`
`Function 3
`CIS
`
`Function 2
`CIS
`
`
`CIS TUNES
`
`
`
`0'5 “‘9'“
`
`LINKTAHGET
`
`
`
`CIS Tuples
`
`LINKTAFIGET
`
`
`CIS Tuples
`
`
`
`0000000
`LONGLINK_MFC
`Attribute Memory
`Address Space
`
`Function 1
`GIS
`
`GlohaiCls
`
`Figure 11-5. Configuration Table Structure Used by a Triple-Function PC Card
`
`157
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`

`PCMCIA System Architecture
`
`
`Devices Commonly Used for the CIS
`
`Both ROM and FLASH are commonly used to implement the CIS. The clear
`advantage of FLASH is that the CIS can be easily updated. The C15 is quite
`small (usually not larger than 1 KB) and in the case of SRAM cards it can be as
`few as six bytes.
`
`CIS Access Timing
`
`Attribute memory (the CIS and configuration registers) must be accessed by
`card enabling software to determine the type of card installed and how it
`should be configured. Attribute memory is accessed by the HBA based on a
`default 300ns cycle time. This ensures that the CIS can be accessed regardless
`of the speed of other devices within the card. See the chapter entitled "The
`Memory-Only Interface“ for details regarding attribute memory accesses.
`
`Summary of Layer 1 Tuples
`
`Table 11-7 lists the tuples that are currently defined by the PCMCIA specifica-
`tion for the CIS (layer 1 of the metaformat). Tuples are also defined for layers
`2 and 3, but are not discussed here. Refer to the PCMCIA specification for de»
`. tails.
`
`Table 11-7. Triples defined for Compatibility Layer One (CIS)
`
`
`
`CISTPL_NAME
`Description and Purpose
`
`
`
`
`
`
`
`
`NULL
`Null Control tuple — Used as a place holder. Ignored by
`
`
`tuple processing software.
`Device Information for Common Memory — Contains
`DEVICE
`
`
`
`information about the card's common memory devices,
`
`
`
`
`
`
`
`Long-Link for Multi-Function Card — Specifies the
`LONGLINK_MFC
`number of functions within this PC Card (Le. sets of
`
`configuration registers} and defines the location of each
`
`function~specific CIS within the card.
`
` Reserved for future versions or for CardBus tuples.
`
`including speed, type, write protect and size.
`
`Reserved
`
`Reserved for future versions of the device information
`tuple or for CardBus implementations.
`
`
`
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`
`
`
`
`
`
`Chapter 11: The Card Information Structure (CIS)
`
`Table 11—7 Tuples Defined for Compatibility Layer One (Continued)
`
`
`
`
`
`
`Code (h) _ISTPL_NAM— Description and Purpose
`
`
`
`
`10
`CHECKSUM
`Checksum Control — Provides a means for verifying the
`contents of the C18 in memory. Multiple checksum con-
`
`
`trol tuples can be implemented within a single C15.
`Long-Link Control to Attribute Memory — Specifies the
`
`
`
` continuation of a tuple string to a location in attribute
`
`memory, beyond the limits of the 1 byte link field. The
`
`entry point specified must contain a Link Target tupte.
`
`
`
`
`
`
`
`11
`
`
`
`
`LONG LIN K_A
`
`LONGLINK_C
`
`Long-Link Control to Common Memory — Specifies the
`continuation of a tuple string to a location in common
`memory, beyond the limits of the 1 byte link field. The
`entry point specified must contain a Link Target tuple.
`
`Link Target — Verifies the continuation of a valid tuple
`string. The Link Target tuple is the first tuple at the entry
`point specified by a Long-Link tuple.
`
`
`
`
`
`
`
`
`
`
`
`LINKTARGET
`
`
`
`NO—LINK
`
`
`
`
`
`
`
`
`The No Link tuple tellslprocessing software that when
`the end of the current tuple chain is reached (i.e. the
`Termination Tuple has been detected) that no more tu-
`ples exist in the chain to be processed. (See Termination
`tuple -- code FFh for more information.)
`
`
`
`
`
`Level 1 (also layer 1)Version identifies the PCMCIA
`
`
`
`compliance level of the CIS (also called the compatibility
`layer or metaformat layer one}. Following the Version
`information, production information is provided in a
`series of ASCII strings each ended by zero (Called AS-
`
`CIIZ).
`
`Alternate Language String — includes additional lan-
`guages for ASCII strings used in the product information
`
`tuple (code 15h). Also used for the Level 2 Version /
`
`
`Product Information tuple (code 40h}.
`
`Device Information to Attribute Memory — Contains
`
`information about the card's attribute memory devices,
`
`including speed, type, write protect and size. (optional)
`
`
`
`
`
`
`
`
`
`VERSJ
`
`ALTSTR
`
`DEVICEflA
`
`JEDEC_C
`
`
`
`Specifies the JEDEC (Joint Electronic Device Engineering
`Council) manufacturer and programming algorithm
`required by programmable devices listed in the device
`information tuple (01h) for common memory. Entries in
`the JEDEC identifier tuple have a one-to—one correspon-
`dence to the entries in the device information tuple.
`
`
`
`
`
`
`159
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`PCMCIA System Architecture
`
`Table 11—? Topics Defined for Compatibiiity Layer One (Continued)
`
`CISTPL_NAME
`
`Description and Purpose
`
`IEDECHA
`
`CONFIG
`
`Specifies the IEDEC (Joint Electronic Device Engineering
`Council) manufacturer and programming algorithm
`required by programmable devices listed in the device
`information tuple (17h). Entries in the IEDEC identifier
`tuple have a one-to—one correspondence to the entries in
`the device information tuple.
`
`Configuration tuple —- Specifies the address of the con-
`figuration registers in attribute memory space and
`specifies which configuration registers are implemented
`in the card. Also identifies the last configuration entry
`within the configuration table, and provides a method of
`appending subtuples to the basic configuration tuple.
`
`Subtuples define additional information related to the
`card's configuration. Subtupie codes SDh-BFh are re-
`served for vendor specific items, while COh- FEh are
`reserved for future PCMCIA standard definition. Cur-
`
`rently, only the Custom Interface subtuple has been
`defined.
`
`
`
`CFTABLE_ENTRY Configuration Table Entry — Provides configuration
`options supported by the card. Each configuration table
`entry provides additional configuration options. The
`entire set of configuration entries within the C18 is called
`the configuration table.
`Other Conditions Device Information (common mem-
`
`DEVICE_OC
`
`ory) — Specifies the characteristics of devices mapped in
`the common memory address space, when operating
`under conditions other than the defaults. For example, if
`the card is a dual voltage card (operates at both 5 volts
`and 3.3 volts) the characteristics of the common memory
`devices may be altered depending on which voltage is
`applied. There must be a one~to-one correspondence
`between the information fields listed in the Device In-
`
`formation tuple and the Other Conditions Device
`Information tuple.
`
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`
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`
`Chapter 11: The Card Information Structure (CI-S)
`
`Tobie 11-7 Triples Defined for Compatibility Layer One (Continued)
`
`CISTPL_NAME
`
`Description and Purpose
`
`
`
`
`DEVICE_OA
`
`
`
`
`
`
`
`
`
`
`
`
` DEVICEGEO
`
`
`
`
`
`Other Conditions Device Information (attribute mem-
`
`ory).— Specifies the characteristics of devices mapped in
`the attribute memory address space, when operating
`under conditions other than the defaults. For example, if
`the card is a dual voltage card (operates at both 5 volts
`and 3.3 volts) the characteristics of the attribute memory
`devices may be altered depending on which voltage is
`applied. There must be a one-to-one correspondence
`between the information fields listed in the Device In-
`
`formation tuple and the Other Conditions Device
`Information tuple.
`
`Device Geometry (common memory) — Device geome—
`try provides the erasa, read, and write characteristics of
`programmable devices. This tuple consists of multiple
`entries for each device identified in the device informa-
`
`tion tuple.
`
`Device Geometry {attribute memory) — Device geome-
`try provides the erase, read, and write characteristics of
`programmable devices. This tuple consists of multiple
`entries for each device identified in the device informa-
`
`tion tuple.
`PCMCIA Manufacturers Identification ~— Contains the
`PCMCLA manufacturer identification code and manufac-
`turer card identifier and revision information.
`
`
`Function Identification — Categorizes the card's func-
`tional type and specifies whether the card should be
`
`initialized during basic system initialization or when the
`
`operating system loads.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`DEVICEGEO_A
`
`20
`
`
`
`
`FUNCID
`
`
`
`
`
`
`
`CISTPL_NAME
`
`
`
`
`A multi-function device may also be specified, in which
`case additional Function Identification tuples for each of
`the cards functions will follow.
`
`Description and Purpose
`
`161
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`PCMCIA System Architecture
`
`
`Table 11-7 Triples Defined for Compatibility Layer One (Continued)
`
`CISTPLJJAME
`
`Description and Purpose
`Function Extension —— Provides detailed information
`
`
`
`
`about a specific function previously identified by the
`function identification tuple. This tuple contains addi-
`tional information useful to application programs or
`utility programs that are PCMCIA aware. Function ex—
`
`tensions, if applicable, follow each Function
`
`Identification tuple in the tuple chain.
`
`Extensions are useful for defining the capabilities of
`
`various types of devices such as modems and network
`
`interface cards.
`
`
`Termination tuple - Indicates that this tuple is the last
`
`tuple in the string. However, by default parsing software
`
`will continue processing tuples at location zero in com-
`mon memory. This implied jump to common memory
`occurs unless this tuple string contains either a
`
`LONGLINK OR NO_LINI< tuple. if a no-link tuple has
`
`been encountered, the tuple string ends without further
`
`processing. If a valid long-link tuple has been encoun-
`
`tered, tuple processing continues at the location
`
`specified, contingent on the presence of a LINKTARGET
`
`tuple at the target location. If there is neither a long- link
`
`nor a no-link tuple within the tuple string, tuple process-
`
`ing should continue at location zero in common
`
`memory.
`
`
`
`
`
`
`Sample CIS implementations for SRAM, FAX/MODEM, Flash Card and ATA
`Hard Drive are discussed in later chapters.
`
`Note that the CIS must start at address location zero in attribute address
`
`space or at the location Specified by the LONGLINK_MFC tuple in multiple
`function PC Cards.
`
`162
`
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`Chapter 12: Function Configuration Registers
`
`Chapter 12
`
`The Previous Chapter
`
`The previous chapter discussed the CIS and its role in the PC Card configura-
`tion process. Tuples were introduced and their format and structure were
`described. The basic structure of the ClS’s configuration table required by l/ 0
`cards was also described.
`
`This Chapter
`
`This chapter discusses the configuration registers and provides a complete de-
`scription of each register specified by the PC Card standard. Configuration
`register implementations for both single and multiple function cards are cov-
`ered.
`
`The Next Chapter
`
`The next chapter describes a sample SRAM card implementation, including a
`functional block diagram of the SRAM card along with a sample CIS.
`
`Configuration Registers
`
`Each PC Card’s [/0 function must implement configuration registers. The PC
`Card standard defines the following configuration registers:
`
`.00....
`
`Configuration Option Register -— mandatory for all I/O functions
`Configuration and Status Register — optional
`Pin Replacement Register —— optional
`Socket and Copy Register # optional
`Extended Status Register —— optional
`[/0 Base Address Register(s) — mandatory for multi-function PC Cards
`1 [0 Limit Register —— optional
`
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`PCMCIA System Architecture
`
`The format of each register is listed in table 12-]. These configuration registers
`are mapped into the attribute memory space at the location specified within
`the CONFIG tuple. Note that each function of a multiple function PC Card
`will have a dedicated set of configuration registers.
`
`Table 12-1. Format of the Function Configuration Registers
`
`Configuration Option Register
`
`Function Configuration Index
`LeleEQ
`SRESET
`Configuration and Status Register_
`
`1/0 Limit
`
`Pin Replacement Register
`
`Socket and Copy Register
`
`Extended Status Register
`
`Copy Number
`
`Socket Number
`
`l/O Base 0
`
`1/0 Base 1
`
`1/0 Base 2
`
`I/O Base 3
`
`Each of these registers have read /write capability and are mapped at even 10-
`cations, consistent with the design of attribute memory. The definition of each
`configuration register is detailed below.
`
`Configuration Option Register
`
`The configuration option register (COR) configures PC Cards that have pro»
`grammable address decoders. Once a card's client driver successfully parses
`the CIS and obtains the system resources required by the card, it assigns the
`resources to the card via the COR.
`
`As discussed earlier in this chapter, the configuration table within the CIS
`specifies the configuration options that a given card supports. Each entry
`
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`Chapter 12: Function Configuration Registers
`
`within the CIS contains a different combination of resources that satisfies a
`
`card's resource requirements. When the configuration options described by a
`particular configuration entry are found to be available,
`the index number of
`that configuration entry is written to the COR (refer to table 12-2). The index
`number programs the card to utilize the resources specified within the associ-
`ated configuration table entry.
`
`As shown in table 12-2, the COR also specifies whether the card should use
`level or pulse mode interrupts and provides a