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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`____________
`
`NICHIA CORPORATION,
`
`Petitioner,
`
`v.
`
`DOCUMENT SECURITY SYSTEMS, INC.,
`
`Patent Owner.
`
`_______________
`
`Case IPR2018-00965
`Patent 7,919,787
`
`____________
`
`
`PATENT OWNER’S PRELIMINARY RESPONSE
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`
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`TABLE OF CONTENTS
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`
`
`I.
`
`II.
`
`INTRODUCTION ........................................................................................... 1
`
`PETITIONER FAILS TO ACCURATELY IDENTIFY THE SCOPE OF
`THE CLAIMS BEING CHALLENGED ........................................................ 6
`
`A. Disputed Claims .................................................................................... 6
`
`B.
`
`Claim Construction..............................................................................14
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`III. THE CHALLENGED CLAIMS ARE NOT UNPATENTABLE ................18
`
`A. Grounds 1-3 Fail and Should be Denied Without Institution .............20
`
`1.
`
`Lumbard Does Not Disclose or Suggest the Claimed Light
`Emitting Semiconductor Die ..........................................................20
`
`2. Weeks Fails to Remedy Lumbard’s Shortcomings ........................22
`
`3. Wirth Also Fails to Remedy Lumbard’s Shortcomings .................25
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`4.
`
`Negley Also Fails to Remedy Lumbard’s Shortcomings ..............28
`
`B.
`
`C.
`
`Grounds 4-6 Fail and Should be Denied Without Institution Because
`Ishidu and the Secondary References Do Not Disclose or Suggest the
`Claimed Light Emitting Semiconductor Die.......................................31
`
`Grounds 7-9 Fail and Should be Denied Without Institution Because
`Ogawa and the Secondary References Do Not Disclose or Suggest the
`Claimed Light Emitting Semiconductor Die.......................................34
`
`IV. CONCLUSION ..............................................................................................37
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`
`
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`
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`- i -
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`
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`TABLE OF AUTHORITIES
`
`Cases
`
`Innova/Pure Water, Inc. v. Safari Water Filtration Systems, Inc.,
`381 F.3d 1111 (Fed. Cir. 2004) .....................................................................16
`
`SAS Institute Inc. v. Iancu,
`138 S. Ct. 1348 (2018) ...............................................................................1, 18
`
`Statutes
`
`35 U.S.C. § 154(a)(2) ...............................................................................................15
`
`35 U.S.C. § 316 ........................................................................................................18
`
`35 U.S.C. § 316(a)-(b) .............................................................................................19
`
`Rules
`
`37 C.F.R. § 42 ..........................................................................................................18
`
`37 C.F.R. § 42.100(b) ..............................................................................................15
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`37 C.F.R. § 42.104(b)(4) ..........................................................................................17
`
`37 C.F.R. § 42.107 ..................................................................................................... 1
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`37 C.F.R. § 42.108(a) ...............................................................................................18
`
`37 C.F.R. § 42.108(b) ..............................................................................................18
`
`37 C.F.R. § 42.108(c) ...............................................................................................18
`
`37 C.F.R. § 42.120(a) ................................................................................................. 1
`
`Other Authorities
`
`Office Patent Trial Practice Guide, 77 Fed. Reg. 48,612 (Aug. 14, 2012) .............19
`
`
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`- ii -
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`IPR2018-00965 Patent Owner’s Preliminary Response
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`Pursuant to 37 C.F.R. § 42.107, Patent Owner Document Security Systems,
`
`Inc. (“DSS” or “Patent Owner”) files this preliminary response to the Petition,
`
`setting forth reasons why the Petition for inter partes review (“IPR”) of U.S. Patent
`
`No. 7,919,787 (the “’787 patent”), claims 1-14, as requested by Nichia Corporation
`
`(“Petitioner”) should be denied.1
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`I.
`
`INTRODUCTION
`
`To obtain institution of a challenge presented in the Petition, the Board’s
`
`Rules require Petitioner to show that the challenge demonstrates a reasonable
`
`likelihood of success. The Board’s Rules also require an evaluation of all such
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`challenges on a ground-by-ground and claim-by-claim basis. Because SAS
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`Institute Inc. v. Iancu, 584 U.S. ___, 138 S. Ct. 1348 (2018), requires a binary
`
`institution decision, if any challenge in the Petition is deficient, there can be no
`
`institution of the entire Petition. Nichia’s Petition includes numerous deficient
`
`challenges, both against all grounds and claims in those grounds, which should
`
`result in no institution of an IPR against the ’787 patent.
`
`
`1 By submitting this Preliminary Response, no waiver of any argument is intended
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`by Patent Owner. Patent Owner will have a right to file “a response to the petition
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`addressing any ground for unpatentability not already denied” should the Board
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`institute inter partes review. 37 C.F.R. § 42.120(a).
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`-1-
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`IPR2018-00965 Patent Owner’s Preliminary Response
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`The ’787 patent, entitled “Semiconductor Device Incorporating with a Light
`
`Emitting Semiconductor Die,” discloses a semiconductor device having a
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`semiconductor die arranged on a packaging device. The packaging device includes
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`a substrate having opposed major surfaces and interconnecting elements arranged
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`on at least one sidewall of the substrate. A first interconnecting element connects a
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`bonding pad arranged on a first major surface of the substrate with a connecting
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`pad arranged on the other major surface (a second major surface) of the substrate.
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`The second interconnecting element connects another bonding pad arranged on the
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`first major surface of the substrate with another connecting pad arranged on the
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`second major surface of the substrate. A semiconductor die is arranged on the
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`packaging device, and more specifically on the bonding pads of the substrate.
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`To avoid use of a bonding wire linking the semiconductor die with a
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`bonding pad, the semiconductor die has both an anode and a cathode on a bottom
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`major surface of the semiconductor die, where the bottom major surface is also a
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`bottom surface of a substrate of the semiconductor die. The anode and cathode are
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`respectively connected to the conductive bonding pads on the first major surface of
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`the substrate. The bonding pads are respectively connected to connecting pads
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`arranged on a second major surface of the substrate via the interconnecting
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`elements.
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`-2-
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`IPR2018-00965 Patent Owner’s Preliminary Response
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`FIGS. 8A, 8B, and 8C of the ’787 patent show examples of such a
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`semiconductor device, where semiconductor device 800 includes semiconductor
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`die 750, bond pads 760 and 762, bonding pads 730 and 732, substrate 710,
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`connecting pads 740 and 742, and edge interconnecting elements 770 and 772.
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`The top view from FIG. 8A of this exemplary semiconductor device 800 and a side
`
`view from FIG. 8B are reproduced below:
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`
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`-3-
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`IPR2018-00965 Patent Owner’s Preliminary Response
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`
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`In this exemplary embodiment, the semiconductor die 750 has both an anode
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`and a cathode on a bottom major surface of the semiconductor die, respectively
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`connected to bond pads 760 and 762. Further, the bottom major surface of the
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`semiconductor die is also the bottom surface of a substrate of the semiconductor
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`die. Petitioner provided the following annotation of FIG. 7B in this Petition, with
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`the bottom major surface of semiconductor die 750 marked:
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`Pet., 11.
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`-4-
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`IPR2018-00965 Patent Owner’s Preliminary Response
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`However, Petitioner’s challenges against the ’787 patent set forth proposed
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`constructions of terms relating to “the LED” (Pet., 10)2 that unreasonably broaden
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`the scope of the challenged claims. Petitioner’s unreasonably broad constructions
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`include structures which do not have a light emitting semiconductor die with an
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`anode and a cathode formed on a bottom major surface of the semiconductor die,
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`the bottom major surface also being a bottom surface of a substrate of the
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`semiconductor die. Under the correct constructions, the asserted art fails to
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`disclose all features recited in the claims.
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`In particular, when properly construed, the claims are neither disclosed nor
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`suggested by the relied-upon art in the Petition. The primary references,
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`Lumbard,3 Ishidu,4 and Ogawa5 fail to disclose (either expressly or inherently) a
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`bottom major surface of the LED having both an anode and a cathode formed
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`thereon, where the bottom major surface is also bottom surface of a substrate of the
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`semiconductor die. Petitioner acknowledges this shortcoming, and therefore looks
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`2 Petitioner uses “LED” in the Petition to refer to a light emitting semiconductor
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`die. Pet., 5 n.2.
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`3 Ex. 1006, U.S. Patent No. Re. 36,614 (“Lumbard”).
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`4 Ex. 1010, U.S. Patent Application Publication No. 2006/0198162 (“Ishidu”).
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`5 Ex. 1011, U.S. Patent Application Publication No. 2006/0113906 (“Ogawa”).
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`-5-
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`IPR2018-00965 Patent Owner’s Preliminary Response
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`to secondary references Weeks,6 Wirth,7 and Negley8 in a failed attempt to remedy
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`these shortcomings. But Petitioner incorrectly considers the references’ features in
`
`isolation in its challenges. As result, each challenge is deficient and must be
`
`denied.
`
`II.
`
`PETITIONER FAILS TO ACCURATELY IDENTIFY THE SCOPE
`OF THE CLAIMS BEING CHALLENGED
`
`A. Disputed Claims
`
`Elements of an exemplary semiconductor device are claimed in the ’787
`
`patent, of which claims 1-14 are at issue in this IPR proceeding. In full, the
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`challenged claims of the ’787 patent recite (with the highlighting of the elements to
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`be addressed below):
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`1. A semiconductor device comprising:
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`a substantially planar substrate having first and second
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`major surfaces, the first and second major surfaces
`
`being opposed surfaces;
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`a light emitting semiconductor die comprising a top
`
`major light emitting surface and an oppositely-
`
`disposed bottom major surface, the light emitting
`
`
`6 Ex. 1007, U.S. Patent No. 6,611,002 (“Weeks”).
`
`7 Ex. 1008, International Patent Application Publication No. WO 2005/081319,
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`with English translation (“Wirth”).
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`8 Ex. 1009, U.S. Patent Application Publication No. 2004/0217360 (“Negley”).
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`-6-
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`IPR2018-00965 Patent Owner’s Preliminary Response
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`semiconductor die having an anode and a cathode
`
`on the bottom major surface of the light emitting
`
`semiconductor die, the anode and the cathode of
`
`the
`
`light emitting semiconductor die being
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`electrically connected
`
`to
`
`first and
`
`second
`
`electrically conductive bonding pads located on the
`
`first major surface,
`
`the semiconductor
`
`light
`
`emitting die being mounted on at least the first
`
`electrically conductive bonding pad such that one
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`of the anode and the cathode on the bottom major
`
`surface of the light emitting semiconductor die is
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`electrically connected to the first electrically
`
`conductive bonding pad;
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`first and second electrically conductive connecting pads
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`located on the second major surface;
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`a first electrically conductive interconnecting element
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`electrically connected to the first electrically
`
`conductive bonding pad and the first electrically
`
`conductive connecting pad; and
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`a second electrically conductive interconnecting element
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`electrically connected to the second electrically
`
`conductive bonding pad and the second electrically
`
`conductive connecting pad,
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`wherein the bottom major surface of the light emitting
`
`semiconductor die is a bottom surface of a
`
`substrate of the die, each of the anode and
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`cathode comprises a metallization layer formed
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`-7-
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`IPR2018-00965 Patent Owner’s Preliminary Response
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`on the bottom major surface of the light emitting
`
`semiconductor die.
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`
`
`2.
`
`The semiconductor device of claim 1 wherein at
`
`least one of the first and second electrically
`
`conductive interconnecting elements is on at least
`
`one sidewall of the substantially planar substrate
`
`and electrically interconnects one of the first and
`
`second electrically conductive bonding pads to one
`
`of the first and second electrically conductive
`
`connecting pads.
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`
`
`3.
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`The semiconductor device of claim 2 wherein the
`
`first
`
`electrically
`
`conductive
`
`interconnecting
`
`element is on a sidewall of the substantially planar
`
`substrate and electrically interconnects the first
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`electrically conductive bonding pad to the first
`
`electrically conductive connecting pad and the
`
`second electrically conductive
`
`interconnecting
`
`element is on the same sidewall or another
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`sidewall of the substantially planar substrate and
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`electrically interconnects the second electrically
`
`conductive bonding pad to the second electrically
`
`conductive connecting pad.
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`
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`4.
`
`The semiconductor device of claim 2 wherein the
`
`at least one of the first and second electrically
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`-8-
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`IPR2018-00965 Patent Owner’s Preliminary Response
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`conductive interconnecting elements is situated
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`within a partial cylindrical depression in the at
`
`least one sidewall of the substantially planar
`
`substrate.
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`
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`5.
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`The semiconductor device of claim 1, wherein the
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`light emitting semiconductor die is also mounted
`
`on the second electrically conductive bonding pad
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`such that the anode and the cathode of the light
`
`emitting
`
`semiconductor die, are electrically
`
`connected to the first and second electrically
`
`conductive bonding pads, respectively.
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`
`
`6.
`
`The semiconductor device of claim 1 wherein the
`
`light emitting semiconductor die is a light emitting
`
`diode die.
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`
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`7. A semiconductor device comprising:
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`a substantially planar substrate having first and second
`
`major surfaces, the first and second major surfaces
`
`being opposed surfaces;
`
`first and second electrically conductive bonding pads
`
`located on the first major surface;
`
`a light emitting semiconductor die comprising a top
`
`major light emitting surface and an oppositely-
`
`disposed bottom major surface, the light emitting
`
`semiconductor die having an anode and a cathode
`
`-9-
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`IPR2018-00965 Patent Owner’s Preliminary Response
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`on the bottom major surface of the light emitting
`
`semiconductor die,
`
`the semiconductor
`
`light
`
`emitting die being mounted on the first and second
`
`electrically conductive bonding pads such that the
`
`anode of the light emitting semiconductor die is
`
`electrically connected to the first electrically
`
`conductive bonding pad and the cathode of the
`
`light emitting semiconductor die is electrically
`
`connected to the second electrically conductive
`
`bonding pad;
`
`first and second electrically conductive connecting pads
`
`located on the second major surface;
`
`a first electrically conductive interconnecting element
`
`electrically connected to the first electrically
`
`conductive bonding pad and the first electrically
`
`conductive connecting pad; and
`
`a second electrically conductive interconnecting element
`
`electrically connected to the second electrically
`
`conductive bonding pad and the second electrically
`
`conductive connecting pad,
`
`wherein the bottom major surface of the light emitting
`
`semiconductor die is a bottom surface of a
`
`substrate of the die, each of the anode and
`
`cathode comprises a metallization layer formed
`
`on the bottom major surface of the light emitting
`
`semiconductor die.
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`
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`-10-
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`IPR2018-00965 Patent Owner’s Preliminary Response
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`8.
`
`The semiconductor device of claim 7 wherein at
`
`least one of the first and second electrically
`
`conductive interconnecting elements is on at least
`
`one sidewall of the substantially planar substrate
`
`and electrically interconnects one of the first and
`
`second electrically conductive bonding pads to one
`
`of the first and second electrically conductive
`
`connecting pads.
`
`
`
`9.
`
`The semiconductor device of claim 8 wherein the
`
`first
`
`electrically
`
`conductive
`
`interconnecting
`
`element is on a sidewall of the substantially planar
`
`substrate and electrically interconnects the first
`
`electrically conductive bonding pad to the first
`
`electrically conductive connecting pad and the
`
`second electrically conductive
`
`interconnecting
`
`element is on the same sidewall or another
`
`sidewall of the substantially planar substrate and
`
`electrically interconnects the second electrically
`
`conductive bonding pad to the second electrically
`
`conductive connecting pad.
`
`
`
`10. The semiconductor device of claim 8 wherein the
`
`at least one of the first and second electrically
`
`conductive interconnecting elements is situated
`
`within a partial cylindrical depression in the at
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`-11-
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`IPR2018-00965 Patent Owner’s Preliminary Response
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`least one sidewall of the substantially planar
`
`substrate.
`
`
`
`11. A semiconductor device comprising:
`
`a substantially planar substrate having first and second
`
`major surfaces, the first and second major surfaces
`
`being opposed surfaces;
`
`first and second electrically conductive bonding pads
`
`located on the first major surface;
`
`a light emitting semiconductor die comprising a top
`
`major light emitting surface and an oppositely-
`
`disposed bottom major surface, the light emitting
`
`semiconductor die having an anode and a cathode
`
`on the bottom major surface of the light emitting
`
`semiconductor die, the anode and the cathode of
`
`the
`
`light emitting semiconductor die being
`
`electrically connected to the first and second
`
`electrically
`
`conductive
`
`bonding
`
`pads,
`
`the
`
`semiconductor light emitting die being mounted on
`
`at least the first electrically conductive bonding
`
`pad such that one of the anode and the cathode on
`
`the bottom major surface of the light emitting
`
`semiconductor die is electrically connected to the
`
`first electrically conductive bonding pad;
`
`first and second electrically conductive connecting pads
`
`located on the second major surface;
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`-12-
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`IPR2018-00965 Patent Owner’s Preliminary Response
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`a first electrically conductive interconnecting element
`
`electrically connected to the first electrically
`
`conductive bonding pad and the first electrically
`
`conductive connecting pad; and
`
`a second electrically conductive interconnecting element
`
`electrically connected to the second electrically
`
`conductive bonding pad and the second electrically
`
`conductive connecting pad, wherein at least one of
`
`the
`
`first and second electrically conductive
`
`interconnecting elements is located on at least one
`
`sidewall of the substantially planar substrate,
`
`wherein the bottom major surface of the light emitting
`
`semiconductor die is a bottom surface of a
`
`substrate of the die, each of the anode and
`
`cathode comprises a metallization layer formed
`
`on the bottom major surface of the light emitting
`
`semiconductor die.
`
`
`
`12. The semiconductor device of claim 11 wherein the
`
`first
`
`electrically
`
`conductive
`
`interconnecting
`
`element is on a sidewall of the substantially planar
`
`substrate and electrically interconnects the first
`
`electrically conductive bonding pad to the first
`
`electrically conductive connecting pad and the
`
`second electrically conductive
`
`interconnecting
`
`element is on the same sidewall or another
`
`sidewall of the substantially planar substrate and
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`-13-
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`IPR2018-00965 Patent Owner’s Preliminary Response
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`electrically interconnects the second electrically
`
`conductive bonding pad to the second electrically
`
`conductive connecting pad.
`
`
`
`13. The semiconductor device of claim 11 wherein the
`
`at least one of the first and second electrically
`
`conductive interconnecting elements is situated
`
`within a partial cylindrical depression in the at
`
`least one sidewall of the substantially planar
`
`substrate.
`
`
`
`14. The semiconductor device of claim 11, wherein the
`
`light emitting semiconductor die is also mounted
`
`on the second electrically conductive bonding pad
`
`such that the anode and the cathode of the light
`
`emitting
`
`semiconductor die are electrically
`
`connected to the first and second electrically
`
`conductive bonding pads, respectively.
`
`’787 patent, 14:6-16:57.
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`
`
`B. Claim Construction
`
`The ’787 patent was filed in the United States on August 14, 2007 as a
`
`continuation-in-part of U.S. Patent Application No. 10/608,605, filed on June 27,
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`2003 (now U.S. Patent No. 7,256,486), and issued on April 5, 2011. Accordingly,
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`-14-
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`IPR2018-00965 Patent Owner’s Preliminary Response
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`the ’787 patent is not expected to expire prior to any Final Written Decision in this
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`IPR. See 35 U.S.C. § 154(a)(2); 37 C.F.R. § 42.100(b).
`
`Petitioner states that the Board applies the “broadest reasonable construction
`
`(‘BRI’) in light of the specification” to the ’787 patent. Pet., 10. Allegedly
`
`applying BRI, Petitioner proposes the following constructions “with respect to
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`limitations of the LED, not the substrate packaging assembly:”
`
` “[top] major light emitting surface” means “of the two largest faces of
`
`the LED, the face through which light is emitted;”
`
` “an oppositely-disposed [bottom] major surface” means “of the two
`
`largest faces of the LED, the face opposite the light emitting face;”
`
`and
`
` “the [bottom] major surface … is a bottom surface of a substrate of
`
`the die” means “the face of the LED opposite the light emitting face is
`
`on the substrate side of the LED.”
`
`Pet., 10-13 (emphasis added). As is clear from Petitioner’s proposed constructions,
`
`Petitioner incorrectly interprets the major surfaces of the LED to be synonymous
`
`with the largest faces of the LED. Petitioner repeats this unsupported exchange of
`
`terms in its analysis of the claims as well, stating that the ’787 patent “is consistent
`
`in its usage of ‘major surface’ to refer, as a matter of geometric orientation, to a
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`-15-
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`IPR2018-00965 Patent Owner’s Preliminary Response
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`face that is greater in size than the other faces of the element being described.”
`
`Pet., 11 (citing Ex. 1003, ¶¶49-51) (emphasis added).
`
`But Petitioner’s interpretation exceeds the broadest reasonable interpretation
`
`of “surface” according to the ’787 patent specification, and there is no justification
`
`presented in the Petition for this unsupported substitution of “surface” for “face” in
`
`the proposed constructions. The purpose of claim construction is not simply to
`
`identify potential synonyms of claim terms and swap them out without reason;
`
`rather, the purpose is to “accord a claim a meaning it would have to a person of
`
`ordinary skill in the art at the time of the invention.” Innova/Pure Water, Inc. v.
`
`Safari Water Filtration Systems, Inc., 381 F.3d 1111, 1116 (Fed. Cir. 2004).
`
`Confirming that Petitioner’s constructions are wrong and unreasonably
`
`broad, the ’787 patent does not use the term “face” to be synonymous with
`
`“surface.” While describing the semiconductor die 750, the ’787 patent explains
`
`that “semiconductor die 750 is a die with bond pads 760 and 762 on a lower major
`
`surface of the die, which is the surface that faces the substrate 710 when the die is
`
`mounted on a substrate.” ’787 patent, 12:35-38 (emphasis added). In this
`
`disclosure, the ’787 patent distinguishes between a semiconductor die’s surface
`
`and a facing direction of that surface. Petitioner and Dr. Shealy fail to identify any
`
`portion of the ’787 patent that uses the term “face” in a manner synonymous with
`
`“surface,” and in fact Dr. Shealy quotes a portion of the prosecution history in
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`-16-
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`IPR2018-00965 Patent Owner’s Preliminary Response
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`which the term “faces” was used as a verb, like in the example above, to describe a
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`surface’s facing direction. Ex. 1003, ¶53.
`
`As an additional defect, Petitioner applies its proposed construction in a
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`manner that fails to lend any weight to the claim term, “major.” In particular,
`
`Petitioner views a bottom side or bottom face of an LED as a “bottom major
`
`surface” without regard to where (or even whether) there exists a “major surface”
`
`on that face or side. Petitioner’s challenges simply point to a bottom face of side
`
`of the LEDs in the asserted references without taking the necessary step of
`
`identifying a “bottom major surface.” As a result, Petitioner’s Petition fails under
`
`37 C.F.R. § 42.104(b)(4) (the petition must identify “[h]ow the [correctly]
`
`construed claim is unpatentable.”).
`
`As will be discussed in more detail below, the Petition fails under the proper
`
`construction of “bottom major surface.” Primary references Lumbard, Ishidu, and
`
`Ogawa fail to disclose the claimed “light emitting semiconductor die” having the
`
`“bottom major surface” as claimed in the challenged claims. Further, the alleged
`
`bottom faces (or sides) of the LEDs in secondary references Weeks, Wirth, and
`
`Negley also fail to disclose a “bottom major surface” possessing all claimed
`
`features. Thus, each challenge necessarily fails.
`
`
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`-17-
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`IPR2018-00965 Patent Owner’s Preliminary Response
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`III. THE CHALLENGED CLAIMS ARE NOT UNPATENTABLE
`
`In order to justify the institution of an inter partes review, a petitioner must
`
`establish that there is a “reasonable likelihood that the petitioner would prevail
`
`with respect to at least 1 of the claims challenged in the petition.” 35 U.S.C. §
`
`314(a). Further, prior to SAS Institute Inc. v. Iancu, 584 U.S. ___, 138 S. Ct. 1348
`
`(2018), the Director, as required by 35 U.S.C. § 316, implemented regulations in a
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`manner that required claim-by-claim and ground-by-ground evaluation and
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`permitted claim-by-claim and ground-by-ground institution. See 37 C.F.R. § 42.
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`In particular, 37 C.F.R. § 42.108(a) allowed the Board to “authorize the
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`review to proceed on all or some of the challenged claims and on all or some of the
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`grounds of unpatentability asserted for each claim.” Additionally, 37 C.F.R. §
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`42.108(b) allowed the Board to “deny some or all grounds for unpatentability for
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`some or all of the challenged claims” prior to institution of inter partes review.
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`When denying a ground, 37 C.F.R. § 42.108(b) stated that such a “[d]enial of a
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`ground is a Board decision not to institute inter partes review on that ground.”
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`Moreover, under the heading “Sufficient grounds,” 37 C.F.R. § 42.108(c) provided
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`that “Inter partes review shall not be instituted for a ground of unpatentability
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`unless the Board decides that the petition supporting the ground would demonstrate
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`that there is a reasonable likelihood that at least one of the claims challenged in the
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`petition is unpatentable.” (emphasis added).
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`-18-
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`
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`IPR2018-00965 Patent Owner’s Preliminary Response
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`In implementing these final rules, the Agency stated, “[t]he Board will
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`identify the grounds upon which the review will proceed on a claim-by-claim
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`basis. Any claim or issue not included in the authorization for review is not part of
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`the review.” See 77 Fed. Reg. 48,689. Indeed, the Agency specifically stated that
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`the regulations did not adopt comments requesting that “all challenged claims to
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`be included in the inter partes review when there is a reasonable likelihood of
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`prevailing with respect to one challenged claim.” See 77 Fed. Reg. 48,702-03.
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`Post-SAS, and though required under 35 U.S.C. § 316(a)-(b), the Agency has
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`not issued new rules that would permit the Board to institute all grounds against all
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`challenged claims even though a petitioner failed to establish a reasonable
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`likelihood of prevailing on all challenged claims and all grounds. Therefore,
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`should the Board find any challenge to any claim deficient, the sole permissible
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`outcome, consistent with both the binary decision required under SAS and the
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`Board’s governing regulations, is for the Board to deny institution of this inter
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`partes review.
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`Here, Petitioner has failed to establish that each of the challenged ’787
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`patent claims are unpatentable over the asserted art. For the reasons discussed
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`below, the Board should deny the Petition and decline to institute the inter partes
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`review.
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`-19-
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`IPR2018-00965 Patent Owner’s Preliminary Response
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`A. Grounds 1-3 Fail and Should be Denied Without Institution
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`Claims 1-14 are challenged in Grounds 1-3 based on Lumbard in alternate
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`view of Weeks, Wirth, or Negley. But Weeks, Wirth, and Negley each fail to
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`remedy the shortcomings of Lumbard. As such, Petitioner’s challenge fails, and no
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`trial should be instituted against claims 1-14 based on these challenges of Grounds
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`1-3.
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`1.
`Lumbard Does Not Disclose or Suggest the Claimed Light
`Emitting Semiconductor Die
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`Claim 1 recites, in relevant part, a semiconductor device comprising “a light
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`emitting semiconductor die comprising a top major light emitting surface and an
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`oppositely-disposed bottom major surface, the light emitting semiconductor die
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`having an anode and a cathode on the bottom major surface of the light emitting
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`semiconductor die,” and the claim also requires that “the bottom major surface of
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`the light emitting semiconductor die is a bottom surface of a substrate of the die,
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`each of the anode and cathode comprises a metallization layer formed on the
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`bottom major surface of the light emitting semiconductor die.” (emphasis added).
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`Unpacking this claim language, claim 1 requires a surface of an LED die substrate,
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`having the anode and cathode formed of a metallization layer thereon, also be a
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`“bottom major surface” of the semiconductor die. Petitioner’s own annotation of
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`the ’787 patent’s FIG. 7B indicates an exemplary semiconductor die’s bottom
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`major surface:
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`-20-
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`IPR2018-00965 Patent Owner’s Preliminary Response
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`
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`Pet., 11. But the express terms of claim 1 are not satisfied simply by a
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`semiconductor die having an anode and cathode arranged on a bottom side of the
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`die. Rather, claim 1 requires the semiconductor die to have a bottom major
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`surface, or a bottom surface that is larger than other surfaces, where the anode and
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`cathode are both formed on that bottom major surface, and where that bottom
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`major surface is also a bottom surface of an LED die substrate.
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`As shown below, Lumbard discloses a light emitting diode encapsulated in a
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`transparent epoxy, and “light-emitting diode 15 is mounted on the land area 13 so
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`that its terminal on the underneath or back side is electrically and mechanically
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`coupled to the land area 13.” Lumbard, 3:4-10. On the top of light emitting diode
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`15, a bonding wire 17 connects a terminal 16 of the light emitting diode 15 with
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`the connection pad 14:
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`-21-
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`IPR2018-00965 Patent Owner’s Preliminary Response
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`
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`As is apparent from this figure, Petitioner acknowledges and agrees that
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`Lumbard does not “disclose that the oppositely-disposed LED surface (i.e., the
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`bottom surface or backside) has both an anode and a cathode on it.” Pet., 19.
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`Petitioner therefore looks to Weeks, Wirth, and Negley in an attempt to remedy
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`this shortcoming of Lumbard, though those references fail to do so.
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`2. Weeks Fails to Remedy Lumbard’s Shortcomings
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`Petitioner first looks to Weeks to provide the semiconductor die structure of
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`claim 1. Specifically, Petitioner alleges that “Weeks discloses a cathode and an
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`anode … on ‘backside 22’ of its LED, which refers to the bottom of ‘silicon
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`substrate 12’—i.e., the side opposite to the light emitting side.” Pet., 20.
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`Petitioner further alleges that both backside 22 and substrate 12 “correspond to the
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`claimed ‘oppositely-disposed bottom major surface … [that] is a bottom surface of
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`a substrate of the die.’” Pet., 21. Following these allegations, Petitioner includes
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`-22-
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`IPR2018-00965 Patent Owner’s Preliminary Response
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`the following annotation of Weeks’ FIG. 8:
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`
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`Pet., 21.
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`Initially, two defects in Petitioner’s theory are clear from this annotation.
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`First, Weeks does not include a “bottom major surface” that includes both an
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`anode and a cathode formed thereon. Rather, Petitioner generally and improperly
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`looks to the entire “backside 22” of Weeks’ LED 70 in an attempt to meet the
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`“bottom major surface” features of claim 1, without ever identifying a “major
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`surface” that meets all features of the claim. Indeed, backside contact 20b is not
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`formed on substrate 12, but
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