Universal Serial Bus Specification Revision 2.0
`
`buffers (continued)
`Transaction Translator buffers
`overview, 11.14.1
`resetting, 11.24.2.9
`space required, 11 .19
`underrun or overrun states and error
`counts , 10.2.6
`USBD role in allocating, 10.5.1 .2.1
`bulk transfers . See also non-periodic
`transactions
`buffering requirements, 11.14.2.2, 11 .17.4
`bus access constraints , 5.8.4
`data format, 5.8.1
`data sequences, 5.8.5
`defined, 2.0 glossary, 5.4
`direction, 5.8.2
`failures, 11.17 .5
`NAK rates for endpoints , 9.6.6
`non-periodic transactions, 11 .17 to 11 .17 .5
`overview, 4.7.2, 5.8
`packet size, 5.8.3, 9.6.6
`scheduling , 11 .14.2.2
`split transaction examples , A.1 , A.2
`split transaction notation for, 11.15
`state machines, 8.5.1 , 8.5.1.1, 8.5.2, 11.17 .2
`transaction format, 8.5.2
`transaction organization within IRPs, 5.11.2
`USBD pipe mechanism responsibilities,
`10.5.3.1.3
`bus access for transfers
`bulk transfer constraints, 5.8.4
`bus access periods , 5.12.8
`bus bandwidth reclamation , 5.11.5
`calculating buffer sizes , 5.11.4
`calculating bus transaction times, 5.11.3
`client software role in , 5.11 .1.1
`control transfer constraints, 5.5.4
`HCD role in, 5.11.1 .3
`Host Controller role in , 5.11 .1.5
`interrupt transfer constraints, 5.7.4
`isochronous transfer constraints, 5.6.4
`transaction list, 5.11 .1.4
`transaction tracking, 5.11.2
`transfer management, 5.1.1 to 5.11.1 .5
`transfer type overview, 5.4
`USBD role in, 5.11.1.2
`bus clock, 5.12.2, 5.12 .3, 5.12.8
`bus enumeration
`defined, 2.0 glossary
`device initialization , 10.5.1.1
`enumeration handling, 11 .12.6
`overview, 4.6.3, 9.1.2
`re-enumerating sub-trees, 10.5.4.5
`staged power switching in functions, 7.2.1.4
`USB System Software role, 4.9
`
`576
`
`bus-powered devices and functions
`configuration descriptors , 9.6.3
`defined, 4.3.1
`device states, 9.1 .1.2
`high-power bus-powered functions, 7.2.1.4
`low-power bus-powered functions, 7 .2.1.3
`power budgeting, 9.2.5.1
`bus-powered hubs
`configuration, 11 .13
`defined, 4.3.1 , 7.2.1
`device states , 9.1 .1.2
`overview, 7.2.1.1
`power switching , 11 .11
`voltage drop budget, 7.2.2
`bus protocol overview, 4.4
`Bus_Reset receiver state, 11.6.3, 11.6.3.9
`bus states
`evaluating after reset, 7.1.7.3
`global suspend, 7.1.7.6.1
`Host Controller role in state handling, 10.2.1
`signaling levels and , 7.1.7.1, 7.1.7.2
`Transaction Translator tracking , 11.14.1
`bus timing/electrical characteristics , 7 .3.2
`bus topology, 5.2 to 5.2.5
`client-software-to-function relationship, 5.2.5
`defined, 4.1
`devices, 5.2.2
`hosts, 5.2.1
`illustrated, 4.1.1
`logical bus topology, 5.2.4
`physical bus topology, 5.2.3
`bus transaction timeout in isochronous transfers,
`5.12.7
`bus turn-around time, 2.0 glossary, 7 .1.18 to
`7.1.18.2, 8.7.2, 11 .18.2
`busy (ready/x) state, 11.17 .5
`bypass capacitors, 7 .2.4.1, 7 .2.4.2
`bytes, defined, 2.0 glossary
`C
`cable assemblies, 6.4 to 6.4.4
`cable attenuation, 7 .1.17
`cable delay
`electrical characteristics , 7.3.2 Table 7-12
`high-/full-speed cables , 6.4.2
`hub differential delay, differential jitter, and
`SOP distortion, 7.3.3 Figure 7-52
`hub EOP delay and EOP skew, 7.3.3 Figure
`7-53
`hub signaling timings , 7.1.14.1
`inter-packet delay and , 7.1.18.1
`low-speed cables, 6.4.3, 7 .1.1.2
`overview, 7 .1 .16
`propagation delay, 6.4.1, 6.7 Table 6-7,
`7.1 .1.2
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`Universal Serial Bus Specification Revision 2.0
`
`cable delay (continued)
`skew delay, 6.7 Table 6-7, 7.1.3, 7.3.3 Figure
`7-53
`
`cables
`attenuation, 7.1.17
`cable assemblies, 6.4 to 6.4.4
`cable delay (See cable delay)
`captive cables
`high-/full-speed captive cable assemblies,
`6.4.2
`inter-packet delay and, 7 .1.18.1
`low-speed captive cable assemblies, 6.4.3
`maximum capacitance, 7.1.6.1
`termination, 7.1.5.1
`color choices, 6.4
`construction, 6.6.2
`description, 6.6.1
`detachable cables
`cable delay, 7 .1.16
`connectors and, 6.2
`detachable cable assemblies, 6.4.1
`inter-packet delay and, 7 .1.18.1
`low-speed detachable cables, 6.4.4
`maximum capacitance, 7.1.6.1
`termination, 7.1.5.1
`voltage drop budget, 7.2.2
`electrical characteristics and standards, 4.2.1,
`6.6.3, 6.7, 7.3.2 Table 7-12
`end-to-end signal delay, 7 .1.19.1
`environmental characteristics, 6.6.4, 6. 7
`flyback voltage, 7.2.4.2
`high-/full-speed cables, 6.4.2
`impedance, 6.4.1, 6.4.2, 6.7 Table 6-7
`input capacitance, 7 .1.6.1
`length, 6.4.1, 6.4.2, 6.4.3
`listing, 6.6.5
`low-speed cables, 6.4.3, 6.4.4, 7 .1.1.2
`mechanical configuration and material
`requirements, 6.6 to 6.6.5, 6.7
`overview, 6.3
`prohibited cable assemblies, 6.4.4
`pull-out standards, 6.7 Table 6-7
`shielding, 6.6, 6.6.1
`termination, 7.1.5.1
`voltage drop budget, 7.2.2
`calculations
`buffering for rate matching, 5.12.8
`buffer sizes in functions and software, 5.11.4
`bus transaction times, 5.11.3
`capabilities, defined, 2.0 glossary
`capacitance
`after dynamic attach, 7.2.4.1
`decoupling capacitance, 7.3.2 Table 7-7
`input capacitance, 7.1.6.1, 7.3.2 Table 7-7
`low-speed buffers, 7.1.1.2, 7.1.2.1
`low-speed cable capacitive loads, 6.4.3
`
`capacitance (continued)
`lumped capacitance guidelines for
`transceivers, 7.1.6.2
`optional edge rate control capacitors, 7 .1.6.1
`pull-up resistors and, 7.1.5.1
`single-ended capacitance, 7.1.1.2
`small capacitors, 7.1.6.1
`target maximum droop and, 7.2.4.1
`unmated contact capacitance, 7.3.2 Table 7-
`12
`capacitive load, 6.7 Table 6-7
`captive cables
`high-/full-speed captive cable assemblies,
`6.4.2
`inter-packet delay and, 7.1.18.1
`low-speed captive cable assemblies, 6.4.3
`maximum capacitance, 7.1.6.1
`rise and fall times, 7 .1.2.1, 7 .1.2.2
`TOR measurements and, 7 .1.6.2
`termination, 7.1.5.1
`change bits
`device states, 11.12.2
`hub and port status change bitmap, 11.12.4
`hub status, 11.24.2.6
`over-current status change bits, 11.12.5
`port status change bits, 11.24.2.7.2 to
`11.24.2.7.2.5
`Status Change endpoint defined, 11.12.1
`change propagation, host state handling of,
`10.2.1
`characteristics of devices, 2.0 glossary, 9.6.3,
`9.6.4
`Chirp J and K bus states, 7.1.4.2, 7.1.7.2,
`7.1.7.5, C.1, C.2.4
`C_HUB_LOCAL_POWER, 11.11, 11.24.2,
`11.24.2.1, 11.24.2.6, 11.24.2. 7 .1.6
`C_HUB_OVER_CURRENT, 11.24.2, 11.24.2.1
`C_HUB_OVER_POWER, 11.24.2.6
`classes of devices. See device classes
`Class field, 9.2.3, 9.6.5
`class-specific descriptors, 9.5, 11.23.2.1
`class-specific requests
`hub class-specific requests, 11.24.2 to
`11.24.2.13
`time limits for completing, 9.2.6.5
`USBDI mechanisms, 10.5.2.8
`Cleared timer status, C.O
`ClearFeature() request, CLEAR_FEATURE
`ClearHubFeature() request, 11.24.2.1
`ClearPortFeature() request, 11.24.2.2
`endpoint status and, 9.4.5
`hub class requests, 11.24.2
`hub requests, 11.24.1
`overview, 9.4.1
`standard device request codes, 9.4
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`Universal Serial Bus Specification Revision 2.0
`
`ClearHubFeature() request
`clearing hub features, 11 .24.2.6
`hub class requests, 11 .24.2
`hub class-specific requests , 11.24.2.1
`clearing pipes, 10.5.2.2
`ClearPortFeature() request
`clearing status change bits , 11.12.2,
`11 .24.2.7.2
`C_PORT _CONNECTION , 11.24.2.7.2.1
`C_PORT_ENABLE, 11 .24.2.7.2.2
`C PORT OVER-CURRENT, 11 .24.2.7 .2.4
`c ::::PoR{::RESET, 11 .24.2.7.2.5
`C_PORT _SUSPEND , 11.24.2.7.2.3
`hub class requests, 11 .24.2, 11.24.2.2
`PORT_CONNECTION , 11 .24.2.7.1.1
`PORT_ENABLE, 11 .5.1.4, 11.24.2.7.1.2
`PORT_HIGH_SPEED, 11.24.2.7.1.8
`PORT_INDICATOR, 11 .24.2.2, 11.24.2.7.1.10
`PORT_LOW_SPEED, 11 .24.2.7.1 .7
`PORT_ OVER_ CURRENT, 11.24.2. 7 .1.4
`PORT _POWER, 11.24.2.13
`PORT _POWER, 11 .5.1.2, 11.24.2.7 .1.6
`PORT_RESET, 11.24.2.7.1.5
`PORT _SUSPEND, 11 .5.1.10
`ClearTTBuffer() request, CLEAR_ TT _BUFFER
`checking for busy state, 11.17 .5
`hub class-specific requests, 11.24.2,
`11.24.2.3
`client pipes, 10.5.1.2.2
`client software
`in bus topology, 5.2, 5.2.1 , 5.2.5
`client software-to-function relationships, 5.2,
`5.2 .5
`in communication flow, 5.3
`control transfers and , 5.5
`defined, 2.0 glossary
`as implementation focus area, 5.1
`notification identification, 10.3.4
`role in configuration, 10.3.1
`role in data transfers, 10.3.3
`service clock and , 5.12.2
`in source-to-sink connectivity, 5.12.4.4
`in transfer management, 5.11.1, 5.11 .1.1
`clock model
`buffering for rate matching, 5.12.8
`bus clock, 5.12.2
`clock encoding scheme in electrical
`specifications overview, 4.2.1
`clock synchronization , 5.12.3
`clock-to-clock phase differences, 5.12.3
`clock tolerance, 11.7.1.3
`defined, 5.12
`frame clocks, 11 .18.3
`hub clock source, 11 .2.3
`in non-USB isochronous application, 5.12.1
`overview, 5.12.2
`
`578
`
`clock model (continued)
`receive clock, 11.7.1.2, 11.7.1.3
`sample clock, 5.12.2
`service clock , 5.12.2
`transmit clock, 11.7.1.3
`using SOF tokens as clocks, 5.12.5
`clock timings, 7.3.2 Table 7-8, 7.3.2 Table 7-9,
`7.3.2 Table 7-10
`CMOS driver circuit, 7 .1.1.1
`CMOS implementations, 7.1.1.3
`codes . See specific types of codes
`Collision conditions, 11 .8.3
`color choices
`cables, 6.4
`indicator lights on devices, 11.5.3 to 11.5.3.1
`plugs, 6.5.4.1
`receptacles, 6.5.3.1
`commanded stalls , 8.4.5
`commands. See requests
`common mode range for differential input
`sensitivity, 7 .1.4.1
`Communication Cables (UL Subject-444), 6.6.5,
`6.7.1
`communication flow, 5.3 to 5.3.3
`Compare_BC_buff algorithm , 11.17.1
`completed operations , 9.2.6
`completed transactions , 11 .3.3
`complete-split transactions
`buffering , 11.14.2.1, 11 .17
`bulk/control transactions, 11.17, 11.17 .1
`CSPLIT transaction tokens , 8.4.2.3
`defined, 11 .14.1.2
`isochronous transactions, 11.21
`notation for, 11.15
`overview, 11.14.1
`scheduling, 11.14.2.1 , 11 .18.4
`space for, 11.18.6.3
`split transaction overview, 8.4.2, 8.4.2.1
`TT state searching, 11.18.8
`completion times for hub requests, 11.24.1
`composite devices, 5.2 .3
`compound devices
`bus-powered hubs, 7 .2.1.1
`in bus topology, 5.2.3
`defined, 4.8.2.2
`hub descriptors for, 11 .23.2.1
`power configuration , 11 .13
`self-powered hubs, 7.2.1.2
`conditions in state machine transitions, 8.5,
`11.15
`conductor resistance unbalance, 6.6.3
`conductors
`mechanical specifications , 4.2.2
`power and signal conductors in cables, 6.3,
`6.6.2
`resistance, 6.6.3
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`PA_0001788
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`Universal Serial Bus Specification Revision 2.0
`
`configuration
`bus enumeration, 4.6.3, 9.1.2
`configuration management, 10.5.4.1.1
`Configured device state, 9.1.1.5
`control transfers and, 5.5.4
`descriptors, 5.3.1.1, 9.4.3, 9.5, 9.6.1 to 9.6.4,
`11.23.1 (See also descriptors)
`device attachment, 4.6.1
`device configuration, 10.3.1
`device removal, 4.6.2, 10.5.4.1.4
`function configuration, 10.3.1
`hubs, 11.13
`information in device characteristics, 4.8.1
`initial device configuration, 10.5.4.1.2
`interrupt transfers and, 5.7.4
`modifying device configuration, 10.5.4.1.3
`multiple configurations, 9.6.1
`multiple interfaces, 9.2.3
`operations overview, 9.2.3
`other-speed configurations, 9.6.2
`power distribution and, 7.2.1
`remote wakeup capabilities, 9.2.5.2
`requests
`configuration requests, 5.11.1.2
`GetConfiguration() request, 9.4.2
`SetConfiguration() request, 9.4. 7
`required configurations before usage, 10.3.1
`USB configuration, 10.3.1
`USBDI mechanisms for getting current
`settings, 10.5.2.4
`USBD role in, 5.11.1.2, 10.5.4.1 to 10.5.4.1.4
`Configuration = 0 signal/event, 11.5 Table 11-5
`CONFIGURATION descriptor, 9.4 Table 9-5
`configuration descriptors, 9.4.3, 9.6.4, 11.23.1
`Configured device state
`in bus enumeration process, 9.1.2
`overview, 9.1.1.5
`standard device requests and, 9.4.1 to 9.4.11
`visible device state table, 9.1.1 Table 9-1
`configuring software, defined, 2.0 glossary
`Connect bus state, 7.1.7.1, 7.1.7.3
`connecting devices. See dynamic insertion and
`removal
`connection status, 11.24.2.7.2, 11.24.2.7.2.1
`connectivity
`audio connectivity, 5.12.4.4.1
`hub fault recovery mechanisms, 11.1.2.3
`Hub Repeater responsibilities, 11.1
`hubs, 11.1, 11.1.2 to 11.1.2.3
`packet signaling connectivity, 11.1.2.1
`resume connectivity, 11.1.2.2
`source/sink connectivity, 5.12.4.4
`synchronous data connectivity, 5.12.4.4.2
`tearing down, 11.2.5
`
`connectors
`input capacitance, 7 .1.6.1
`inrush current and, 7.2.4.1
`interface and mating drawings, 6.5.3, 6.5.4
`keyed connector protocol, 6.2
`mechanical configuration and material
`requirements, 4.2.2, 6.5 to 6.5.4.3
`orientation, 6.5.1
`reference times, 7 .1.6.2
`Series "A" and Series "B" plugs, 6.5.4
`Series "A" and Series "B" receptacles, 6.5.3
`standards for, 6.7
`termination data, 6.5.2
`USB Icon, 6.5
`construction, cable, 6.6.2
`contact arcing, minimizing, 7.2.4.1
`contact capacitance standards, 6.7 Table 6-7
`contact current rating standards, 6.7 Table 6-7
`contact materials, 6.5.3.3, 6.5.4.3
`control endpoints, 2.0 glossary. See also control
`transfers
`controlling hubs, defined, 7.1.7.7
`control mechanisms
`device states and control information, 11.12.2
`Host Controller control flow management, 4.9
`of USB host, 10.1.2
`control pipes, 2.0 glossary. See also control
`transfers; message pipes; pipes
`control transfers. See also non-periodic
`transactions
`buffering, 11.14.2.2, 11.17.4
`bus access constraints, 5.5.4
`control pipes in device characteristics, 4.8.1
`data format, 5.5.1
`data sequences, 5.5.5
`defined, 2.0 glossary, 5.4
`device requests, 9.3
`direction, 5.5.2
`error handling on last data transaction, 8.5.3.3
`failures, 11.17 .5
`full-speed limits, 5.5.4 Table 5-2
`high-speed limits, 5.5.4 Table 5-3
`low-speed limits, 5.5.4 Table 5-1
`NAK rates for endpoints, 9.6.6
`non-periodic transactions, 11.17 to 11.17 .5
`overview, 4.7.1, 5.5
`packet size, 5.5.3, 9.6.6
`protocol stalls, 8.4.5
`reporting status results, 8.5.3.1
`scheduling, 11.14.2.2
`simultaneous transfers, 5.5.4
`split transaction examples, A.1, A.2
`split transaction notation for, 11.15
`stages, 2.0 glossary, 5.5
`STALL handshakes returned by control pipes,
`8.5.3.4
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`579
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`
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`Universal Serial Bus Specification Revision 2.0
`
`control transfers (continued)
`state machines, 8.5.1, 8.5.1.1, 8.5.2, 11.17 .2
`transaction format, 8.5.3
`transaction organization within IRPs, 5.11.2
`USBD pipe mechanism responsibilities,
`10.5.3.1.4
`variable-length data stage, 8.5.3.2
`converting split transactions, 11.14.1
`corrupted transfers and requests
`in control transfers, 8.5.3
`corrupted ACK handshake, 8.5.3.3, 8.6.4
`corrupted CRCs, 10.2.6
`corrupted IN tokens, 8.4.6.1
`corrupted PIDs, 8.3.1
`corrupted SOF packets in isochronous
`transfers, 5.12.6
`in data toggle, 8.6.3
`error detection and recovery, 8.7 to 8.7.4
`function response to OUT transactions,
`8.4.6.3
`host response to IN transactions, 8.4.6.2
`NAK or STALL handshake, 8.6.3
`costs of implementation, 3.3
`C PORT CONNECTION
`-
`-
`clearing, 11.24.2.2
`defined, 11.24.2.7.2.1
`hub class feature selectors, 11.24.2
`Port Change field, 11.24.2.7.2
`port status changes, 11.24.2.7.1.10
`SetPortFeature() request, 11.24.2.13
`C PORT ENABLE
`-
`-
`ClearPortFeature() request, 11.24.2.2
`defined, 11.24.2.7.2.2
`hub class feature selectors, 11.24.2
`Port Change field, 11.24.2.7.2
`SetPortFeature() request, 11.24.2.13
`C PORT OVER CURRENT
`-
`-
`-
`clearing, 11.24.2.2
`defined, 11.24.2.7.2.4
`hub class feature selectors, 11.24.2
`over-current conditions, 11.11.1, 11.12.5
`Port Change field, 11.24.2.7.2
`SetPortFeature() request, 11.24.2.13
`C PORT RESET
`-
`-
`clearing, 11.24.2.2
`defined, 11.24.2.7.2.5
`hub class feature selectors, 11.24.2
`Port Change field, 11.24.2.7.2
`SetPortFeature() request, 11.24.2.13
`C PORT SUSPEND
`-
`-
`clearing, 11.24.2.2
`defined, 11.24.2.7.2.3
`hub class feature selectors, 11.24.2
`Port Change field, 11.24.2.7.2
`resume conditions and, 11.4.4
`SetPortFeature() request, 11.24.2.13
`
`580
`
`CRCs
`in bulk transfers, 8.5.2
`corrupted CRCs, 10.2.6
`CRC16 handling, 11.15, 11.18.5, 11.20.3,
`11.20.4, 11.21.3, 11.21.4
`CRC check failures, 11.15, 11.20.3, 11.20.4,
`11.21.3, 11.21.4
`in data packets, 8.3.5.2, 8.4.4
`defined, 2.0 glossary
`in error detection, 8.7.1
`overview, 8.3.5
`protection in isochronous transfers, 5.12.7
`resending, 8.6.4
`in token packets, 8.3.5.1, 8.4.1
`USB robustness and, 4.5, 4.5.1
`cross-over points of data lines, 7 .1.13.2.1
`cross-over voltage in signaling, 7.1.2.1
`crystal capacitive loading, 7 .1.11
`CSPLIT (complete-split transactions). See
`complete-split transactions
`CTI, 2.0 glossary, 3.1
`current
`current averaging profile, 7.2.3
`current spikes during suspend/resume, 7.2.3
`high-speed current driver, 7.1 Table 7-1
`high-speed signaling and, 7.1.1.3
`supply current, 7.3.2 Table 7-7
`current frame in hub timing, 11.2.3.1
`current limiting
`bus-powered hubs, 7 .2.1.1
`dynamic attach and detach, 7.2.4.1
`in over-current conditions, 11.12.5
`power control during suspend/resume, 7.2.3
`remote wakeup and, 7.2.3
`self-powered functions, 7 .2.1.5
`cyclic redundancy check. See CRCs
`D
`D+ or D- lines
`average voltage, 7.1.2.1
`high-speed signaling and, 7.1, 7.1.1.3
`impedance, 7.1.6.1
`pull-up resistors and, 7.1
`signaling levels and, 7.1.7.1
`signal termination, 7.1.5.1
`during signal transitions, 7 .1.4.1
`single-ended capacitance, 7.1.1.2
`standardized contact terminating
`assignments, 6.5.2
`test mode, 7.1.20
`data
`data defined, 5.12.4
`data encoding/decoding, 7 .1.8
`data prebuffering, 5.12.5
`data processing role of Host Controller, 10.2.4
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`PA_0001790
`
`

`

`Universal Serial Bus Specification Revision 2.0
`
`DATAO/DATA1/DATA2 PIDs
`in bulk transfers, 5.8.5, 8.5.2
`comparing sequence bits, 8.6.2
`in control transfers, 8.5.3
`in data packets, 8.4.4
`high-bandwidth transactions and, 5.9.1, 5.9.2
`high-speed DATA2 PIDs, 8.3.1 Table 8-1
`in interrupt transactions, 5. 7 .5, 8.5.4, 11.20.4
`synchronization and, 8.6
`Transaction Translator response generation,
`11.18.5
`data field in packets, 8.3.4, 8.4.4
`data flow model. See transfers
`data flow types. See transfer types
`data formats. See also specific types of transfers
`bulk transfers, 5.8.1
`control transfers, 5.5.1
`interrupt transfers, 5. 7 .1
`isochronous transfers, 5.6.1, 5.12.4
`overview, 5.4
`Data J state. See J bus state
`Data K bus state. See K bus state
`data packets
`bus protocol overview, 4.4
`data CRCs, 8.3.5.2
`in isochronous transfers, 8.5.5
`packet field formats, 8.3 to 8.3.5.2
`packet overview, 8.4.4
`spreading over several frames, 5.5.4
`data payload
`bulk transfers, 5.8.3
`calculating transaction times, 5.11.3
`defined, 5.3.2
`interrupt transfers, 5. 7 .3
`isochronous transfers, 5.6.3
`maximum sizes, 8.4.4
`non-zero data payload, 5.6.3
`packet size constraints, 5.5.3, 5.6.3
`data phases
`aborting, 11.18.6.1
`transaction notation for, 11.15
`data PIDs. See DATAO/DATA1/DATA2 PIDs;
`DATAO/DATA1 PIDs; MDATA PIDs
`data rates
`adaptive endpoints, 5.12.4.1.3
`asynchronous endpoints, 5.12.4.1.1
`in buffering calculations, 5.12.8
`data-rate tolerance, 7 .1.11
`defined, 5.12.4
`in electrical specifications overview, 4.2.1
`feedback for isochronous transfers, 5.12.4.2
`full-speed source electrical characteristics,
`7.3.2 Table 7-9
`high-speed source electrical characteristics,
`7.3.2 Table 7-8
`
`data rates (continued)
`low-speed source electrical characteristics,
`7.3.2 Table 7-10
`overview, 7.1.11
`sample clock and, 5.12.2
`synchronous endpoints, 5.12.4.1.2
`data recovery unit, 11. 7 .1.2
`data retry indicators in control transfers, 5.5.5
`data sequences
`bulk transfers, 5.8.5
`control transfers, 5.5.5
`interrupt transfers, 5. 7 .5
`isochronous transfers, 5.6.5
`data signaling, 7.1.7.4 to 7.1.7.4.2
`data signal rise and fall time. See rise and fall
`times
`data source jitter, 7.1.13.1 to7.1.13.1.2,
`7.1.14.2, 7.1.15.1
`data source signaling, 7.1.13 to 7.1.13.2.2
`Data stage
`in control transfers, 5.5, 5.5.5, 8.5.3
`error handling on last data transaction, 8.5.3.3
`length of data, 9.3.5
`packet size constraints, 5.5.3
`variable-length data stages, 8.5.3.2
`data toggle
`bulk transfers, 5.8.5
`in bulk transfers, 8.5.2
`corrupted ACK handshake, 8.6.4
`data corrupted or not accepted, 8.6.3
`in data packets, 8.4.4
`data toggle sequencing, 8.5.5
`high bandwidth transactions and, 5.9.1
`initialization via SETUP token, 8.6.1
`in interrupt transactions, 8.5.4
`interrupt transfers and, 5.7.5
`low-speed transactions, 8.6.5
`overview, 8.6
`successful data transactions, 8.6.2
`data transfers. See data packets; Data stage;
`transfers
`DC electrical characteristics, 7.3.2 Table 7-7
`DC output voltage specifications, 7 .1.6.2
`DC resistance of plugs, 6.6.3
`debounce intervals in connection events, 7.1.7.3
`debouncing connections, 11.8.2
`declarations in state machines
`global declarations, B.1
`Host Controller declarations, B.2
`Transaction Translator declarations, B.3
`decoupling capacitance, 7.3.2 Table 7-7
`default addresses of devices, 2.0 glossary,
`9.1.1.4, 10.5.1.1
`Default bus state, 7.1.7.5
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`Default Control Pipe
`in bus enumeration process, 9.1.2
`in communication flow, 5.3
`control transfer packet size constraints, 5.5.3
`defined, 4.4, 5.3.2
`endpoint zero requirements, 5.3.1.1
`as message pipe, 5.3.2.2
`size description in descriptors, 9.6.1
`Default device state
`overview, 9.1.1.3
`standard device requests and, 9.4.1 to 9.4.11
`visible device state table, 9.1.1 Table 9-1
`default pipes, 2.0 glossary, 10.5.1.2.1
`delays. See cable delay; differential delay;
`propagation delay
`delivery rates in isochronous transfers, 4.7.4
`DEOP signal/event, 11.7.2.3 Table 11-11
`descriptor index, 9.4.3, 9.4.8
`descriptors
`accessing, 11.23.1
`in bus enumeration process, 9.1.2
`class-specific descriptors, 9.5, 11.23.2.1
`configuration descriptors, 9.6.3, 9.6.4, 10.3.1,
`10.5.2.4
`control transfers and, 5.5, 5.5.3
`defined, 9.5
`descriptor index, 9.4.3, 9.4.8
`device class definitions, 9.7, 9.7.1
`device descriptors, 9.4 Table 9-5, 9.6.1 to
`9.6.5
`endpoint descriptors, 9.6.6
`getting descriptors, 9.4.3, 10.5.2.3
`hub descriptors, 11.23 to 11.23.2.1, 11.24.2.5,
`11.24.2.10
`interface descriptors, 9.2.3, 9.6.5
`isochronous transfer capabilities, 5.12
`listing remote wakeup capabilities, 9.2.5.2
`other speed configuration descriptor, 9.6.4
`overview, 9.5 to 9.7.3
`setting descriptors, 5.3.1.1, 9.4.8, 10.5.2.12
`speed dependent descriptors, 9.2.6.6, 9.6.4
`string descriptors, 9.6.7
`USBDI mechanisms for getting descriptors,
`10.5.2.3
`vendor-specific descriptors, 9.5
`deserialization of transmissions, 10.2.2
`detachable cables
`cable delay, 7 .1.16
`connectors and , 6.2
`detachable cable assemblies, 6.4.1
`inter-packet delay and, 7.1.18.1
`low-speed detachable cables, 6.4.4
`maximum capacitance, 7.1.6.1
`termination, 7.1.5.1
`voltage drop budget, 7.2.2
`detached devices, 9.1.1.1, 9.1.2
`
`582
`
`detaching devices. See dynamic insertion and
`removal
`detecting connect and disconnect conditions,
`7.1.7.3, 7.1.20
`detecting errors. See error detection and
`handling
`detecting hub and port status changes, 7.1.7.5,
`11.12.2, 11.12.3, 11.12.4
`detecting over-current conditions, 7.2.1.2.1
`detecting speed of devices. See speed detection
`Detection mechanism, 7.1.5.2
`Dev_Do_BCINTI state machine, 8.5.2 Figure 8-
`34
`Dev_Do_BCINTO state machine, 8.5.2 Figure 8-
`32
`Dev_Do_lN state machine, 8.5 Figure 8-25
`Dev_Do_lsochl state machine, 8.5.5 Figure 8-43
`Dev_Do_lsochO state machine, 8.5.5 Figure 8-
`41
`Dev_Do_OUT state machine, 8.5 Figure 8-24
`Dev_HS_BCO state machine, 8.5.1.1 Figure 8-
`29
`Dev_HS_ping state machine, 8.5.1.1 Figure 8-28
`device addresses, 2.0 glossary. See also
`addresses; devices
`device classes. See also USB device framework
`class codes, 9.2.3
`defined, 4.8
`descriptors, 9.2.3, 9.6.1, 9.7
`device characteristics, 4.8.1
`device class definitions, 9.7
`device qualifier descriptors, 9.6.2
`getting class-specific descriptors, 9.5
`hub class-specific requests, 11.24.2 to
`11.24.2.13
`interfaces and endpoint usage, 9.7.2
`requests, 9.7.3
`standard, class, and vendor information, 4.8.1
`Device Class Specification for Audio Devices
`Revision 1.0, 9.6
`DEVICE descriptor, 9.4 Table 9-5
`device descriptors
`descriptor types, 9.4 Table 9-5
`device class descriptors, 9.2.3, 9.7
`device qualifier descriptors, 9.6.2
`GetDescriptor() request, 9.4.3
`getting class-specific descriptors, 9.5
`hubs, 11.23.1
`overview, 9.6.1
`speed dependent descriptors, 9.2.6.6
`standard definitions, 9.6.1 to 9.6.5
`device drivers, 5.12.4.4, 10.3.1
`device endpoints, 2.0 glossary, 5.3.1.1. See also
`endpoints
`device-initiated resume. See remote wakeup
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`Universal Serial Bus Specification Revision 2.0
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`Device layer
`descriptors, 9.5 to 9.7.3
`device states, 9.1 to 9.1.2
`generic USB device operations, 9.2 to 9.2.7
`standard device requests, 9.4 to 9.4.11
`in USB device framework, 9
`USB device requests, 9.3 to 9.3.5
`Device_Process_trans state machine, 8.5 Figure
`8-23
`device qualifier descriptors, 9.2.6.6, 9.4.3, 9.4
`Table 9-5, 9.6.1, 9.6.2
`Device release numbers, 9.6.1
`DEVICE_REMOTE_WAKEUP, 9.4 Table 9-6
`DeviceRemovable field (hub descriptors),
`11.23.2.1
`device resources, 2.0 glossary. See also buffers;
`endpoints
`devices. See also USB device framework
`address assignment, 9.1.2, 9.2.2
`characteristics and configuration (See also
`device descriptors)
`configuration, 4.8.2.2, 9.2.3
`data-rate tolerance, 7 .1.11
`descriptors, 9.5 to 9.7.3, 9.6.1
`device characteristics, 4.8.1
`device classes, 4.8, 9.7
`device descriptions, 4.8.2 to 4.8.2.1
`device speed, 7.1.5 to 7.1.5.2, 7.1.7.3,
`11.8.2
`host role in configuration, 10.3.1
`optional endpoints, 5.3.1.2
`USBD role in configuration, 10.5.4.1 to
`10.5.4.1.4
`data transfer, 9.2.4
`communication flow requirements, 5.3
`control transfers and, 5.5
`detailed communication flow illustrated, 5.3
`differing bus access for transfers, 5.11
`jitter budget table, 7 .1.15.1
`PING flow control, 8.5.1, 8.5.1.1
`response to IN transactions, 8.4.6.1
`response to OUT transactions, 8.4.6.3
`response to SETUP transactions, 8.4.6.4
`role in bulk transfers, 8.5.2
`device event timings, 7.3.2 Table 7-14
`devices defined, 2.0 glossary
`device state machines, 8.5
`dynamic attach and detach, 9.2.1
`power distribution, 7.2.4 to 7.2.4.2
`removing, 10.5.2.6, 10.5.4.1.4
`USBDI mechanisms, 10.5.2.5, 10.5.2.6
`generic USB device operations, 9.2 to 9.2.7
`port indicators, 11.5.3 to 11.5.3.1
`
`devices (continued)
`power distribution, 7.2.1, 9.2.5
`bus-powered devices, 4.3.1, 7.2.1.1
`dynamic attach and detach, 7.2.4 to 7.2.4.2
`high-power bus-powered functions, 7.2.1.4
`low-power bus-powered functions, 7 .2.1.3
`power supply and, 4.3.1
`self-powered devices, 4.3.1, 7.2.1.2, 7.2.1.5
`suspend/resume conditions, 7 .2.3
`voltage drop budget, 7.2.2
`requests
`host communication, 10.1.1
`request errors, 9.2.7
`request processing, 9.2.6 to 9.2.6.6
`standard device requests, 9.4 to 9.4.11
`USB device requests, 9.3 to 9.3.5
`state machines, 8.5, 8.5.2, 8.5.5
`status
`device states, 9.1 to 9.1.2, 11.12.2
`getting device status, 9.4.5
`getting port status, 11.24.2.7.1.1
`subtree devices after wakeup, 10.5.4.5
`turn-around timers, 8.7.2
`types of devices
`composite devices, 5.2.3
`compound devices, 4.8.2.2, 5.2.3
`functions, 4.8.2.2
`hubs, 4.8.2.1
`mapping physical and virtual devices,
`5.12.4.4
`virtual devices, 2.0 glossary
`in USB topology, 4.1.1.2, 5.2, 5.2.2, 9.0
`device software, defined, 2.0 glossary
`device state machines, 8.5. See also specific
`state machines under Dev
`diameter of cables, 6.6.2
`diamond symbols in state machines, 8.5, 11.15
`dielectric withstanding voltage standards, 6.7
`Table 6-7
`Differential O bus state, 7.1.7.2
`Differential 1 bus state, 7.1.7.1, 7.1.7.2
`Differential 2 bus state, 7.1.7.1
`differential data jitter, 7 .3.3 Figure 7-49, 7 .3.3
`Figure 7-52
`differential delay, 7.3.2 Table 7-11, 7.3.3 Figure
`7-52
`differential-ended components in upstream
`ports, 11.6.1, 11.6.2
`differential envelope detectors, 7.1
`differential input receivers, 1, 7 .1, 7 .1.4.1, 7 .1.6,
`7.1 Table 7-1
`differential output drivers, USBD as, 7 .1.1
`differential signaling, 7.1.7.1, 7.1.7.2, 7.1.7.4.1
`differential termination impedance, 7.1.6.2
`differential-to-EOP transition skew, 7.3.3 Figure
`7-50
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`Universal Serial Bus Specification Revision 2.0
`
`dimensional inspection standards, 6.7 Table 6-7
`Direction bit, 9.3.1, 9.3.4
`direction of communication flow, 5.4
`bmRequestType field, 9.3.1
`bulk transfers, 5.8.2
`bus protocol overview, 4.4
`control transfers, 5.5.2
`interrupt transfers, 5. 7 .2
`isochronous transfers, 5.6.2
`disabled ports, 11.5, 11.5.1.4, 11.24.2. 7 .1,
`11.24.2.7.2
`Disabled state, 11.5, 11.5.1.4
`disabling features, 9.4.1
`discarding packets, 11.3.2
`Disconnect_Detect signal/event, 11.5.2, 11.5
`Table 11-5
`Disconnected state
`connect and disconnect signaling, 7.1.7.3
`detecting, 7.1, 7.1.4.2, 7.1.20
`downstream ports, 11.5, 11.5.1.3
`signaling levels and, 7.1.7.1, 7.1.7.2
`disconnecting devices. See dynamic insertion
`and removal
`disconnection envelope detectors, 7.1.7.3, 7.1
`Table 7-1
`disconnect timer, 11.5.2
`distortion, minimizing in SOP, 7.1.7.4.1
`DLL lock, 7 .1
`documents, applicable standards, 6. 7 .1
`down counters in hub timing, 11.2.3.1
`downstream facing ports and hubs
`Disconnect state detection, 7.1
`downstream connectivity defined, 11.1.2.1
`downstream defined, 2.0 glossary
`downstream facing port state machine, 11.5
`downstream plugs, 6.2
`downstream ports defined, 4.8.2.1
`driver speed and, 7.1.2.3
`enumeration handling, 11.12.6
`high-speed driver characteristics and, 7.1.1.3
`high-speed signaling and, 7.1.7.6.1, 7.1.7.6.2,
`11.1.1
`in hub architecture, 11.1.1
`hub delay, 7.3.3 Figure 7-52
`hub descriptors, 11.23.2.1
`hub EOP delay and EOP skew, 7.3.3 Figure
`7-53
`input capacitance, 7 .1.6.1
`jitter, 7.3.2 Table 7-10
`multiple Transaction Translators, 11.14.1.3
`port state descriptions, 11.5.1 to 11.5.1.14
`reset state machines, C.1
`signaling delays, 7.1.14.1
`signaling speeds, 7 .1
`status changes, 11.12.6
`test mode support, 7.1.20
`
`584
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`downstream facing ports and hubs (continued)
`transceivers, 7.1, 7.1.7.1, 7.1.7.2
`downstream facing transceivers, high-speed
`signaling and, 7, 7.1
`downstream packets (HSD1 ), 8.5, 11.15
`drain wires, 6.5.2, 6.6.1, 6.6.2
`dribble, defined, 7.1.9.1
`drift, 5.12.1, 5.12.3
`driver characteristics
`full-speed driver characteristics, 7 .1.1.1
`full-speed source electrical characteristics,
`7.3.2 Table 7-9
`high-speed driver characteristics, 7 .1.1.3
`high-speed source electrical characteristics,
`7.3.2 Table 7-8
`low-speed driver characteristics, 7 .1.1.2, 7 .1
`Table 7-1
`low-speed source electrical characteristics,
`7.3.2 Table 7-10
`overview, 7.1.1
`drivers
`defined, 2.0 glossary
`role in configuration, 10.3.1
`in source-to-sink connectivity, 5.12.4.4
`droop, 7.2.3, 7.2.4.1
`dual pin-type receptacles, 6.9
`durability standards, 6.7 Table 6-7
`DWORD, defined, 2.0 glossary
`dynamic insertion and removal, 9.2.1
`attaching devices, 4.6.1
`defined, 2.0 glossary
`detecting insertion and removal, 4.9, 9.2.1
`Hub Repeater responsibilities, 11.1
`hub support for, 11.1
`power control, 7.2.3, 7.2.4 to 7.2.4.2
`power-on and connection events timing,
`7.1.7.3
`removing devices, 4.6.2
`USB robustness and, 4.5
`E
`E field (End), 8.4.2.2
`E2PROM defined, 2.0 glossary
`ease-of-use considerations, 1.1
`EBEmptied signal/event, 11.7.1.4 Table 11-10
`edges of signals
`cable delay, 7 .1.16
`data source jitter, 7.1.13.1.1
`edge transition density, 8.2
`optional edge rate control capacitors, 7.1.6.1
`EEPROM, defined, 2.0 glossary
`elasticity buffer, 11. 7 .1.3
`Electrical Connector/Socket Test Procedures,
`6.7.1
`Electrically Erasable Programmable Read Only
`Memory (EEPROM), 2.0 glossary
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`Universal Serial Bus Specification Revision 2.0
`
`endpoints (continued)
`explicit feedback endpoints, 9.6.5, 9.6.6
`getting endpoint status, 9.4.5
`high-bandwidth endpoints, 2.0 glossary, 5.7.4
`high-speed signaling attributes, 9.6.6
`Hub Controller endpoint organization, 11.12.1
`in interfaces, 9.2.3, 9.6.3, 9.6.5
`logical devices as collections of endpoints, 5.3
`message pipes and, 5.3.2.2
`non-endpoint zero requirements, 5.3.1.2
`number matching, 9.6.6
`overview, 5.3.1
`pipes and, 4.4, 5.3.2
`programmable data rates, 2.0 glossary
`reflected endpoint status, 10.5.2.2
`role in data transfers, 4.7
`samples, 2.0 glossary
`specifying in wlndex field, 9.3.4
`state machines, 8.5
`stream pipes and, 5.3.2.1
`synchronization frame, 9.4.11
`Transfer Types, Synchronization Types, and
`Usage Types, 9.6.6
`endpoint synchronization type, 5.12.4, 5.12.4.1
`Endpoint Type field (ET), 8.4.2.2
`endpoint type field (ET), 8.4.2.2
`endpoint zero
`Default Control Pipe and, 5.3.2
`in device characteristics, 4.8.1
`non-endpoint zero requirements, 5.3.1.2
`require