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`."o*n.o3@o.^.ru
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`DATE
`APR 02 20U
`
`PATENT NUMBER
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`,68&0,!28
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`EXAMINER3 C(**
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`APPLICATION NO.
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`CONT/PBIOR CLASS
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`ISSU ING CLASSIFICATION
`cRoss REFERENCE(S)
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`SUBCLASS (ONE SUBCLASS PER BLOCK)
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`-months
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`SP?*;'*&**
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`Date Reeeived
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`or
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`CONTENTS
`Date Received
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`or
`Date Mailed
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`ft ,",' '' "
`Q '/otoet- 44.
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`ISSUE SLIP STAPLE AREA (for additional cross references)
`
`POSTTION
`
`INITIALS
`
`ID NO.
`
`FEE DETERMINATION
`O.I.P.E. CLASSIFIER
`FORMALITY REVIEW
`RESPONSE FORMALITY REVIEW
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`
`INDEX OF CLAIMS
`Rejected
`Allowed
`(Through numeral)... Canceled
`Restricted
`
`L
`
`Claim
`
`Date
`
`Claim
`
`Date
`
`(!
`(,)
`
`101
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`60
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`70
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`71
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`72
`
`75
`76
`77
`78
`79
`80
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`81
`82
`83
`84
`85
`86
`
`87
`88
`89
`
`90
`
`91
`
`92
`93
`94
`95
`96
`97
`98
`99
`
`lf more than 150 claims or 10 actions
`staple additional sheet here
`
`(LEFT INSIDE)
`
`

`

`SEAR
`
`SEARCH NOTES
`(TNCLUDTNG SEARCH STRATEGY)
`
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`

`

`*,.
`
`ur.urep STATEs P,qr-ENr Ar.rp ThApEl,,rARK orflcn
`
`Page 1 of 1
`
`6&ili#EN;; ;6; Ei;iE
`UNttto Smres PATENT ANo TFADEI''IARK OFFICE
`W€HINGrcN, D,C.2O23I
`www,usPto.gov
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`CLASS
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`GROUP ART UNIT
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`ATTORNEY
`DOCKET NO.
`X-784 US
`
`ilillililllllllllllllllflllilllllllllffi lllllillllilllillllllll
`Bib Data Sheet
`
`SERIAL NUMBER
`09/655,1 68
`
`FILING DATE
`09/05/2000
`
`RULE
`
`\PPLICANTS
`AtulV. Ghia, San Jose, CA ;
`Suresh M. Menon, SunnYvale, CA;
`David P. Schulz, San Jose, CA;
`
`* coNTINUING DATA *************************
`/) c
`Pu-'-4-
`'84
`- FOREIGN AppLIcATloNS **********r--.-l::-,-
`Fro-)-(-
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`F REQUIRED, FOREIGN FILING LICENSE
`]RANTED.. 1012312000
`E r.Jgl
`:oreign Priority claimed
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`15 USC 1 19 (a-d) conditions
`net
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`,f
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`/ @r SHEETS
`
`DRAWING
`10
`
`TOTAL
`CLAIMS
`23
`
`NDEPENDENT
`CLAIMS
`3
`
`\DDRESS
`
`ldel M Young
`(ilinx lnc
`2100 Logic Drive
`ian Jose .CA 95124
`
`rITLE
`lircuit for producing low-voltage differential signals
`
`FILING FEE
`RECEIVED
`744
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`:EES: Authority has been given in Paper
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`_
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`itFF.toEffiII
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`Atul V. Ghia
`
`Circuit for Producing Low-Yoltage Differential Signals
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`

`

`x-784 uS
`
`C]RCUIT FOR PRODUCING LOW-VOLTAGE DIFFERENTIAL
`Atul V. Ghia
`Suresh M. Menon
`David P. Schultz
`
`PATENT
`
`SIGNALS
`
`FTELD OF THE INVENTION
`This invention relates generallY
`for providing high-speed, 1ow-voltage
`
`to methods and circuits
`differential signals.
`
`BACKGROT]ND
`The Telecommunications Industry Association (TIA)
`published a standard specifying t.he electrical characteristics
`of low-voltage differential signaling (LVDS) interface
`circuits thaL can be used to interchange binary signals ' LVDS
`employs 1ow-voltage differential signals to provide high-
`speed, low-power data communicat'ion' The use of differential
`signals allows for cancellation of common-mode noise, and thus
`enables data transmission with exceptional speed and noise
`immunity. For a detaited description of this LVDS standard,
`see ,,Electrical Characteristics of Low voltage Differential
`signaling (LVDS) Interface circuits, " TIA/ElA-644 (March
`Lg96), which is incorporated herein by reference'
`Figure 1 (prior art) illustrites an LVDS generator 100
`connected to an LVDS receiver l-l-0 via a transmission line l-l'5 '
`Generator l-00 converts a single-ended digital input signal
`D-IN on a tike-named input terminal into a pair of
`complementary LVDS output signals on differential output
`terminal_s Tx_A and Tx_B. A l-o0-ohm termination 10ad RL
`separates terminals TX-A and TX-B, and sets the output
`impedance of generator l-00 Lo the level specified in t'he
`above-referenced LVDS Standard'
`LVDS receiver 110 accepts the differential input. siqnals
`from terminals TX-A and. TX-B and Converts them to a single-
`ended output signal D-OUT. The LVDS standard specifies the
`
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`

`

`x-784 US
`
`PATENT
`
`1 properties of LVDS receiver l-l-0. The present application is
`2 directed to d.ifferential-signal generators: a comprehensive
`3 discussion of receiver 110 is not included in the present
`4 application.
`Figure 2 (prior art) schematically depicts LVDS generator
`5
`6 1-00 of Figure 1. Generator L00 includes a preamplifier 200
`7 connected to a driver stage 205. Preamplifier 200 receives
`the single-end.ed data signal D-IN and produces a pair of
`g
`9 complementary data signals D and D/ (signal names terminating
`10 in ,/, are active 1ow signals). Unless otherwise specified,
`11 each signal is referred to by the corresponding node
`1,2 d.esignation depicted in the figures. Thus, for example, the
`13 input terminal and input signal to generator l-00 are both
`L4 designated D-fN. In each instance, the interpretation of the
`15 node designation as either a signal or a physical element is
`L5 clear from the context.
`Driver stage 205 includes a PMOS load transistor 207 and
`1,j
`18 an NMOS load transistor 209, each of which produces a
`Lg relatively stable drive current in response to respect.ive bias
`20 voltages PBIAS and NBIAS. Driver stage 205 additionally
`21, includes four drive transistors 2!1, 2L3, 2L5, and 2L7 -
`If signal D-IN is a logic one (e.9., 3'3 volts),
`22
`23 preamplifier 200 produces a logic one on terminal D and a
`24 logic zero (e.g. , zero volLs) on terminal D/' The logic one
`25 on terminal D turns on transistors 2L1, and 2L7, causing
`26 current to flow down through transistors 207 and 2l-l-, up
`27 though termination load RL, and down through transistors 2L7
`2g and 209 to grround (see the series of arrows 219). The current
`29 through termination load RL develops a negative voltage
`30 between output terminals TX-A and TX-B'
`Conversely, if signal D-IN is a logic zero, preamplifier
`31
`32 200 produces a logic zero on terminal D and a logic one on
`33 terminal D/. The logic one on terminal D/ turns on
`34 transistors 2L3 and 215, causing current to flow down through
`
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`x-784 us
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`PATENT
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`li i
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`1
`transistor 207, transistor 21-5, termination load RL,
`2
`transLstor 2!3, and transistor 209 to ground (see the series
`3 of arrows 22L). The current through termination toad RL
`4 develops a positive voltage between output terminals TX_A and
`5 TX_B.
`Figure 3 (prior art) is a waveform diagram 300 depicting
`6
`7
`the signaling sense of the voltages appearing across
`8
`termination load RL of figures l- and 2. LVDS g'enerator 1-00
`9 produces a pair of differential output signals on terminals
`10 TX_A and TX_B. The LVDS Standard requires that the voltage
`11 between terminals TX-A and TX-B remain in the range of 250 mV
`1,2 to 450 mV, and that the voltage midway between the two
`13 differential voltages remains at approximately 1.2 volLs.
`ii 14 Terminal TX_A is negative with respect to terminal TX_B to
`;$ 15 represent a binary one and positive with respect Lo terminal B
`tj'l 16 to represent a binary zero.
`A programmable logic device (PLD) is a well-knoum tlpe of
`:i., 17
`lyi 18 rC that may be programmed by a user (e.q., a circuit designer)
`ii+i 19 to perform specified logic functions. Most PLDs contain some
`t)4>e of input/output block (IOB) that can be configured either
`i5 20
`to receive external signals or to drive signals off chip. One
`.;21
`\,fl 22 tlnpe of PLD, the f ield-programmable gate array (FPGA) ,
`typically includes an array of configurable logic blocks
`;:l ,,
`24 (Cf,ss) that are programmably interconnected to each other and
`25 to the progranunable IOBs. Configuration data loaded into
`26 internal configuration memory ce1ls on the FPGA define the
`27 operation of the FPGA by determining how the CLBs,
`28 interconnections, block RAM, and IOBs are configured.
`IOBs configured as output circuits ty'pica11y provide
`29
`30 single-ended logic signals to external d.evices. As with other
`31 t)pes of circuits, PLDs would benefit from the performance
`32 advantages offered by driving external signals using
`33 differential output signals. There is therefore a need for
`34 IOBs that can be configured to provide differential output
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`PATENT
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`signals. There is also a need for LVDS output circuits that
`can be tailored to optimize performance for different loads
`
`SUMMARY
`The present invention addresses the need for
`differential-signal output circuits that can be tailored for
`use with different 1oads. In accordance with one embodiment,
`one or more driver stages can be added, as necessary, to
`provide adequate power for driving a given 1oad. Driver stagres
`are added by prograrnming one or more proqranunable elements,
`such as memory cel1s, fuses, and antifuses.
`A differential driver in accordance with another
`embodiment includes a multi-stage delay element connected to a
`number of consecutive driver stages. The delay element
`produces two or more pairs of complementary input signals in
`response to each input-sigrnal transition, each successive
`signal pair being delayed by some amount relative to the
`previous signal pair. The pairs of complementary signals are
`conveyed to respective driver stages, so that each driver
`stage successively responds to the input-signal transition.
`The output terminals of the driver stages are connected to one
`another and to the output terminals of the differential
`driver. The differenLial driven thus responds to each input-
`signal transition with increasingly powerful amplification.
`The progressive amplification produces a corresponding
`progressive reduction in output resistance, which reduces the
`noise normally associated. with signal reflection.
`Extendable and multi-stage differential amplifiers in
`accordance with the invention can be adapted for use in PLDs.
`In one embodiment, adjacent pairs of fOBs are each provided
`with half of the circuitry required to produce LVDS signals.
`Adjacent pairs of IOBs can therefore be used either
`individually to provide single-ended input or output signals
`or can be combined to produce differential output signals.
`
`l-
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`a 3 4 5 5 7 8 9
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`10
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`11
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`1,2
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`13
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`1.4
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`15
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`1"6
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`1,7
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`18
`t9
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`ZU
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`21_
`')')
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`)1.
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`24
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`?q
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`26
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`28
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`29
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`30
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`31
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`32
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`33
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`34
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`ri ii
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`x-784 us
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`PATENT
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`This summary does not limit
`the invention,
`instead defined by the appended claims.
`
`BRIEF DESCRIPTION OF THE FIGURES
`Figure 1 (prior art) illustraLes an LVDS generator 100
`connected. t.o an LVDS recei-ver 110 via a transmission line l-1-5.
`Figure 2 (prior art) schematically depicts LVDS generator
`100 of Figure 1-.
`Figure 3 (prior art) is a waveform diagram 300 depicting
`the signaling sense of t.he voltages appearing across
`termination load RL of rigures 1 and 2.
`Figure 4 depicts an extensible differential amplifier 400
`in accordance with an embodiment of the invention.
`Figure 5A is a schematic diagram of predriver 405 of
`Figure 4.
`Figure 5B is a schematic diagram of driver 415 of Figure
`
`4.
`
`Figure 5C is a schematic diagram of extended driver 410
`of Figure 4.
`Figure 6 depicts a multi-stage driver 600 in accordance
`with another embodiment of the invention.
`Figure 7A schematically depicts a predriver 700 in which
`a predriver is connected to delay circuit 605 of Fiqure 6 to
`develop three complementary signal pairs.
`Fiqure 78 schematically depicts differential-amplifier
`sequences 610 and 615 and termination load 620, all of Figure
`6.
`
`Figures 8A and 8B schematically depict a programmable
`bias-voltage generator 800 in accordance with an embodiment of
`the invention.
`
`DETAILED DESCRIPT]ON
`Figure 4 depicts
`in accordance with an
`
`an extensible differential amplifier 400
`embodiment of the invention. Amplifier
`
`1 2 3 4 5 6 7 8 9
`
`10
`
`11
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`1.2
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`13
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`1.4
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`15
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`i irl
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`1.6
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`L7
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`IU
`
`19
`
`20
`
`2L
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`22
`
`23
`
`24
`1tr
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`26
`)'7
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`28
`,o
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`30
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`3l-
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`32
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`33
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`34
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`x-784 uS
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`l- 4OO includes a predriver 405 connected to a pair of driver
`2 stages 410 and 41-5. The corrbination of predriver 405 and
`3 driver 415 operates as described above in connection with
`4 Figures 2 and.3 to convert the single-ended input. on terminal
`5 D-fN into differential output signals on lines TX-A and TX-!.
`In accordance wiLh the invention, driver 410 can be activated
`6
`7 as needed to provide additional drive power. rn one
`g embodiment, drivers 410 and 4l-5 reside within a pair of
`9 adjacent programmable IOBs (collectively labeled 41-7) and
`10 lines TX-A and TX-g connect to the respective input/output
`j.1 (I/O) pad.s of the pair. This aspect of the invention is
`12 detailed below.
`The program state of a configuraLion bLt 420 determines
`j_3
`14 whether amplifier 400 is enabled, and the program state of a
`15 second configuration bil- 425 determines whether the driver
`L6 stage of amplifier 400 is extended to include driver 410. An
`L7 exemplary configuration bit is described below in connection
`18 with Figure BA.
`If bit 420 is programmed to provide a logic one on
`1,g
`20 ,,enable differential signaling" line EN-DS, then pred.river 405
`2L and driver 4l-5 function in a manner similar to that described
`22 above in connection with Figure 2. If desired, the drive
`23 circuitry can be extended to include driver 410 by programming
`24 biL 425 to provide a logic one on "extended differential
`25 signaling" line X-DS. The signals on lines X-DS and EN-DS are
`26 logicatly combined using an AND gat.e 430 to produce an "enable
`21 termination load" signal EN-T to drivet 415. This signal and
`2g its purpose are described below in connection with Figure 58.
`Figure 5A is a schematic diagram of an embodiment of
`29
`30 predriver 405 of Figure 4. Predriver 405 includes a pair of
`3l_ conventional tri-state drivers 500 and 502. A conventional
`32 inverter 504 provides the complement of signal EN-DS.
`amplifier 400 is inactive when signals EN-DS and EN-DS/
`33
`34 are low and high, respectively. These logic levels cause
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`x-784 us
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`PATENT
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`tristate drivers 500 and 502 to disconnect input terminal D_IN
`1
`from respective tristate output terminals TL and T2. Signal
`2
`3 EN-DS and its complementary signal EN-DS/ also connecL
`terminals T1 and T2 to respective supply voltages VCCO and
`4
`5 grround by turning on a pair of transistors 506 and 508. Thus,
`terminals Ti- and T2 do noL change in response to changes on
`6
`input terminal D_IN when differential sigrnaling is disabled.
`7
`In the case where amplifier 400 is implemented using IOBs in a
`8
`9 programmable logic device, amplifier 400 may be disabled to
`10 a]1ow the IOBs to perform some other input or output function.
`Amptifier 400 is active when signals EN-DS and EN-DS/ are
`L1,
`L2 high and low, respectively. These logic levels cause tristate
`13 drivers 500 and 502 to connect input terminal D-IN to
`1,4 respective Lristate output terminals T1 and T2. Signal EN-DS
`15 and its complementary signal EN-DS/ also disconnect terminals
`L6 T1 and T2 from respective supply voltages VCCO and ground by
`L7 turning off transistors 506 and 508. Thus, terminals T1 and T2
`18 change in response to signal D-IN when differenLial signaling
`is enabled.
`t9
`tristate output terminals T1 and T2 connect to the
`20
`2L respective inpuL terminals of an inverting predriver 510 and a
`22 non-inverting predriver 51,2. Predriver 510 includes a pair of
`23 conventional- inverters 514 and 516. Inverter 514 produces a
`24 signal D, an inverted and amplified version of the signal on
`25 line T1; inverter 516 provides a similar signal to a test pin
`26 5LB. predriver 5L2 includes t.hree conventional inverters 520,
`21 522, and 524. Predriver 5L2 produces a signal D/, the
`28 complement of signat D. Inverter 524 provides a similar signal
`29 to a test Pin 526.
`Each inverter within predrivers 5l-0 and 512 is a cMos
`30
`31 inverLer in which the ratios of the PMOS and NMOS transistors
`32 are as specified. These particular ratios were selected so
`33 that signals D and D/ transition simultaneously, or very
`34 nearly so. Different ratios may be appropriate, depending upon
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`x-784 uS
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`PATENT
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`l-
`the process used to produce amplifier 400. Adjusting layout
`2 and process parameters to produce synchronized complementary
`3 signals is within the skiI1 of Lhose in the art.
`As d.iscussed above in connection with Fiqure 4, amplifier
`4
`5 400 can be extended to include additional drive circuitry,
`6 which may be needed to drive some loads while remaining in
`7 compliance with the LVDS Standard. Returning to Figure 5A, a
`B pair of NOR gates 528 and 530 facilitates this extension by
`9 producing a pair of complimentary extended-data signals DX and
`10 DXl when signal X-DS/ is a logic zero, indicating the extended
`11 driver is enabled. Extend.ed-data signal DX is substantially
`12 the same as signal D, and extended data signal DX/ is
`13 substantially the same as signal D/. Signals DX and DXl are
`L4 conveyed to extended driver 410, the operation of which is
`15 detailed below in connection with Figure 5C.
`Figure 58 is a schematic d.iagram of driver 415 of Figure
`1,6
`t] 4. Driver 415 is similar to driver sLage 205 of Figure 2,
`18 like-numbered elements being the same. Unlike driver 205,
`19 however, driver 415 includes a programmable termination load
`20 540. Further, load transistors 207 and 209 of Figure 2 are
`2L replaced with pairs of para11e1 transistors, so that
`22 transistors 21-L and, 215 connect to VCCO via respective PMOS
`23 transistor 532 and 533, instead of via a single transistor
`24 207, and transistors 2L3 and. 2L7 connect to ground via
`25 respective NMOS transistors 534 and. 535, instead of via a
`26 single transistor 209.
`Employing pairs of load t,ransistors allows driver 41-5 to
`27
`2g be separated into two similar parts 536 and 538, each
`29 associated with a respective one of terminals TX-A and TX-B.
`30 Such a configuration is convenient, for example, when driver
`31 4L5 is implemented on a PLD in which terminals TX-A and TX-B
`32 connect to neighboring I/O pins. Each part 536 and 538 can be
`33 implemented as a portion of the IOB (not shown) associated
`34 with the respective one of terminals Tx-A and Tx-B'
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`x-784 uS
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`PATENT
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`1 Termination load 540 can be part of either IOB, neither IOB,
`2 or can be split between the two. In one embod,iment, transistor
`3 542 is included in the rOB that includes part 536, and
`transistor 543 is included in the fOB that. includes part 538.
`4
`programmable termination load 540 includes a pair of
`5
`transistors 542 and 543, the gates of which connect to
`6
`terminal EN-T. As shown in Figrure 4, the signal EN-T is
`7
`8 controll-ed through AND gate 430 by configuration bits 420 and
`g
`425 ' Termination load 540 is acLive (conducting) only when
`10 differential signaling is enabled in the non-extended mode.
`1,1" This condition is specified when configuration bLt 420 is set
`1"2 to a logic one and configuration bit 425 is set to a logic
`13 zero.
`Driver 415 includes a number of terminals that provide
`L4
`15 appropriate bias voltages. Terminals PBIAS and NBIAS provide
`1-6 respective bias levels esLablish the gain driver 415, and
`L7 common terminals PCOM and NCOM conventionally establish the
`l-8 higrh and low volt.age levels on output terminals TX-A and TX-B'
`B Driver 415 shares the bias and common terminafs with extended
`20 driver 410 (See figure 5C).
`The bias levels PBIAS and. NBIAS are important in defining
`2t
`22 LVDS signal guality. In one embodiment, NMOS transistors 534
`23 and 535 are biased to operate in saturation to sink a
`24 relatively stable current, whereas PMOS transistors 532 and
`25 533 are biased to operate in a linear region. Operating
`26 transistors 532 and 533 in a linear region reduces t3l3@
`the output resistances of those devices, and the
`27 €giiE
`28 reduced resistance tends to dissipate signal reflections
`29 returning to terminals TX-A and TX-B. Reduced reflections
`30 translate into reduced noise, and reduced noise allows signals
`3l- to be conveyed at higher dat.a rates. Circuits for developing
`32 appropriate bias l-evels for the circuits of Fiqures 5A-7B are
`33 discussed below in connection with Figures 8A and 8B.
`Figure 5C is a schematic d.iagram of one embodiment of
`34
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`x-784 us
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`PATENT
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`1 extended driver 410 of Figure 4. Extended driver 4l-0 includes
`2 a pair of driver stages 544 and 546 and a programmable
`3
`termination load 548. Driver stages 544 and 546 can be
`4
`included, for example, in respective adjacent rOBs on a pLD.
`5 Termination load 548 can be part of either IOB, neither IOB,
`6 or can be split between the two. The various terminals of
`7 Figure 5C are connected to like-named terminals of Figures 5A
`8 and 5B.
`9
`Driver stage 544 includes a PMOS load transistor 550, a
`10 pair of NMOS differential-driver transistors 552 and 554
`11 having their qates connected to respective extended-driver
`1,2 input signals ox and DXl, a diode-connecLed PMOS transistor
`l-3 556, and a PMOS transistor 558 connected as a capacitor
`i:: 14 between terminal VCCO and terminal PCOM. Transistors 550, 552,
`:$ rs and 554 combined amplify the extended-driver signals ox and
`it'i
`lijl 15 Dx/ to produce an amplified output signal on output terminal
`,,.i 1z Tx-A. rn one embodiment, t,ransistor 556 is diode-connected
`li1i 18 between terminals PCOM and VCCO to establish the appropriate
`level for l-ine PCOM, which is conimon to both drivers 410 and
`,l' t,
`i3 20 41,5. Finally,
`transistor 558 can be sized or eliminated as
`'.i zt desired to minimize noise on line PCoM.
`Driver stage 546 is identical to driver stage 544, except
`ii\i ZZ
`that lines DX and DX/ are connected to Lhe opposite
`;$ ,,
`24 differential driver transistors. Consequently, the signals on
`25 outpuL terminals Tx-A and TX-B are complemenLary. Driver
`25 stages 544 and 546 thus supplement the drive strength provided
`27 by driver stage 415.
`As shown in Figure 4, the extend-differential-signaling
`28
`29 signal X_DS is a logic one when CBIT 425 Ls programmed.
`30 However, programming CBIT 425 causes AND gate 430 to output a
`31 logic zero, disabling termination load 532 of Figure 58. Thus,
`32 programming CBIT 425 substitutes termination load 548 for
`33 termination load 532, thereby increasing the termination load
`34 resistance to an aBpropriate Ieve1. In one embodiment, the
`
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`x-784 US
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`PATENT
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`1 resistance of termination load 532 is selected so that the
`2 resulting output signal conforms to the LVDS Standard.
`Figure 6 depicLs a multi-stage driver 600 in accordance
`3
`4 with another embodiment of the invention. Driver 600 includes
`5 a mutti-st.age delay circuit 605, a first sequence of
`6 differential amplifiers 610, a second sequence of differential
`7 amplifiers 6L5, and a termination load 620. For illustrative
`g purposes, the amplifiers of sequences 610 and 6l-5 are referred
`to as "high-side" and "low-side" amplifiers, respectively. In
`9
`l-0 dif ferent embod.iments, each amplifier sequence 610 and 6l-5 can
`i,L be implemented as a portion of the IOB (not shown) associated
`i,2 with the respective one of t.erminals TX-A and TX-B.
`13 Termination load 620 can be part of either IOB, neither IOB,
`1,4 or can be sPliL between the two.
`Delay circuit 605 receives a pair of complementary
`15
`1,6 sigrnals D and D/ on a like-named pair of input terminals. A
`Lt sequence of delay elements conventional buffers 625 in the
`18 depicted example -- provides a first pair of delayed
`1,g complementary signals D1 and D1l and a second pair of delayed
`20 complementary signals D2 and D2/.
`Sequence 6L0 includes three differential amplifiers 630,
`2L
`22 63L, and.632, the output. terminals of which connect to one
`23 another and to output terminal TX-A. The differential input
`24 t.erminals of each of these high-side amplifiers connect to
`25 respective complemenLary terminals from delay circuit 605 '
`26 That is, the non-inverting (+) and inverting (-) terminals of
`27 differential amplifier 630 connect to respective input
`2g terminals D and D/, the non-inverting and inverting terminals
`29 of differential amplifier 631 connect to respective input'
`30 terminals D1 and' DL/, and the non-inverting and inverting
`31 terminals of different