Universal Serial Bus Specification Revision 2.0
`
`Figure 7-6 shows the full-speed driver signal waveforms.
`
`One Bit
`
`Driver
`Signal Pins
`
`One-Way
`Trip Cable
`Delay
`
`VIH (min)--,-----t-----tt---------t--------tl--------',c-------------.-.-----
`Signal pins pass
`input spec levels
`after one cable
`delay
`
`Receiver
`Signal Pins
`
`VIL (max)
`Vss --=::::::::j:::::::::~======+==--=====================:..._.======-
`Figure 7-6. Full-speed Signal Waveforms
`
`7.1.1.2 Low-speed (1.5 Mb/s) Driver Characteristics
`A low-speed device must have a captive cable with the Series A connector on the plug end. The combination of
`the cable and the device must have a single-ended capacitance of no less than 200 pF and no more than 450 pF
`on the D+ or D- lines.
`
`The propagation delay (TLSCBL) of a low-speed cable must be less than 18 ns. This is to ensure that the
`reflection occurs during the first half of the signal rise/fall, which allows the cable to be approximated by a
`lumped capacitance.
`
`Figure 7-7 shows the low-speed driver signal waveforms.
`
`One Bit
`
`VIH (min)-+--+----,c--+----+---+-l----------'rt(cid:173)
`
`Driver
`Signal Pins
`
`Signal pins
`pass output
`spec levels
`with minimal
`reflections and
`ringing
`
`Figure 7-7. Low-speed Driver Signal Waveforms
`
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`7.1.1.3 High-speed (480 Mb/s) Driver Characteristics
`A high-speed USB connection is made through a shielded, twisted pair cable with a differential characteristic
`impedance (Zo) of90 Q ±15%, a common mode impedance (ZcM) of30 Q ±30%, and a maximum one-way
`delay of 26 ns (TFSCBL). The D+ and D- circuit board traces which run between a transceiver and its associated
`connector should also have a nominal differential impedance of 90 Q, and together they may add an additional
`4 ns of delay between the transceivers. (See Section 7.1.6 for details on impedance specifications of boards and
`transceivers.) The differential output impedance of a high-speed capable driver is required to be 90 Q ±10%.
`When either the D+ or D- lines are driven high, VHSOH (the high-speed mode high-level output voltage driven on
`a data line with a precision 45 Q load to GND) must be 400 mV ±10%. On a line which is not driven, either
`because the transceiver is not transmitting or because the opposite line is being driven high, VHSOL (the high(cid:173)
`speed mode low-level output voltage driven on a data line with a 45 Q load to GND) must be O V ± 10 mV.
`
`Note: Unless indicated otherwise, all voltage measurements are to be made with respect to the local circuit
`ground.
`
`Note: This specification requires that a high-speed capable transceiver operating in full-speed or low-speed
`mode must have a driver impedance (ZHSDRv) of 45 Q ±10%. It is recommended that the driver impedances be
`matched to within 5 Q within a transceiver. For upstream facing transceivers which do not support high-speed
`mode, the driver output impedance (ZDRv) must fall within the range of28 Q to 44 Q.
`
`On downstream facing ports, RPD resistors (15 ill ±5%) must be connected from D+ and D- to ground.
`
`When a high-speed capable transceiver transitions to high-speed mode, the high-speed idle state is achieved by
`driving SEO with the low-/full-speed drivers at each end of the link (so as to provide the required terminations),
`and by disconnecting the D+ pull-up resistor in the upstream facing transceiver.
`
`In the preferred embodiment, a transceiver activates its high-speed current driver only when transmitting high(cid:173)
`speed signals. This is a potential design challenge, however, since the signal amplitude and timing specifications
`must be met even on the first symbol within a packet. As a less efficient alternative, a transceiver may cause its
`high-speed current source to be continually active while in high-speed mode. When the transceiver is not
`transmitting, the current may be directed into the device ground rather than through the current steering switch
`which is used for data signaling. In the example circuit, steering the current to ground is accomplished by
`setting HS_Drive_Enable low.
`
`In CMOS implementations, the driver impedance will typically be realized by the combination of the driver's
`intrinsic output impedance and Rs. To optimally control ZHSDRV and to minimize parasitics, it is preferred the
`driver impedance be minimized (under 5 Q) and the balance of the 45 Q should be contributed by the Rs
`component.
`
`When a transceiver operating in high-speed mode transmits, the transmit current is directed into either the D+ or
`D- data line. A J is asserted by directing the current to the D+ line, a K by directing it to the D- line.
`
`When each of the data lines is terminated with a 45 Q resistor to the device ground, the effective load resistance
`on each side is 22.5 Q. Therefore, the line into which the drive current is being directed rises to 17.78 ma*
`22.5 Q or 400 mV (nominal). The other line remains at the device ground voltage. When the current is directed
`to the opposite line, these voltages are reversed.
`
`7.1.2 Data Signal Rise and Fall, Eye Patterns
`The following sections specify the data signal rise and fall times for full-speed and low-speed signaling, and the
`rise time and eye patterns for high-speed signaling.
`
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`7.1.2.1 Low-speed and Full-speed Data Signal Rise and Fall
`For low-speed and full-speed, the output rise time and fall times are measured between 10% and 90% of the
`signal (Figure 7-8). Rise and fall time requirements apply to differential transitions as well as to transitions
`between differential and single-ended signaling.
`
`The rise and fall times for full-speed buffers are measured with the load shown in Figure 7-9. The rise and fall
`times must be between 4 ns and 20 ns and matched to within ±10% to minimize RFI emissions and signal skew.
`The transitions must be monotonic.
`
`The rise and fall times for low-speed buffers are measured with the load shown in Figure 7-10. The capacitive
`load shown in Figure 7-10 is representative of the worst-case load allowed by the specification. A downstream
`facing transceiver is allowed 150 pF of input/output capacitance (CIND). A low-speed device (including cable)
`may have a capacitance of as little as 200 pF and as much as 450 pF. This gives a range of 200 pF to 600 pF as
`the capacitive load that a downstream facing low-speed buffer might encounter. Upstream facing buffers on
`low-speed devices must be designed to drive the capacitance of the attached cable plus an additional 150 pF. If
`a low-speed buffer is designed for an application where the load capacitance is known to fall in a different range,
`the test load can be adjusted to match the actual application. Low-speed buffers on hosts and hubs that are
`attached to USB receptacles must be designed for the 200 pF to 600 pF range. The tise and fall time must be
`between 75 ns and 300 ns for any balanced, capacitive test load. In all cases, the edges must be matched to
`within ±20% to minimize RFI emissions and signal skew. The transitions must be monotonic.
`
`For both full-speed and low-speed signaling, the crossover voltage (VCRS) must be between 1.3 V and 2.0 V.
`
`For low-speed and full-speed, this specification does not require matching signal swing matching to any greater
`degree than described above. However, when signaling, it is preferred that the average voltage on the D+ and
`D- lines should be constant. This means that the amplitude of the signal swing on both D+ and D- should be the
`same; the low and high going transition should begin at the same time and change at the same rate; and the
`crossover voltage should be the same when switching to a J or K. Deviations from signal matching will result in
`common-mode noise that will radiate and affect the ability of devices and systems to pass tests that are
`mandated by government agencies.
`
`Rise Time
`
`Fall Time
`
`VCRS
`
`Differential
`Data Lines
`
`Figure 7-8. Data Signal Rise and Fall Time
`
`Full-speed
`Buffer
`R
`
`I
`
`R
`
`I
`: J_
`-
`
`I
`
`"------------ J_
`
`CL= 50pF
`
`L
`
`L
`
`Figure 7-9. Full-speed Load
`
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`
`Low-speed
`Buffer
`
`Low-speed
`Buffer
`
`T~
`
`T~15Kn
`
`:
`TxD-'
`
`Rs
`
`: -
`, ·
`\ . -<> - - r - -~
`
`,
`TxD-'
`
`Rs
`
`-
`
`·
`
`1
`,
`
`_
`-
`
`15KQ
`
`CL= 200pF to 600pF
`
`CL= 50pF to 150pF
`
`Low-speed downstream port load
`
`Low-speed upstream port load
`
`Figure 7-10. Low-speed Port Loads
`
`Note: The CL for low-speed port load only represents the range of loading that might be added when the low(cid:173)
`speed device is attached to a hub. The low-speed buffer must be designed to drive the load of its attached cable
`plus CL. A low-speed buffer design that can drive the downstream test load would be capable of driving any
`legitimate upstream load.
`
`7.1.2.2 High-speed Signaling Eye Patterns and Rise and Fall Time
`The following specifications apply to high-speed mode signaling. All bits, including the first and last bit of a
`packet, must meet the following eye pattern requirements for timing and amplitude.
`
`TP1
`
`TP2
`
`TP3
`
`TP4
`
`Traces
`
`USB Cable
`
`Transceiver
`
`A
`Connector
`
`B
`Connector
`
`Transceiver
`
`Hub Circuit Board
`
`Device Circuit Board
`
`Figure 7-11. Measurement Planes
`
`Figure 7-11 defines four test planes which will be referenced in this section. TP 1 and TP4 are the points where
`the transceiver IC pins are soldered to the hub and device circuit boards, respectively. TP2 is at the mated pins
`of the A connector, and TP3 is at the mated pins of the B connector ( or, in the case of a captive cable, where the
`cable is attached to the circuit board). The following differential eye pattern templates specify transmit
`waveform and receive sensitivity requirements at various points and under various conditions.
`
`When testing high-speed transmitters and receivers, measurements are made with the Transmitter/Receiver Test
`Fixture shown in Figure 7-12. In either case, the fixture is attached to the USB connector closest to the
`transceiver being tested.
`
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`
`Transmitter Test Attenuation: Voltage at Scope Inputs= 0.760 * Voltage at Transmitter Outputs
`Receiver Test Attenuation: Voltage at Receiver Inputs= 0.684 * Voltage at Data Generator Outputs
`
`Test Supply Voltage
`
`USB
`Connector
`Nearest
`Device
`Under Test
`
`Vbus
`D+
`D-
`Gnd
`
`+
`To 50 Ohm Inputs of a
`High Speed Differential
`Oscilloscope, or 50 Ohm
`Outputs of a High Speed
`Differential Data
`Generator
`
`50 Ohm
`Coax
`
`50 Ohm
`Coax
`
`143
`Ohms
`
`143
`Ohms
`
`Figure 7-12. Transmitter/Receiver Test Fixture
`
`Note: When testing the upstream facing port of a device, VBUS must be provided from the time the device is
`placed in the appropriate test mode until the test is completed. This requirement will likely necessitate
`additional switching functionality in the test fixture (for example, to switch the D+ and D- lines between the host
`controller and the test instrument). Such additions must have minimal impact on the high frequency
`measurement results.
`
`Transmit eye patterns specify the minimum and maximum limits, as well as limits on timing jitter, within which
`a c1i;ver must drive signals at each of the specified test planes. Receive eye patterns specify the minimum and
`maximum limits, as well as limits on timing jitter, within which a receiver must recover data.
`
`Conformance to Templates l , 2, 3, and 4 is required for USB 2.0 hubs and devices:
`
`Template 1: Transmit waveform requirements for hub measured at TP2, and for device (without a captive
`cable) measured at TP3
`
`Template 2: Transmit waveform requirements for device (with a captive cable) measured at TP2
`
`Template 3: Receiver sensitivity requirements for device ( with a captive cable) when signal is applied at TP2
`
`Template 4: Receiver sensitivity requirements for device (without a captive cable) when signal is applied at
`TP3, and for hub when signal is applied at TP2
`
`Templates 5 and 6 are recommended guidelines for designers:
`
`Template 5: Transmit waveform requirements for hub transceiver measured at TPl, and for device transceiver
`measured at TP4
`
`Template 6: Receiver sensitivity requirements for device transceiver when signal is applied at TP4, and for hub
`transceiver at when signal is applied at TPI
`
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`
`Template 1
`
`Figure 7-13 shows the transmit waveform requirements for a hub measured at TP2, and for a device (without a
`captive cable) measured at TP3.
`
`Leve I 1 -----------
`
`-·--····· -·-····~···-~~~~~·'··-·-
`i
`i
`
`1
`
`1
`
`1
`'
`
`I
`
`I
`I
`
`1
`
`I
`
`I
`I
`
`!
`
`I
`
`i
`
`i
`
`I
`
`I
`
`I
`I
`
`i
`
`I
`
`i
`I
`
`,
`
`I
`
`i
`I
`
`'
`
`I
`I
`
`I
`
`I
`
`-------------------------------------------------------------------------------------- --------------
`I
`I
`! ·-··l Point t ---·1----·· ····-----·-
`I
`I
`I
`+----+--- 1-l-----r------1--1 ---1------r---- ---------
`+-- t·-----1-+-----t------~-+----+ ---+--- ---------
`·-.J __ J_ .. _.J ..... J __ J .. Por ··-··t··-·- -·-·-·-·-···
`
`··-··--·-·· ·--···i·-···Per
`I
`I
`I
`I
`I
`I
`I
`------1---------1 ----- -I----- 1--------1-------- 1-----I ---- 1---------1----- ------------
`I
`I
`I
`I
`1
`!
`!
`!
`I
`I
`I
`I
`I
`I
`I
`I
`··-··-········· ·-··-··+·······-+·······+·-··
`'
`' ··-·+········-+-·······+··-··-·· ·········-··-···
`I Point~
`I
`~oint s j
`I
`I
`
`1
`
`j
`
`I
`
`I
`
`+ 400mV
`Differential
`
`OVolts
`Differential
`
`-400mV
`Differential
`
`Leve I 2 -----------
`
`-------------------------------------------------------------------------------------- --------------
`
`0%
`
`Unit Interval
`
`100%
`
`Voltage Level (D+ - D-)
`
`Time (% of Unit Interval)
`
`Level 1
`
`Level2
`
`Point 1
`
`Point 2
`
`525 mV in UI following a transition,
`475 mV in all others
`
`-525 mV in UI following a transition,
`-475 in all others
`
`ov
`ov
`
`Point 3
`
`300 mV
`
`Point 4
`
`300 mV
`
`Point 5
`
`-300 mV
`
`Point 6
`
`-300 mV
`
`N/A
`
`N/A
`
`7.5% UI
`
`92.5% UI
`
`37.5% UI
`
`62.5% UI
`
`37.5% UI
`
`62.5% UI
`
`Figure 7-13. Template 1
`
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`
`Template 2
`
`Figure 7-14 shows transmit waveform requirements for a device ( with a captive cable) measured at TP2.
`
`Level 1 -------- ------------------------------------------------------------------------- -------------
`
`Level 2 --------- ------------------------------------------------------------------------------ --------------
`
`0%
`
`Unit Interval
`
`100%
`
`Voltage Level (D+ - D-)
`
`Time (% of Unit Interval)
`
`Level 1
`
`Level2
`
`Point 1
`
`Point 2
`
`525 mV in UI following a transition,
`475 mV in all others
`
`-525 mV in UI following a transition,
`-475 in all others
`
`ov
`ov
`
`Point 3
`
`175 mV
`
`Point 4
`
`175 mV
`
`Point 5
`
`-175 mV
`
`Point 6
`
`-175 mV
`
`N/A
`
`N/A
`
`12.5% UI
`
`87.5% UI
`
`35% UI
`
`65% UI
`
`35% UI
`
`65% UI
`
`Figure 7-14. Template 2
`
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`

`Universal Serial Bus Specification Revision 2.0
`
`Template 3
`
`Figure 7-15 shows receiver sensitivity requirements for a device (with a captive cable) when a signal is applied
`at TP2.
`
`Level 1 - - - - - - - - - - - - - - - - - - - -
`
`+ 400mV
`Differential
`
`0 Volts
`Differential
`
`-400mV
`Differential
`
`Level 2
`
`0%
`
`Unit Interval
`
`100%
`
`Voltage Level (D+ - D-)
`
`Time (% of Unit Interval)
`
`Level 1
`
`575mV
`
`Level2
`
`-575 mV
`
`Point 1
`
`Point 2
`
`ov
`
`ov
`
`Point 3
`
`275 mV
`
`Point 4
`
`275 mV
`
`Point 5
`
`-275 mV
`
`Point 6
`
`-275 mV
`
`N/A
`
`N/A
`
`10% UI
`
`90% UI
`
`40% UI
`
`60% UI
`
`40% UI
`
`60% UI
`
`Figure 7-15. Template 3
`
`Note: This eye is intended to specify differential data receiver sensitivity requirements. Levels 1 and 2 are
`outside the Disconnect Threshold values, but disconnection is detected at the source ( after a minimum of 32 bit
`times without any transitions), not at the target receiver.
`
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`

`Universal Serial Bus Specification Revision 2.0
`
`Template 4
`
`Figure 7-16 shows receiver sensitivity requirements for a device ( without a captive cable) when signal is applied
`at TP3, and for a hub when a signal is applied at TP2.
`
`Level 1
`
`Level 2
`
`+ 400mV
`Differential
`
`OVolts
`Differential
`
`-400mV
`Differential
`
`0%
`
`Unit Interval
`
`100%
`
`Voltage Level (D+ - D-)
`
`Time (% of Unit Interval)
`
`Level 1
`
`575mV
`
`Level2
`
`-575 mV
`
`Point 1
`
`Point 2
`
`ov
`
`ov
`
`Point 3
`
`150 mV
`
`Point 4
`
`150 mV
`
`Point 5
`
`-150 mV
`
`Point 6
`
`-150 mV
`
`N/A
`
`N/A
`
`15% UI
`
`85% UI
`
`35% UI
`
`65% UI
`
`35% UI
`
`65% UI
`
`Figure 7-16. Template 4
`
`Note: This eye is intended to specify differential data receiver sensitivity requirements. Levels 1 and 2 are
`outside the Disconnect Threshold values, but disconnection is detected at the source ( after a minimum of 32 bit
`times without any transitions), not at the target receiver.
`
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`
`Template 5
`
`Figure 7-17 shows transmit waveform requirements for a hub transceiver measured at TPl and for a device
`transceiver measured at TP4.
`
`Level 1
`
`Level 2
`
`+ 400mV
`Differential
`
`0 Volts
`Differential
`
`-400mV
`Differential
`
`0%
`
`Unit Interval
`
`100%
`
`Voltage Level (D+ - D-)
`
`Time (% of Unit Interval)
`
`Level 1
`
`Level2
`
`Point 1
`
`Point 2
`
`525 mV in UI following a transition,
`475 mV in all others
`
`-525 mV in UI following a transition,
`-475 in all others
`
`ov
`
`ov
`
`Point 3
`
`300 mV
`
`Point 4
`
`300 mV
`
`Point 5
`
`-300 mV
`
`Point 6
`
`-300 mV
`
`N/A
`
`N/A
`
`5% UI
`
`95% UI
`
`35% UI
`
`65% UI
`
`35% UI
`
`65% UI
`
`Figure 7-17. Template 5
`
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`
`Template 6
`
`Figure 7-18 shows receiver sensitivity requirements for a device transceiver when a signal is applied at TP4 and
`for a hub transceiver when a signal is applied at TPl.
`
`Level 1
`
`Level 2
`
`+ 400mV
`Differential
`
`0 Volts
`Differential
`
`-400mV
`Differential
`
`0%
`
`Unit Interval
`
`100%
`
`Voltage Level (D+ - D-)
`
`Time (% of Unit Interval)
`
`Level 1
`
`575mV
`
`Level2
`
`-575 mV
`
`Point 1
`
`Point 2
`
`ov
`
`ov
`
`Point 3
`
`150 mV
`
`Point 4
`
`150 mV
`
`Point 5
`
`-150 mV
`
`Point 6
`
`-150 mV
`
`N/A
`
`N/A
`
`20% UI
`
`80% UI
`
`40% UI
`
`60% UI
`
`40% UI
`
`60% UI
`
`Figure 7-18. Template 6
`
`Note: This eye is intended to specify differential data receiver sensitivity requirements. Levels 1 and 2 are
`outside the Disconnect Threshold values, but disconnection is detected at the source ( after a minimum of 32 bit
`times without any transitions), not at the target receiver.
`
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`
`High-speed Signaling Rise and Fall Times
`
`The transition time of a high-speed driver must not be less than the specified minimum allowable differential
`rise and fall time (THSR and THSF). Transition times are measured when driving a reference load of 45 Q to
`ground on D+ and D-. Figure 7-12 shows a recommended "Transmitter Test Fixture" for performing these
`measurements.
`
`For a hub, or for a device with detachable cable, the 10% to 90% high-speed differential rise and fall times must
`be 500 ps or longer when measured at the A or B receptacles (respectively).
`
`For a device with a captive cable assembly, it is a recommended design guideline that the 10% to 90% high(cid:173)
`speed differential rise and fall times must be 500 ps or longer when measured at the point where the cable is
`attached to the device circuit board.
`
`It is required that high-speed data transitions be monotonic over the minimum vertical openings specified in the
`preceding eye pattern templates.
`
`7.1.2.3 Driver Usage
`The upstream facing ports of functions must use one and only one of the following three driver configurations:
`
`1. Low-speed - Low-speed drivers only
`
`2. Full-speed - Full-speed drivers only
`
`3. Full-/high-speed - Combination full-speed and high-speed drivers
`
`Upstream facing USB 2.0 hub ports must use full-/high-speed drivers. Such ports must be capable of
`transmitting data at low-speed and full-speed rates with full-speed signaling, and at the high-speed rate using
`high-speed signaling. Downstream facing ports (including the host) must support low-speed, full-speed, and
`high-speed signaling, and must be able to transmit data at each of the three associated data rates.
`
`In this section, there is reference to a situation in which high-speed operation is "disallowed." This topic is
`discussed in depth in Chapter 11 of this specification. In brief, a high-speed capable hub's downstream facing
`ports are "high-speed disallowed" if the hub is unable to establish a high-speed connection on its upstream
`facing port. For example, this would be the case for the downstream facing ports of a high-speed capable hub
`when the hub is connected to a USB 1.1 host controller.
`
`When a full-/high-speed device is attached to a pre-USB 2.0 hub, or to a hub p011 which is high-speed
`disallowed, it is required to behave as a full-speed only device. When a full-/high-speed device is attached to a
`USB 2.0 hub which is not high-speed disallowed, it mL1st operate with high-speed signaling and data rate.
`
`7 .1.3 Cable Skew
`The maximum skew introduced by the cable between the differential signaling pair (i.e., D+ and D- (TSKEW))
`must be less than 100 ps and is measured as described in Section 6. 7.
`
`7 .1.4 Receiver Characteristics
`This section discusses the receiver characteristics for low-speed, full-speed, and full-/high-speed transceivers.
`
`7.1.4.1 Low-speed and Full-speed Receiver Characteristics
`A differential input receiver must be used to accept the USB data signal. The receiver must feature an input
`sensitivity (V DI) of at least 200 m V when both differential data inputs are in the differential common mode range
`(VcM) of0.8 V to 2.5 V, as shown in Figure 7-19.
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`In addition to the differential receiver, there must be a single-ended receiver for each of the two data lines. The
`receivers must have a switching threshold between 0.8 V (VtL) and 2.0 V (V1H). It is recommended that the
`single-ended receivers incorporate hysteresis to reduce their sensitivity to noise.
`
`Both D+ and D- may temporarily be less than V1H (min) during differential signal transitions. This period can be
`up to 14 ns (TFST) for full-speed transitions and up to 210 ns (TLST) for low-speed transitions. Logic in the
`receiver must ensure that that this is not interpreted as an SEO.
`
`Differential Input Voltage Range
`
`-1.0
`
`0.0
`
`0.2
`
`0.4
`
`0.6
`
`0.8
`
`1.0
`
`1.2
`
`1.4
`
`1.6
`
`1.8
`
`2.0
`
`2.2
`
`2.4
`
`2.6
`
`2.8
`
`3.0
`
`3.2
`
`... .... 4.6
`
`Input Voltage Range (volts)
`
`Figure 7-19. Differential Input Sensitivity Range for Low-/full-speed
`
`7.1.4.2 High-speed Receiver Characteristics
`A high-speed capable transceiver receiver must conform to the receiver characteristics specifications called out
`in Section 7 .1.4.1 when receiving in low-speed or full-speed modes.
`
`As shown in Figure 7-1, a high-speed capable transceiver which is operating in high-speed mode "listens" for an
`incoming serial data stream with the high-speed differential data receiver and the transmission envelope
`detector. Additionally, a downstream facing high-speed capable transceiver monitors the amplitude of the
`differential voltage on the lines with the disconnection envelope detector.
`
`When receiving in high-speed mode, the differential receiver must be able to reliably receive signals that
`conform to the Receiver Eye Pattern templates shown in Section 7.1.2. Additionally, it is a strongly
`recommended guideline that a high-speed receiver should be able to reliably receive such signals in the presence
`ofa common mode voltage component (VHSCM) over the range of -50 mV to 500 mV (the nominal common
`mode component of high-speed signaling is 200 mV). Low frequency chirp J and K signaling, which occurs
`during the Reset handshake, should be reliably received with a common mode voltage range of -50 mV to
`600 mV.
`
`Reception of data is qualified by the output of the transmission envelope detector. The receiver must disable data
`recovery when the signal falls below the high-speed squelch level (VHSSQ) defined in Table 7-3. (Detector must
`indicate squelch when the magnitude of the differential voltage envelope is:::; 100 mY, and must not indicate
`squelch if the amplitude of differential voltage envelope is~ 150 mV.) Squelch detection must be done with a
`differential envelope detector, such as the one shown in Figure 7-1. The envelope detector used to detect the
`squelch state must incorporate a filtering mechanism that prevents indication of squelch during differential data
`crossovers.
`
`The definition of a high-speed packet's SYNC pattern, together with the requirements for high-speed hub
`repeaters, guarantee that a receiver will see at least 12 bits of SYNC (KJKJKJKJKJKK) followed by the data
`portion of the packet. This means that the combination of squelch response time, DLL lock time, and end of
`SYNC detection must occur within 12 bit times. This is required to assure that the first bit of the packet payload
`will be received correctly.
`
`In the case of a downstream facing port, a high-speed capable transceiver must include a differential envelope
`detector that indicates when the signal on the data exceeds the high-speed Disconnect level (VHsDsc) as defined
`in Table 7-3. (The detector must not indicate that the disconnection threshold has been exceeded if the
`differential signal amplitude is :::;525 m V, and must indicate that the threshold has been exceeded if the
`differential signal amplitude is ~625 m V.)
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`When sampled at the appropriate time, this detector provides indication that the device has been disconnected.
`The details of how the disconnection envelope detector is used are described in Section 7.1. 7.3.
`
`7.1.5 Device Speed Identification
`The following sections specify the speed identification mechanisms for low-speed, full-speed, and high-speed.
`
`7.1.5.1 Low-/Full-speed Device Speed Identification
`The USB is terminated at the hub and function ends as shown in Figure 7-20 and Figure 7-21. Full-speed and
`low-speed devices are differentiated by the position of the pull-up resistor on the downstream end of the cable:
`
`•
`
`•
`
`•
`
`Full-speed devices are terminated as shown in Figure 7-20 with the pull-up resistor on the D+ line.
`
`Low-speed devices are terminated as shown in Figure 7-21 with the pull-up resistor on the D- line.
`
`The pull-down terminators on downstream facing ports are resistors of 15 kQ ±5% connected to ground.
`
`The design of the pull-up resistor must ensure that the signal levels satisfy the requirements specified in
`Table 7-2. In order to facilitate bus state evaluation that may be performed at the end of a reset, the design must
`be able to pull-up D+ or D- from O V to VIH (min) within the minimum reset relaxation time of 2.5 µs. A device
`that has a detachable cable must use a 1.5 kQ ±5% resistor tied to a voltage source between 3.0 V and 3.6 V
`(VTERM) to satisfy these requirements. Devices with captive cables may use alternative termination means.
`However, the Thevenin resistance of any termination must be no less than 900 Q.
`
`Note: Thevenin resistance of termination does not include the 15 kQ ±5% resistor on host/hub.
`
`The voltage source on the pull-up resistor must be derived from or controlled by the power supplied on the USB
`cable such that when VBUS is removed, the pull-up resistor does not supply current on the data line to which it is
`attached.
`
`D+
`
`Full-speed or
`Low-speed USB
`Transceiver
`
`'---------'Rpd
`
`Host or
`Hub Port
`
`Zo=90Q ±15%
`
`Rpu=1.5KQ ±5%
`
`Rpu
`D+
`
`D-
`
`Full-speed USB
`Transceiver
`
`Hub Upstream Port
`or
`Full-speed Function
`
`Figure 7-20. Full-speed Device Cable and Resistor Connections
`
`D+
`
`Full-speed or
`Low-speed USB
`Transceiver
`
`'-------~Rpd
`
`Host or
`Hub Port
`
`pu
`D+ Low-speed USB
`.----1-----1 Transceiver
`
`.........,,___D ..... - Slow Slew Rate
`Buffers
`
`R0u=1.5KQ ±5%
`
`Low-speed Function
`
`Figure 7-21. Low-speed Device Cable and Resistor Connections
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`7.1.5.2 High-speed Device Speed Identification
`The high-speed Reset and Detection mechanisms follow the behavioral model for low-/full-speed. When reset is
`complete, the link must be operating in its appropriate signaling mode (low-speed, full-speed, or high-speed as
`governed by the preceding usage rules), and the speed indication bits in the port status register will correctly
`report this mode. Software need only initiate the assertion of reset and read the port status register upon
`notification ofreset completion.
`
`High-speed capable devices initially attach as full-speed devices. This means that for high-speed capable
`upstream facing ports, RPu (1.5 kQ ±5%) must be connected from D+ to the 3.3 V supply (as shown in
`Figure 7-1) through a switch which can be opened under SW control.
`
`After the initial attachment, high-speed capable transceivers engage in a low level protocol during reset to
`establish a high-speed link and to indicate high-speed operation in the appropriate port status register. This
`protocol is described in Section 7.1.7.5 .
`
`7 .1.6 Input Characteristics
`The following sections describe the input characteristics for transceivers operating in low-speed, full-speed, and
`high-speed modes.
`
`7 .1.6.1 Low-speed and Full-speed Input Characteristics
`The input impedance ofD+ or D- without termination should be> 300 kQ (ZINP). The input capacitance of a
`p011 is measured at the connector pins. Upstream facing and downstream facing ports are allowed different
`values of capacitance. The maximum capacitance (differential or single-ended) (C1ND) allowed on a
`downstream facing port of a hub or host is 150 pF on D+ or D- when operating in low-speed or full-speed. This
`is comprised ofup to 75 pF of lumped capacitance to ground on each line at the transceiver and in the connector,
`and an additional 75 pF capacitance on each conductor in the transmission line between the receptacle and the
`transceiver. The transmission line between the receptacle and Rs must be 90 Q ±15%.
`
`The maximum capacitance on an upstream facing port of a full-speed device with a detachable cable (CINuB) is
`100 pF on D+ or D-. This is comprised of up to 75 pF of lumped capacitance to ground on each line at the
`transceiver and in the connector and an additional 25 pF capacitance on each conductor in the transmission line
`between the receptacle and the transceiver. The difference in capacitance between D+ and D- must be less than
`10%.
`
`For full-speed devices with captive cables, the device itself may have up to 75 pF of lumped capacitance to
`ground on D+ and D-. The cable accounts for the remainder of the input capacitance.
`
`A low-speed device is required to have a captive cable. The input capacitance of the low-speed device will
`include the cable. The maximum single-ended or differential input capacitance of a low-speed device is 450 pF
`(CL!NUA).
`
`For devices with captive cables, the single-ended input capacitance must be consistent with the termination
`scheme used. The termination must be able to charge the D+ or D- line from O V to VIH (min) within 2.5 µs.
`The capacitance on D+/D- includes the single-ended input-capacitance of the device (measured from the pins on
`the connector on the cable) and the 150 pF o[ input capacitance o[ the host/hub.
`
`An implementation may use small capacitors at the transceiver for purposes of edge rate control. The sum of the
`capacitance of the added capacitor (CEDGE), the transceiver, and the trace connecting capacitor and transceiver to
`Rs must not exceed 7 5 pF ( either single-ended or differential) and the capacitance must be balanced to within
`10%. The added capacitor, if present, must be placed between the transceiver pins and Rs (see Figure 7-22).
`
`Use offerrite beads on the D+ or D- lines offull-speed devices is discouraged.
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`T
`
`~ EDGE
`
`~ ~ CEDGE
`
`Figure 7-22. Placement of Optional Edge Rate Control Capacitors for Low-/full-speed
`
`7.1.6.2 High-speed Input Characteristics
`Figure 7-23 shows the simple equivalent loading circuit of a USB device operating in high-speed receive mode.
`
`Transceiver
`Chip
`
`Chip Boundary
`If Terminations
`~ Integrated On-die
`
`---------------------
`
`Legacy Driver
`(Output Impedance= Z0 RVl
`
`Receivers,
`RPu pull-up,
`and HS
`Driver
`
`>
`
`V
`
`;::::;:
`
`;::::;:
`
`Vbus
`
`R