`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`ZTE (USA) Inc.,
`Samsung Electronics Co., Ltd., and
`Samsung Electronics America, Inc.,
`
`Petitioner
`
`v.
`
`Fundamental Innovation Systems International LLC,
`
`Patent Owner.
`
`
`
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 7,834,586 B2
`
`Case No. IPR2018-00274
`
`
`
`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
`
`
`
`
`
`
`

`

`Table of Contents
`
`
`
`I. 
`
`Mandatory notices (37 C.F.R. § 42.8) ............................................................. 1 
`
`A. 
`
`B. 
`
`C. 
`
`Real parties-in-interest (§ 42.8(B)(1)) ................................................... 1 
`
`Related matters (§ 42.8(B)(2)) .............................................................. 1 
`
`Counsel information (§ 42.8(b)(3)) ....................................................... 2 
`
`II. 
`
`Requirements for inter partes review .............................................................. 2 
`
`A.  Grounds for standing (37 C.F.R. § 42.104(a)) ...................................... 2 
`
`B. 
`
`Identification of challenge (37 C.F.R. § 42.104(b)) .............................. 3 
`
`1. 
`
`2. 
`
`3. 
`
`4. 
`
`Challenged claims (§ 42.104(b)(1)) ............................................ 3 
`
`Prior art and statutory grounds (§ 42.104(b)(2)) ........................ 3 
`
`Claim construction (§ 42.104(b)(3)) ........................................... 5 
`
`How the claims are unpatentable (§ 42.104(b)(4)) ..................... 7 
`
`C. 
`
`Fee payment (37 C.F.R. § 42.15(a)) ...................................................... 7 
`
`III. 
`
`’586 patent background ................................................................................... 7 
`
`A. 
`
`B. 
`
`C. 
`
`Summary ............................................................................................... 7 
`
`Priority date ........................................................................................... 9 
`
`Prosecution history .............................................................................. 10 
`
`IV.  Technology background ................................................................................ 10 
`
`A. 
`
`B. 
`
`Person of ordinary skill in the art ........................................................ 10 
`
`State of the art ...................................................................................... 10 
`
`1. 
`
`2. 
`
`3. 
`
`4. 
`
`USB architecture ....................................................................... 11 
`
`USB current and voltage limits ................................................. 15 
`
`USB signaling states ................................................................. 18 
`
`TIA/EIA-644 ............................................................................. 21 
`
`Patent 7,834,586 B2
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`Table of Contents
`(continued)
`
`V.  Ground 1: Claims 8-13 are obvious in light of Theobald and Shiga. ............ 22 
`
`A. 
`
`Theobald .............................................................................................. 22 
`
`1. 
`
`2. 
`
`Resistor embodiment ................................................................ 24 
`
`Controller embodiment ............................................................. 27 
`
`B. 
`
`C. 
`
`Shiga .................................................................................................... 30 
`
`Theobald/Shiga combination ............................................................... 33 
`
`D.  Application of Theobald/Shiga combination to claims 8-13 .............. 44 
`
`1. 
`
`2. 
`
`3. 
`
`4. 
`
`5. 
`
`6. 
`
`Claim 8 ...................................................................................... 44 
`
`Claim 9 ...................................................................................... 56 
`
`Claim 10 .................................................................................... 56 
`
`Claim 11 .................................................................................... 59 
`
`Claim 12 .................................................................................... 64 
`
`Claim 13 .................................................................................... 64 
`
`VI.  Ground 2: Claims 10 and 13 are obvious in light of Kanamori. ................... 65 
`
`A.  Kanamori ............................................................................................. 65 
`
`B. 
`
`Application of Kanamori to claims 10 and 13 .................................... 68 
`
`1. 
`
`2. 
`
`Claim 10 .................................................................................... 68 
`
`Claim 13 .................................................................................... 79 
`
`VII.  Conclusion ..................................................................................................... 83 
`
`
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`Patent 7,834,586 B2
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`Exhibit List
`
`Exhibit
`
`Description
`
`1001
`
`1002
`
`1003
`
`1004
`
`1005
`
`1006
`
`1007
`
`1008
`
`1009
`
`1010
`
`1011
`
`1012
`
`1013
`
`1014
`
`1015
`
`1016
`
`1017
`
`1018
`
`U.S. Patent 7,834,586 (“’586 patent”)
`
`File History of U.S. Patent 7,834,586 (“’586 file history”)
`
`U.S. Provisional Application 60/273,021 (“’021 provisional”)
`
`U.S. Provisional Application 60/330,486 (“486 provisional”)
`
`U.S. Patent 5,925,942 (“Theobald”)
`
`U.S. Patent 6,625,738 (“Shiga”)
`
`Universal Serial Bus Specification, Revision 1.1 (“USB 1.1”)
`
`Universal Serial Bus Specification, Revision 2.0 (“USB 2.0”)
`
`Declaration of Mr. James Geier in Support of the Petition for
`Inter Partes Review of U.S. Patent 7,834,586 (“Geier”)
`
`U.S. Patent 6,625,790 (“Casebolt”)
`
`Cypress CY7C63722/23 CY7C63742/43 enCoRe™ USB
`Combination Low-Speed USB & PS/2 Peripheral Controller
`(“Cypress datasheet”)
`
`U.S. Patent 6,531,845 (“Kerai”)
`
`U.S. Patent 5,506,490 (“DeMuro”)
`
`TIA/EIA-644 Electrical Characteristics of Low Voltage
`Differential Signaling (LVDS) Interface
`
`U.S. Patent No. 5,959,601 (“’601 patent”)
`
`U.S. Patent No. 6,353,334 (“’334 patent”)
`
`U.S. Patent No. 6,366,128 (“’128 patent”)
`
`File history of U.S. Patent No. 6,366,128 (“’128 file history”)
`
`Patent 7,834,586 B2
`
`iii
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`Exhibit
`
`Description
`
`Exhibit List
`(continued)
`
`
`1019
`
`1020
`
`1021
`
`1022
`
`
`
`U.S. Patent No. 5,884,086 (“Amoni”)
`
`U.S. Patent No. 6,556,564 (“Rogers”)
`
`U.S. Patent No. 7,360,004 (“Dougherty”)
`
`U.S. Patent Application Publication No. 2008/0272741
`(“Kanamori”)
`
`Patent 7,834,586 B2
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`Petitioner, ZTE (USA) Inc., Samsung Electronics Co., Ltd., and Samsung
`
`Electronics America, Inc., requests inter partes review (“IPR”) of claims 8-13 of
`
`U.S. Patent No. 7,834,586 B2 (“the ’586 patent”). As explained below, there is a
`
`reasonable likelihood that Petitioner will prevail on at least one claim challenged in
`
`this petition.
`
`I. Mandatory notices (37 C.F.R. § 42.8)
`
`A. Real parties-in-interest (§ 42.8(B)(1))
`
`ZTE Corporation, ZTE (USA) Inc., Samsung Electronics Co., Ltd., and
`
`Samsung Electronics America, Inc., are the real parties-in-interest.
`
`B. Related matters (§ 42.8(B)(2))
`
`The ’586 patent is the subject of Civil Action Nos. 2:17-cv-00145-JRG,
`
`2:16-cv-01424-JRG-RSP, and 2:16-cv-01425-JRG-RSP, which are pending in the
`
`U.S. District Court for the Eastern District of Texas, and Civil Action No. 3:17-cv-
`
`01827-N, which is pending in the U.S. District Court for the Northern District of
`
`Texas.1 The ’586 patent is also subject to IPR2018-00485 and IPR2018-00493,
`
`filed January 12, 2018 and January 15, 2018, respectively, by different petitioners.
`
`Patents related to the ’586 patent are subject to the following IPR
`
`proceedings.
`
`
`1 The unpatentability positions herein take into account Patent Owner’s
`infringement positions in the co-pending litigation and in some instances are based
`in-part on these positions.
`
`Patent 7,834,586 B2
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`
`
`Patent
`7,239,111
`
`8,232,766
`
`8,624,550
`
`
`
`IPR Case No.
`IPR2018-00487
`IPR2018-00495
`IPR2018-00214
`IPR2018-00215
`IPR2018-00472
`IPR2018-00508
`IPR2018-00110
`IPR2018-00111
`IPR2018-00460
`IPR2018-00461
`IPR2018-00465
`
`Petitioner is unaware of any other pending matter that would affect, or by
`
`affected by, a decision in this proceeding.
`
`C. Counsel information (§ 42.8(b)(3))
`
`Lead counsel is Charles M. McMahon. Back-up counsel are Hersh H.
`
`Mehta, Gregory S. Arovas, Robert A. Appleby, Todd M. Friedman, Eugene
`
`Goryunov, and Alan Rabinowitz. Petitioner consents to e-mail service. The service
`
`information is identified in the signature block of this petition.
`
`II. Requirements for inter partes review
`
`A. Grounds for standing (37 C.F.R. § 42.104(a))
`
`Petitioner certifies that: (i) the ’586 patent is available for IPR and
`
`(ii) Petitioner is not barred or estopped from requesting an IPR challenging the
`
`’586 patent’s claims. Specifically, Petitioner certifies that: (1) no Petitioner entity
`
`or real party-in-interest has filed a civil action challenging the validity of any claim
`
`of the ’586 patent; (2) Petitioner filed this petition within one year of the date they
`
`Patent 7,834,586 B2
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`were served with a complaint asserting infringement of the ’586 patent; and (3) the
`
`estoppel provisions of 35 U.S.C. § 315(e)(1) do not prohibit this IPR.
`
`B.
`
`Identification of challenge (37 C.F.R. § 42.104(b))
`
`1.
`
`Challenged claims (§ 42.104(b)(1))
`
`Petitioner challenges claims 8-13 of the ’586 patent.
`
`2.
`
`Prior art and statutory grounds (§ 42.104(b)(2))
`
`Petitioner requests that the Board review and cancel claims 8-13 of the ’586
`
`patent on the following grounds:
`
` Ground 1: Under pre-AIA 35 U.S.C. § 103(a), claims 8-13 are obvious in
`
`light of U.S. Patent No. 5,925,942 (Exhibit 1005, “Theobald”), prior art
`
`under § 102(b),2 and U.S. Patent No. 6,625,738 (Exhibit 1006, “Shiga”),
`
`prior art under § 102(e).3
`
` Ground 2: Under § 103(a), claims 10 and 13 are obvious in light of U.S.
`
`Patent Application Publication No. 2008/0272741
`
`(Exhibit 1022,
`
`“Kanamori”), prior art under § 102(b).4
`
`As explained in Section III.B below, claims 10 and 13 of the ’586 patent are
`
`
`2 Theobald’s patent date, July 20, 1999, predates the ’586 patent’s earliest claimed
`priority date, March 1, 2001, by more than one year.
`3 Shiga’s filing date, December 6, 1999, predates the ’586 patent’s earliest claimed
`priority date, March 1, 2001.
`4 Kanamori’s publication date, November 6, 2008, predates the ’586 patent’s
`earliest possible priority date, February 26, 2010, by more than one year.
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`not entitled to the ’586 patent’s earliest claimed priority date (March 1, 2001) and
`
`the earliest possible priority date for claims 10 and 13 is the ’586 patent’s actual
`
`filing date, February 26, 2010. Ground 1 applies to every challenged claim even if
`
`claims 10 and 13 are entitled to the claimed priority date (March 1, 2001). Ground
`
`2 is based on intervening prior art and therefore applies to claims 10 and 13 only if
`
`the earliest possible priority date for those claims is February 26, 2010.
`
`This petition is proper under 35 U.S.C. § 314(a) and General Plastic
`
`Industrial Co., Ltd. v. Canon Kabushiki Kaisha, IPR2016-01357, Paper 19
`
`(P.T.A.B. Sept. 6, 2017) (precedential). Recently, two different petitioners filed
`
`petitions (in IPR2018-00485 and IPR2018-00493, respectively) challenging claims
`
`of the ’586 patent (General Plastic factors 1 and 4). At this early stage, no
`
`response or Board decision has been filed in either proceeding (General Plastic
`
`factor 3). The present Petitioner was not involved with the preparation or filing of
`
`the IPR2018-00485 or IPR2018-00493 petitions (General Plastic factor 5).
`
`Petitioner does not expect that the minimal time between filing of the three
`
`petitions will affect the Board’s resources because none of the petitions has been
`
`accorded a filing date and the three IPR proceedings can readily be consolidated if
`
`the Board wishes to do so (General Plastic factors 6 and 7). Thus, at least General
`
`Plastic factors 1, 3, 4, 5, 6, and 7 weigh in favor of instituting the present petition.
`
`This petition is also proper under § 325(d). During the ’586 patent’s
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`prosecution, the examiner did not consider any of the prior art references that
`
`constitute the grounds presented in this petition. Mr. Geier’s declaration also was
`
`not before the examiner. Accordingly, the grounds in this petition do not present
`
`the same or substantially the same prior art or arguments as were previously
`
`presented to the Patent Office. Accordingly, the Board should decline to exercise
`
`its discretion under § 325(d), as it has done in similar circumstances. See Comcast
`
`Cable Comms. LLC v. Rovi Guides, Inc., IPR2017-00939, Paper 11 at 36-38
`
`(P.T.A.B. Sept. 11, 2017); Juniper Networks, Inc. v. Mobile Telecommunications
`
`Techs., LLC, IPR2017-00642, Paper 24 at 8-9 (P.T.A.B. Jul. 7, 2017).
`
`3.
`
`Claim construction (§ 42.104(b)(3))
`
`The challenged claims receive the broadest reasonable interpretation (BRI)
`
`in light of the specification of the ’586 patent. 37 C.F.R. § 42.100(b).
`
`Under the BRI standard, Petitioner requests that the Board construe the
`
`terms USB enumeration,5 which appears in claim 8, as “the bus-enumeration
`
`procedure specified in the USB 2.0 specification or an earlier USB specification”
`
`at the time of the alleged invention.
`
`The “USB” modifier in USB enumeration indicates that USB enumeration
`
`refers to an enumeration procedure specified in a USB specification.
`
`The ’586 patent repeatedly refers to enumeration as a procedure specified in
`
`5 This petition uses italics to refer to claim language in the ’586 patent.
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`a then-existing USB specification (i.e., USB 2.0 or earlier). For example, the ’586
`
`patent states that “[i]n accordance with the USB specification, typical USB power
`
`source devices, such as hubs and hosts, require that a USB device participate in a
`
`host-initiated process called enumeration in order to be compliant with the current
`
`USB specification in drawing power from the USB interface.”6 As another
`
`example, the ’586 patent states that “[t]he USB specification specifies a process for
`
`transferring energy across the USB called enumeration and limits the electrical
`
`current that can flow across the USB.”7
`
`From this disclosure, POSITAs would have understood that when the ’586
`
`patent’s specification refers to “enumeration,” it is referring to a specific bus-
`
`enumeration procedure in the USB 2.0 specification or an earlier USB
`
`specification.8 For example, the ’586 patent describes enumeration as a “host-
`
`initiated process” needed “to be compliant with the current USB specification in
`
`drawing power from the USB interface.”9 Consistent with the ’586 patent’s
`
`description at column 1, lines 60-62, the USB 2.0 specification describes bus
`
`enumeration as a host-initiated process that a USB device must undergo before it
`
`
`6 Ex. 1001 (’586 patent) 1:58-62.
`7 Ex. 1001 (’586 patent) 8:5-8.
`8 Ex. 1009 (Geier) ¶ 44.
`9 Ex. 1001 (’586 patent) 1:60-62.
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`can communicate data over the USB interface.10 See Section IV.B. Thus, in the
`
`context of the ’586 patent, POSITAs would have immediately recognized that
`
`“enumeration” refers
`
`to
`
`the bus-enumeration procedure
`
`in
`
`the USB 2.0
`
`specification or an earlier USB specification.11
`
`Petitioner expressly reserves its right to advance different constructions in
`
`the related district court cases, which employ a different claim construction
`
`standard.
`
`4. How the claims are unpatentable (§ 42.104(b)(4))
`
`Sections V and VI below explain how claims 8-13 of the ’586 patent are
`
`unpatentable and identify where each claim element is found in the prior art.
`
`C.
`
`Fee payment (37 C.F.R. § 42.15(a))
`
`Petitioner authorizes the Office to charge the filing fee and any other
`
`necessary fee to Deposit Account 50-0417.
`
`III.
`
`’586 patent background
`
`A.
`
`Summary
`
`The ’586 patent “relates generally to power adapters.”12 The ’586 patent has
`
`13 claims, of which claims 8-13 are challenged in this petition. Independent claims
`
`8 and 11 are reproduced below.
`
`
`10 Ex. 1009 (Geier) ¶ 35 (citing Ex. 1008 (USB 2.0) 243).
`11 Ex. 1009 (Geier) ¶ 44.
`12 Ex. 1001 (“’586 patent”) at 1:34.
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`8. A method of charging a battery in a mobile device, the
`mobile device configurable for use in a wireless
`telecommunications network, comprising:
`providing a Universal Serial Bus (“USB”) interface
`configured to allow reception of a USB cable, and,
`receiving power on a V-bus power line at the USB
`interface;
`providing an operable connection between the power
`received at the USB interface on the V-bus power
`line and a charging subsystem;
`having a battery in operable connection to the
`charging subsystem;
`providing power to the battery using the charger
`subsystem; and,
`detecting an identification signal at a D+ and a D−
`data line of the USB interface, the identification
`signal being different than USB enumeration.
`
`11. A method for charging a battery in a mobile device,
`the mobile device configurable for use in a wireless
`telecommunications network, comprising:
`providing a Universal Serial Bus (“USB”) interface
`configured to allow reception of a USB cable, and,
`to receiving power on a V-bus power line at the
`USB interface;
`providing an operable connection between the power
`received at the USB interface on the V-bus power
`line and a charging subsystem;
`having a battery in operable connection to the
`charging subsystem;
`providing power to the battery using the charger
`subsystem in one of a plurality of charge modes;
`using a microprocessor and memory to process the
`signals received on the USB interface data lines,
`such that an identification signal received at the
`D+ and D− lines indicating a charging connection
`is available is recognized by the device.
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`B.
`
`Priority date
`
`The ’586 patent issued from U.S. Patent Application No. 12/714,204, which
`
`was filed on February 26, 2010.13 That application claims priority through a series
`
`of continuations to two provisional applications: (1) U.S. Provisional Application
`
`No. 60/273,021 (“the ’021 provisional”) (Ex. 1003), filed March 1, 2001; and
`
`(2) U.S. Provisional Application No. 60/330,486 (“the ’486 provisional”) (Ex.
`
`1004), filed October 23, 2001.
`
`However, none of the ’586 patent’s priority applications discloses that the
`
`identification signal is a result of using a resistance between the D+ and D- data
`
`lines (which is the claim element that claims 10 and 13 add). Moreover, to the
`
`extent Patent Owner argues the “resistance” claim element would have been
`
`obvious, the Federal Circuit has repeatedly held that a disclosure that merely
`
`renders obvious the claimed invention is not sufficient to satisfy the written
`
`description requirement. See, e.g., PowerOasis, Inc. v. T-Mobile USA, Inc., 522
`
`F.3d 1299, 1306-07 (Fed. Cir. 2008).
`
`Therefore, the earliest possible priority date for claims 10 and 13 is February
`
`26, 2010, the ’586 patent’s actual filing.14
`
`
`13 Ex. 1002 (’586 file history) 48.
`14 Petitioner reserves its right to challenge the validity of claims 10 and 13 in
`district court based on lack of written description and/or enablement.
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`C.
`
`Prosecution history
`
`During prosecution, the examiner did not issue any § 102 or § 103 rejections
`
`of the pending claims. The examiner issued a non-final office action, rejecting
`
`every pending claim on the ground of nonstatutory obviousness-type double
`
`patenting over claims 1-12 of U.S. Patent No. 7,737,657.15 In response, the
`
`applicant filed a terminal disclaimer.16 In response, the examiner issued a notice of
`
`allowance,17 leading to the issuance of the ’586 patent.18
`
`IV. Technology background
`
`A.
`
`Person of ordinary skill in the art
`
`The person of ordinary skill in the art (POSITA) of the subject matter of the
`
`’586 patent would have had a master’s degree in electrical engineering, computer
`
`science, or a related field, plus 2-3 years of experience with Universal Serial Bus
`
`(“USB”). Along with this petition, Petitioner submits the declaration of James T.
`
`Geier, who has been a POSITA since at least the ’586 patent’s claim priority
`
`date.19
`
`B.
`
`State of the art
`
`As of March 1, 2001 (the ’586 patent’s claimed priority date), POSITAs
`
`
`15 Ex. 1002 (’586 file history) 153-157.
`16 Ex. 1002 (’586 file history) 169-178.
`17 Ex. 1002 (’586 file history) 184-187.
`18 Ex. 1002 (’586 file history) 201.
`19 Ex. 1009 (Geier) ¶¶ 3-6, 23.
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`would have had the following background knowledge of the state of the art.
`
`1.
`
`USB architecture
`
`Since its inception in 1995, the USB Implementers Forum, Inc. (“USB-IF”)
`
`has been responsible for the advancement and adoption of USB technology.20 As
`
`of December 2000, USB-IF had more than 900 member companies that helped
`
`facilitate the development of USB.21
`
`USB-IF standardized USB technology in the USB specification and its
`
`various revisions.22 On September 23, 1998, USB-IF released Universal Serial Bus
`
`Specification, Revision 1.1 (“USB 1.1”), which was widely adopted by industry
`
`leaders and consumers.23 On April 27, 2000, USB-IF released USB Revision 2.0
`
`(“USB 2.0”).24 Among USB 2.0’s improvements were faster speeds and additional
`
`functionality.25 Like USB 1.1, USB 2.0 was widely adopted by the industry.26
`
`USB 1.1 and 2.0 specified the architecture for a USB system.27 Generally, a
`
`USB system includes a USB host, one or more USB devices, and a USB
`
`
`20 Ex. 1009 (Geier) ¶ 30.
`21 Ex. 1009 (Geier) ¶ 31.
`22 Ex. 1009 (Geier) ¶ 31.
`23 Ex. 1009 (Geier) ¶ 31.
`24 Ex. 1009 (Geier) ¶ 31 (citing Ex. 1008 (USB 2.0) 1).
`25 Ex. 1009 (Geier) ¶ 31.
`26 Ex. 1009 (Geier) ¶ 31.
`27 Ex. 1009 (Geier) ¶ 32.
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`interconnect.28 A USB host (e.g., a laptop computer system) interacts with USB
`
`devices and is responsible for tasks such as (i) detecting the attachment and
`
`removal of USB devices; (ii) managing control and data flow between the host and
`
`USB devices; (iii) collecting status and activity statistics; and (iv) providing power
`
`to attached USB devices.29 A USB device connects to the USB host, and falls into
`
`one of two categories: (i) a hub, which has the ability to provide additional USB
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`attachment points, or (ii) a function, which is a device that is able to transmit or
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`receive data or control information over the USB bus (e.g., a peripheral device,
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`such as a keyboard, mouse, or mobile phone).30 A USB interconnect is the manner
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`in which USB devices are connected and communicate with the host.31 The
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`following figure depicts a typical USB architectural configuration of a USB host,
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`interconnect, and devices:32
`
`
`28 Ex. 1009 (Geier) ¶ 32 (citing Ex. 1008 (USB 2.0) 15; Ex. 1007 (USB 1.1) 15).
`29 Ex. 1009 (Geier) ¶ 32 (citing Ex. 1008 (USB 2.0) 24; Ex. 1007 (USB 1.1) 24).
`30 Ex. 1009 (Geier) ¶ 32 (citing Ex. 1008 (USB 2.0) 22-24; Ex. 1007 (USB 1.1) 21-
`24).
`31 Ex. 1009 (Geier) ¶ 32 (citing Ex. 1008 (USB 2.0) 15; Ex. 1007 (USB 1.1) 15).
`32 Ex. 1009 (Geier) ¶ 32 (citing Ex. 1008 (USB 2.0) Figure 4-4).
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`Ex. 1008 (USB 2.0) Figure 4-4.
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`
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`USB 1.1 and 2.0 also specified the USB cable structure.33 The USB cable
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`“consist[ed] of four conductors,
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`two power conductors, and
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`two signal
`
`conductors.”34 The following figure from USB 2.0 depicts the four wires within a
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`USB cable.35
`
`Ex. 1008 (USB 2.0) Figure 4-2.
`
`
`
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`33 Ex. 1009 (Geier) ¶ 33 (citing Ex. 1008 (USB 2.0) 86; Ex. 1007 (USB 1.1) 74).
`34 Ex. 1009 (Geier) ¶ 33 (citing Ex. 1008 (USB 2.0) 86; Ex. 1007 (USB 1.1) 74).
`35 Ex. 1009 (Geier) ¶ 33 (citing Ex. 1008 (USB 2.0) Figure 4-2).
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`VBUS and GND deliver power, and D+ and D- carry signals for communication
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`between a USB host and the connected device.36
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`USB 1.1 and 2.0 also specified the USB connector structure.37 For example,
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`USB 1.1 and USB 2.0 specified Series “A” and Series “B” connectors.38 “Table 6-
`
`1 provides the standardized contact terminating assignments by numbers and
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`electrical value for Series ‘A’ and Series ‘B’ connectors.”39
`
`Ex. 1008 (USB 2.0) Figure 4-2.
`
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`According to USB 1.1 and USB 2.0, “[a]ll USB devices must have the standard
`
`
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`Series ‘A’ connector.”40 “The ‘B’ connector allows device vendors to provide a
`
`
`36 Ex. 1009 (Geier) ¶ 33 (citing Ex. 1008 (USB 2.0) 17-18; Ex. 1007 (USB 1.1)
`17).
`37 Ex. 1009 (Geier) ¶ 34 (citing Ex. 1008 (USB 2.0) 85, 94; Ex. 1007 (USB 1.1) 73,
`82).
`38 Ex. 1009 (Geier) ¶ 34.
`39 Ex. 1009 (Geier) ¶ 34 (citing Ex. 1008 (USB 2.0) 94; Ex. 1007 (USB 1.1) 82).
`40 Ex. 1008 (USB 2.0) 85; Ex. 1007 (USB 1.1) 73.
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`standard detachable cable.”41
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`Ex. 1008 (USB 2.0) Figure 6-1.
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`USB 2.0 also specified how the USB host is to configure a USB device. For
`
`
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`example, USB 2.0 stated that “[w]hen a USB device is attached to or removed
`
`from the USB, the host uses a process known as bus enumeration to identify and
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`manage the device state changes necessary.”42 In its “Bus Enumeration” section,
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`USB 2.0 specified the bus-enumeration requirements, including eight actions taken
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`“[w]hen a USB device is attached to a powered port.”43
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`2.
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`USB current and voltage limits
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`USB 2.0 also imposed certain current and voltage limits on VBUS.44 For
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`example, USB 2.0 limited a USB device’s current draw on VBUS to “one unit load
`
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`41 Ex. 1008 (USB 2.0) 85; Ex. 1007 (USB 1.1) 73.
`42 Ex. 1009 (Geier) ¶ 35 (citing Ex. 1008 (USB 2.0) 243).
`43 Ex. 1009 (Geier) ¶ 35.
`44 Ex. 1009 (Geier) ¶ 36.
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`[i.e., 100 mA] or less until configured.”45 USB 2.0 also stated that “[d]epending on
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`the power capabilities of the port to which the device is attached, a USB device
`
`may be able to draw up to five unit loads [i.e., 500 mA] from VBUS after
`
`configuration.”46 As shown below, USB 2.0 also imposed a 5.25 V limit on the
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`VBUS line.47
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`Ex. 1008 (USB 2.0) Table 7-7 (in part).
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`Soon after USB was released, practitioners recognized that the USB limit of
`
`
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`500 mA posed problems in many contexts requiring more power.48 For example,
`
`Amoni discloses:
`
`“One problem with the universal serial bus is that it
`provides only one voltage. Devices that operate at
`different voltages or have high power requirements are
`required to supply their own voltage sources and power
`sources. In some environments, for instance, the retail
`point-of-sale environment, this additional cabling for
`power creates a non-aesthetic appearance at the store
`
`
`45 Ex. 1009 (Geier) ¶ 36 (quoting Ex. 1008 (USB 2.0) 245).
`46 Ex. 1009 (Geier) ¶ 36.
`47 Ex. 1009 (Geier) ¶ 36 (quoting Ex. 1008 (USB 2.0) 175, 178).
`48 Ex. 1009 (Geier) ¶ 37.
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`front.”49
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`Similarly, in the context of a USB speakerphone system, Rogers discloses:
`
`“One difficulty with the existing USB is that it has only a
`limited capability to provide power to a connected
`device. As it is generally known, USB has two wires in
`the cable, which supply 5 VDC. Current is limited to 0.5
`Amp. Additionally, any given device can only use 0.1
`Amp. USB allows devices to be chained, so all chained
`devices must share the same power. This means that the
`maximum power available is 2.5 Watts, with 0.5 Watt for
`each device. This is too little for many potential
`devices.”50
`
`Practitioners overcame the limit and created systems in which a device
`
`connected through USB to a second device drew power from the latter in excess of
`
`the 500 mA standard limit.51 For example, Amoni discloses that two devices
`
`connected through USB could negotiate the amount of current to be drawn by one
`
`of the devices from the other, and that through such negotiation, the one device
`
`could draw more than 3 A of current from the other.52 Similarly, Dougherty
`
`discloses that a mobile computer connected to a docking station through USB
`
`could charge its battery by drawing up to 2.5 A of current “across the USB
`
`49 Ex. 1019 (Amoni) 2:19-26. Amoni is prior art under pre-AIA § 102(b) because
`its issuance date is March 16, 1999, more than one year prior to the 586 patent’s
`claimed priority date, March 1, 2001.
`50 Ex. 1020 (Rogers) 10:67-11:8. Rogers is prior art under pre-AIA § 102(e)
`because its filing date, February 8, 2001, predates the 586 patent’s claimed priority
`date, March 1, 2001.
`51 Ex. 1009 (Geier) ¶ 38.
`52 Ex. 1009 (Geier) ¶ 38 (citing Ex. 1019 (Amoni) 7:16-26).
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`connectors.”53
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`3.
`
`USB signaling states
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`USB 2.0 also specified different signaling states on the D+ and D- lines.54
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`Some of these states (e.g., Differential 0, Differential 1, Data J State, and Data K
`
`State) transmit data while others (e.g., Single-ended 0, Single-Ended 1) are used as
`
`specific signaling conditions.55 Relevant to this petition is the SE1 condition.56
`
`USB 2.0 defined “SE1” as “a state in which both the D+ and D- lines are at a
`
`voltage above VOSE1 (min), which is 0.8 V.”57 USB 2.0 also discloses that the
`
`low- and full-speed USB drivers “must never ‘intentionally’ generate an SE1 on
`
`the bus.”58 In other words, according to USB 2.0, an abnormal data condition
`
`would occur if D+ and D- were intentionally set in a high state above 0.8 V.59
`
`Finally, POSITAs would have also known that the SE1 condition would be a
`
`logical choice for signaling information about a device without interfering with
`
`USB signaling.60 For example, U.S. Patent No. 6,625,790 (Ex. 1010, “Casebolt”)
`
`
`53 Ex. 1009 (Geier) ¶ 38 (quoting Ex. 1021 (Dougherty) 7:49-53). Dougherty is
`prior art under 35 U.S.C. § 102(e) because its effective U.S. filing date, June 30,
`2000, predates the ’586 patent’s earliest claimed priority date, March 1, 2001.
`54 Ex. 1009 (Geier) ¶ 39 (citing Ex. 1008 (USB 2.0) 123).
`55 Ex. 1009 (Geier) ¶ 39 (citing Ex. 1008 (USB 2.0) 144-146, Table 7-2).
`56 Ex. 1009 (Geier) ¶ 39.
`57 Ex. 1009 (Geier) ¶ 40 (quoting Ex. 1008 (USB 2.0) 123).
`58 Ex. 1009 (Geier) ¶ 40 (quoting Ex. 1008 (USB 2.0) 123).
`59 Ex. 1009 (Geier) ¶ 40.
`60 Ex. 1009 (Geier) ¶ 41.
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`discloses that SE1 could be used as a special signaling mode.61 As shown below,
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`the D+ and D- lines would be connected to Vcc (+5V) to signal a PS/2 adapter.62
`
`Ex. 1011 (Casebolt) FIG. 2C (annotated).
`
`
`Ex. 1011 (Casebolt) Table (annotated).
`
`
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`
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`Indeed, knowledge of SE1 was so common that Cypress Semiconductor integrated
`
`it into their enCoRe product, stating “USB D+ and D- lines can also be used for
`
`61 Under pre-AIA § 102(e), Casebolt is prior art to every claim of the ’586 patent.
`Casebolt’s filing date, October 1, 1999, predates the ’586 patent’s earliest claimed
`priority date, March 1, 2001.
`62 Ex. 1010 (Casebolt) FIG. 2C (annotated), 7:41-54, Table 1.
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`PS/2 SCLK and SDATA pins, respectively. With USB disabled, these lines can be
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`placed in a high impedance state that will pull up to VCC.”63 As yet another
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`example, U.S. Patent No. 6,531,845 (Ex. 1012, “Kerai”) used a high state on USB
`
`D+ and D- for charging.64 As shown below, both USB D+ and D- (yellow) are
`
`brought to a high state in cooperation with the charging system (green) for a
`
`spe