US. Patent
`
`Sep, 22, 1998
`
`Sheet 1 01'12
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`5,812,461
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`ZTE/SAMSUNG 1018-0189
`IPR2018-00274
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`US. Patent
`
`Sep. 22, 1998
`
`Sheet 2 of 12
`
`5,812,461
`
`
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`ZTE/SAMSUNG 1018-0190
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`|PR2018-00274
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`IPR2018-00274
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`US. Patent
`
`Sep. 22,1998
`
`Sheet 3 01'12
`
`5,812,461
`
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`|PR2018-00274
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`US. Patent
`
`Sup. 22. 1998
`
`Sheet 4 0f 12
`
`5,812,461
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`[3-3.4
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`cos/c ZERO MAXIMUM VOLTAGE
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`
`ZTE/SAMSUNG 1018-0192
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`US. Patent
`
`Sep. 22, 1998
`
`Sheet 5 0f 12
`
`5,812,461
`
`
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`ZTE/SAMSUNG 1018-0193
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`|PR2018—00274
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`IPR2018-00274
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`US. Patent
`
`Rep. 22. 1998
`
`Slice! 6 of [2
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`5,312,461
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`US. Patent
`
`Rep. 22. 1998
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`51m: 7 of 12
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`5,812,461
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`
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`US. Patent
`
`Sep. 22,1998
`
`Sheet 8 0112
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`5,812,461
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`
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`U.S. Patent
`
`Rep. 22. 1998
`
`Slice! 9 of [2
`
`5,312,461
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`US. Patent
`
`$911.22, 199}:
`
`Sheet III or I:
`
`5,812,461
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`ZTE/SAMSUNG 1018-0198
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`US. Patent
`
`Sep. 22, 1993
`
`Sheet 11 of 12
`
`5,812,461
`
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`TI CORE
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`US. Patent
`
`Scp. 22. 1998
`
`Sheet 12 or 12
`
`5,812,461
`
`[-3. Nb
`
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`ZTE/SAMSUNG 1018-0200
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`5,812,461
`
`1
`DRIVER CIRCUIT FOR ADDRESSING CORE
`MEMORY AND A METHOD FOR THE SAME
`RELATED APPI .ICA’IIONS
`This is a divisional of application Ser. No. 08/487,841
`filed on Jun 7, 1995, U131 Pat. No. 5594.696, which is a
`continuation in part of application Ser. No. 07/912,112
`entitled VLSI Memory with Increased Memory Access
`Speed, Increased Memory Cell Density and Decreased Para,
`silic Capacitance, filed on Jul. 9, 1992, which issued as US.
`Pat. No. 5,241,497, and which in turn is a
`tile wrapper
`continuation of application Serf NtL 07/538,185 filed on Jun
`14, 1990. and now abandoned. This application is also a
`continuation in part of application Ser. No. 08/016,811,
`entitled Improvements in a Very large Scale Integrated
`Planar Read Only Memory, filed on Feb. I], [993, which
`issued as US. Pal No. 5,459,693. Each ol‘ the foregoing
`referenced parent applications are explicitly incorporated
`herein by reference,
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`The invention relates to the fteld of semiconductor memo-
`ries and in panicular to memory cures for read only memo,
`ries (ROM, EPROM) or flash memories (EEPROM).
`Specifically,
`the invention relates to improvements in a
`method of precharg'ing a memory core, sensing of the data
`lines in a memory core, and address decoding ofthe memory
`core.
`2. Description of the Prior Art
`Grounded Memory Core Design and Methodology
`Architectures for very large scale integrated (VLSI)
`ROMs using virtual ground lines and diffusion bits lines to
`access banks of core cells are well known Descriptions of
`such architectures can he found in Okarla, eta]. “'18 Mb
`ROM Design Using Bank Select Architecture," Integrated
`Circuits Group, Sharp (.‘urp. However, such architectures are
`subject to several limitations and drawbacks as a discussed
`in the parent applications of this application and as me
`implicitly further detailed in the brief summary below
`wherein the improvements of the invention of the prior art
`and over the art of the parent application are esplainedt
`Differential Sense Amplifier
`Although not prior artI the parent application shows a
`sense amplifier approach using a current mirror. Aschernatic
`drawing of this previous sense amplifier is presented in FIG.
`21 of the parent, which is reproduced here as 13le 5, since
`many of the improvements of the invention are best under-
`stood in comparison In the design in the parent applicaliuni
`Both approaches List: the same clocking signals and have
`the same timing. Also. both approaches amplify voltage
`differences of about 0.15 volts. The previous design ampli-
`fies voltages that are close to 213 volts with dill'crcnces of
`about (1.15 volts.
`The current mirror approach used in the previous design
`loads the differential amplifier output nodes with an unbal-
`anced capacitive load. This unbalanced load favors one side
`of the latch over the other side of the latch. It would be
`possible to add capacitance to the previous design to bal-
`anced the nodes, but extra capacitance slows the latch and
`reduces the transient response of the latch.
`Because of the small difference in voltages being sensed,
`small imbalances in the previous design of the ditl'ercntial
`amplifier may have a large enough ctl'ect
`to cause the
`differential amplifier to fall into the wrong state.
`
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`Virtual Ground and Bit Line Decoder
`line decoder is
`A design for a Virtual ground and bit
`described in the copending parent application in connection
`with FIGS. 18-20 (N387). Another design for a virtual
`ground and bit line decoder is shown in L‘Operttling applica-
`tion NUSl-D in connection with FIGSI lw-Zi
`A previous interlock method was used in the CMOS 4
`Megabyte ROM circuit. A schematic diagram of a previous
`interlock method is presented in FIG. 8.
`The designs iii
`the parent application both show
`approaches to decoding virtual ground lines and bit lines in
`a ROM. These previous decoder circuits are similar to the
`present decoder circuit, but the methods of decoding are
`difi‘crent as will he described below.
`The interlock method shown in FIG 8 is an example of
`a previous interlock method. The present interlock method is
`an improvement of this design.
`BRIEF SUMMARY OF THE INVENTION
`
`Grounded Memory Core Design and Methodology
`The memory core design of the invention is diagrammatie
`caliy shown in the chip layout depiction of FIG. land in the
`corresponding schematic of FIG. 2. The operation of the bit
`lines and virtual ground lines of the circuit of the invention
`as shown in FIGS.
`1 and 2 is very different from that
`described in the copending parent of this application. The
`operation of the polysilicon word lines, WLl—WI.n, or the
`ptliysilicon select lines I35, (TA, and (TB are the same as
`described in the parent, which is expressly incorporated
`herein by reference, and therefore will not he described in a
`detail greater than necessary to provide contextual support in
`this specification,
`There are at least live separate impruvernents in operation
`for the invention First, the bit lines and virtual ground lines
`are all precharged to ground instead of being precharged to
`an internal low supply voltage of about 2 volts. In the parent
`application,
`the internal low voltage supply or prechttrge
`voltage is referred to as VPC. The VF(‘ voltage is not
`required for the invention.
`Second. the operation of the virtual ground lines in the
`parent was to first precharge all virtual ground lines to VPC,
`then select one of the two virtual ground lines for the
`selected hit and switch it from VPC to ground. The second
`virtual ground line for the selected bit remained Iloating at
`the VPC voltage level.
`In the invention, both of the two virtual ground lines are
`selected for the selected hit and both selected virtual ground
`lines are driven to ground during the prechargc phase. At the
`top of the memory array, all virtual ground lines in the
`ntemory array are prcchargcd to ground during the precharge
`phase. Next. during the sensing phase, the operation of the
`two virtual ground fines for the selected bit is changed to
`selectively hold one virtLIa] ground line atgruund and switch
`the second vtrtua] ground line to a positive voltage. This is
`accomplished by means of a modified virtual ground line
`decoder and driver which are new with the invention.
`Third, the operation of the bit lines in the prior art is to
`prechurge all bit lines to VP(‘, and the then the selected bit
`
`line ' discharged toward ground if the selected memory core
`
`I-‘li't' s programmed with a low threshold voltage. If the
`selected memory core PET is programmed with a high
`threshold voltage, the bit line remains floating at the VPC
`voltage level.
`In the invention, all bit lines are precharged to ground
`during the precharge phase. In the following sensing phase,
`
`ZTE/SAMSUNG 1018-0201
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`line is driven positive by the selected
`the selected bit
`ntemory cure FET if it is programmed with a low threshold
`voltage. If the selected memory core PET is programmed
`with a high threshold voltage, the bit line remains floating at
`the ground level, or it may he held at ground by means otthe
`second virtual ground line, which is held at ground, and low
`threshold core FETs, adjacent
`to the selected core FET,
`which are connected to the selected word line.
`Fourth, a core FET programmed with a low threshold
`voltage is used to define a logic zero at the ROM output, and
`a core lili'l' programmed with a high threshold voltage is
`used to define a logic one at the ROM output. By these
`definitions,
`the total diffusion capacitance on a virtual
`ground line is minimized when the memory cells connected
`to the line are programmed with more logic zeros than lUgit:
`ones. The definitions take advantage of the l'act that a core
`FET programmed with a low thrcshold voltagc, a logic zero,
`has a significantly lower diffusion junction capacitance.
`Also, the definitions take advantage of the fact that unused
`code space in a ROM code pattern is usually titled with logic
`zeros, and that some ROM code patterns, like a font code for
`generating alphanumeric characters, have more logic zeros
`tltan logic ones in the total code pattcm.
`Fifth, the memory con: as illustrated in FIG. 2 is not the
`only cure circuit which can be used in the grounded core ’
`operating mode defined by the current
`il'IVcl'lliOI'l. ()ther
`memory core designs which are compatible with the E0],
`lowing circuit functions can be used, such as:
`l) a voltage sensing or current scnsc amplifier;
`2) a virtual ground line decoder circuit which selects hoth
`virtual ground tines V611 and VGLZ associated with
`the selected main bit line hit line;
`3) a virtual ground line driver circu it to drive both 01' the
`two selected metal virtual ground lines, and it a prc~
`charge phase is used, both of the two selected metal
`virtual ground lines are driven to prcchztrge ground
`level, then, during the sensing phase, one of the two
`metal virtual ground lines is held at ground and the
`other of the two metal virtual ground lines is switched
`to a voltage source; and
`4) It' a precharge phase is used, a precharge circuit is used
`[0 drive all metal virtual ground lines and metal bit lines
`to ground during the precharge phase. During the
`sensing phase, the prcchargc circttit is turned olf.
`Changing the operation of the memory core from the
`protocol described in the above referenced parent applica-
`tion to that of the invention provides significant advantages.
`First,
`the low voltage supply, VPC,
`is eliminated. Some
`ROMS, having 8 megabits or more, may have a standby
`current specification of 100 microamperes maximum from
`the VDD supply voltage. Prior ar1 [ethnology of maintaining
`an 8 megabit memory core at
`the VPC voltage during
`standby is impractical due to the junction leakage current
`drawn by the memory cnrc arrays in thc ROM.
`Using a memory cure precharged to ground eliminates
`VPC and resolves the standby junction leakage current
`problem. Using a memory core without a precharg'e phase
`and with current sensing as defined by the invention climii
`nates VPC‘ and resolves the standby junction leakage current
`problem.
`Second, in the invention the selected bit line is driven
`positive by the selected memory core FET if it
`is pro,
`grammed with a low threshold voltage. The current from the
`selected core FET supplies the current to charge the bit line
`capacitance. It also supplies the selected memory more sector
`junction leakage current and supplies Charge to compensate
`
`5,812,461
`
`4
`for negative noise voltage capacitively coupled to the bit line
`from the core prcchargc clocks turning olf.
`In the designs described in the parent application refer,
`cnccrl above, the bit line may remain floating at the WC
`voltage level during the cure sensing time,
`it' the selected
`core PET is programmed with a high thShold voltage. 'l‘o
`supply the selected memory core sector junction leakage
`current, and to supply charge to compensate for negative
`noise capacitively coupled to the bit line, a circuit, such as
`[he one shown in FIG. 4 of the parent application is
`necessary.
`is not needed in the invention.
`This type of circuit
`Elimination of this circuit provides a significant improve,
`rttcnt
`in the sensing pertomtancc ol‘ the invention. The
`circuit provides a small pull-up current to the selected bit
`line to compensate for both negative capacitivcly coupled
`noise and core junction leakage to the grounded memory
`substrate. When a selected memory cell switches the bit line
`toward ground, the memory cell ntust also switch the small
`pull-up current to ground. The "bit-low" switching time and
`voltage level is achieved more easily in the invention than in
`prior types of designs for ROMS using this type of circuit.
`Third, a ROM utilizing the invention can operate with a
`VDD supply voltage of 3 volts because the memory core is
`prccharged to ground. Prior designs of ROMS with a
`memory con: prccharged to a low supply voltage, such as
`Vl’C which is about 2 volts. require an operating VDD
`supply voltage more than 1.5 volts greater than VPC [or
`operation of the prechargc clocks, polysilicon word lines,
`and polysilicon sector select Lines in the memory core.
`Fourth, a ROM utilizing the currcnt invention can pro-
`charge the memory core to ground, the prccharge voltage
`lcwl, in significantly less time than required for ROMS with
`the memory core precharged to a low supply voltage, such
`as VPC, which is about 2 volts The current
`invention
`utilizes an NFET with a grounded source for switching the
`memory core virtual ground lines and main bit
`lines to
`ground. This NI-‘Li'l' has the full VDD voltage applied From
`the gate terminal to the source terminal during the entire
`prccharge time. The prior designs utilize an N'FET in a
`source follower configuration for switching the memory
`core virtual ground lines and main bit lines to a low Voltage
`such as VPC. With this cUnllgllraliOn, the voltage applied
`from the gate terminal to the source terminal, which is
`connected to VI’C, decreases during the prcchargc time. This
`increases the required prcchargc tone, and requires an operi
`fitting VIJD supply voltage more than 15 volts greater than
`VPC for minimizing the precharge time to VPC'.
`The invention is an improvement in a memory having a
`memory core with a plurality of memory cells and a predci
`tcrmincd memory core substrate voltage. The mcmory cells
`are accessed at least in part by selection ul‘corresponding bit
`lines and virtual ground lines coupled thereto The improve-
`ment comprises prechargiug circuitry for precharging the
`virtual ground lines and bit lines in the memory core to thc
`memory core substrate voltage. Virtual ground line and bit
`lint: decoder and precharging circuitry prcchargcs previously
`selected virtual ground lines and bit lines in the memory core
`to ground. Virtual ground tine driver circuitry first drives
`both selected virtual ground lines to ground during a pref
`charge phase and then selectively drives one virtual ground
`line to ground and the second virtual ground line to a
`positive voltage level. Memory core junction leakage cur,
`rent [rem the virtual ground lines and bit lines in the memory
`core is reduced to zero when the memory core is prcchargcd
`lo the memory core substrate voltage. The need for an
`internal low voltage supply [or a prcchargc level is elimi-
`
`ZTE/SAMSUNG 1018-0202
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`
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`
`5
`nated. VDD standby current and operating voltage level
`required for the memory is significantly reduced.
`The time required to precharge the memory core to the
`precharged voltage level at the beginning ofa memory read
`cycle is significantly reduced. The precharging circuitry,
`virtual ground line and bit line decoder and precharging
`circuitry, virtual ground linc drivercircuitry and the memory
`core provide the main hit fine with bit-low level and hit-high
`level voltages which are negligibly affected by capacitively
`coupled negative noise voltages or by memory core junction
`leakage currents to the memory cure substrate. ‘lhe pre-
`charging circuitry, vinual ground line and bit line decoder
`and prccharging circuitry, virtual ground linc driver
`circuitry, and the memory Core provide a positive current to
`the main bit line for providing a positive voltage defined as
`a logic zero level or bitihigh level and a precharged zero
`voltage level to the main bit line for a logic one or bit—low
`level.
`The improvement further comprises bit line voltage sens-
`ing circuitry to sense hit-low level and bit-high level volt-
`ages on the main bit line at high speed with a bit—high
`voltage level of at least 150 millivolts and with a bitslow
`level of approximately zero voltsi
`Each memory cell comprises a core 1" "1'. The core [-‘E'fof
`at least one of the memory cells is programmed with a low ,
`threshold voltage defining a logic zero output. The prechargi
`ing circuitry. virtual ground line and bit line decoder and
`precharging circuitry, virtual ground line driver circuitry,
`and the memory core for minimizing total diffusion capaci-
`tance on the virtual ground line coupled to the memory cells
`when the memory cells are programmed with more logic
`zeros than logic ones, and for reducing capacitance associ~
`ated with the core li‘LiT programmed with a low threshold
`voltage due to minimized total diffusion capacitance.
`The virtual ground line and bit line decoder and prccharg-
`ing circuitry prccharges previously selected virtual ground
`lines and bit lines in the memory core to approximately zero
`voltage.
`The invention is also an improvement in a method of
`operation of a memory having a memory core with a
`plurality of memory cells and a predetermined memory core
`
`substrate voltage. The memory cells are accessed at lea
`in
`part by selection of corresponding hit lines and two associ-
`ated virtual ground lines coupled thereto from a plurality of
`bit lines and associated virtual ground lines in the memory.
`The improvement comprises the steps of precharging the
`virtual ground lines and hit lines in the memory cure to the
`memory core substrate voltage. A pair of the virtual ground
`lines is selected in the memory. Both selected virtual ground
`lines are driven to ground during a prechargc phase, One of
`the selected virtual ground line is selectively driven to
`ground and the other one of the selected virtual ground line
`to a positive Voltage level.
`Differential Sense Amplifier
`The parent application shows a similar sense amplifier
`approach using a current mirror instead of a crom coupled
`
`current source. A schematic drawing of this previous
`se
`amplifier is presented in FIG. 21 ot‘ the parent, which is
`reproduced here as FIG. 5, since many of the improvements
`of the invention are best understood in comparison to the
`design in the parent application.
`Both approaches use the same clocking signals and have
`the same timing. Also, bod: approaches amplify voltage
`dilfl'erenccs of about 0.15 volts. The previous design amplii
`fies voltages that are close to 2.0 volts with diflercnces of
`about [US volts. The present design amplifies voltages that
`are close to ground with dilierences of about 0.15 volts. The
`
`5,812,461
`
`6
`use of voltage level shifters, a cross coupled current source
`and invcncrs is unique to the present design.
`The present sense amplifier design amplifies voltage
`differences of signals that are about (L15 volts. The previous
`sense amplifier design amplifies voltage differences of sig-
`nals that are about 210 volLs.
`The idea of using a cross coupled current source instead
`of a current mirror is not limited to the present design. This
`idea will Work equally well in the previous sense amplifier
`and may he used without the voltage level shifting circuitry.
`The current mirror approach used in the previous design
`loads the dill'erential amplifier otttput nodes with an unbal-
`anced capacitive load. This unbalanced load favors one side
`of the latch over the other side of the latch. The cross
`coupled current source approach loads the differential ampli-
`fier with a balanced load.
`It would be possible to add
`capacitance to the previous design to balanced the nodes, but
`extra capacitance would slow the latch and reduce the
`transient response of the latch.
`The voltage level shifters in the present design are impor-
`tant because they allow the ditfercntial amplifier to sense
`signals that are close to ground with a voltage diltercnce of
`about 015 volts. The voltage level shifters also shift the
`signals to a voltage that increases the gain of the differential
`amplifier. In the previous design, the dilTerential amplifier
`was limited to amplifying signals that were at the internal
`precharge voltage of the memory core, i.c. about 2t) volts.
`lly level shifting inputs to the dillerential amplifier from
`Zero volts to about 212 volts, the differences of these level
`shifted signals can now be amplified with a conventional
`differential amplifier.
`It is imponant to note that the use of level shifters is not
`limited to only sense amplifiers. FIG.
`’7 shows a timing
`circuit that employs voltage level shifting circuits and a
`difi‘crential amplifier.
`It
`is very desirable to have a symmetric design in a
`dill'erential amplifier.
`The cross coupled current source approach is symmetric
`while the current mirror approach is noti Because of the
`small difference in voltages being sensed, small imbalances
`in the difi'erential amplifier may have a large enough effect
`to cause the differential amplifier to fall in“) the wrong state.
`The idea of Using symmetry tn imprtwe the balance of the
`sense amplifier extends beyond the design to the layout of
`the design. A symmetric and balanced layout may sense
`smaller voltage dilferences and operate faster than would
`otherwise be possihlei
`The cross coupled current source approach can provide
`more gain than the current mirror approach. The gain of the
`cross coupled current source is controlled by four FETs.
`The present design uses two inverters to block half level
`signals from being outputted until the sense amplifier data
`has been latched.
`l-ly blocking half level outputs of the
`ditfcrential amplifier. a race condition is eliminated and
`output enable signal, OE may switch sooner than would
`otherwise be possible.
`The invention is an improvement in a detection circuit
`having an input signal which is sensed. The improvement
`comprises a level shilling circuit for receiving the input
`signal and for shifting the voltage of the input signal to a
`predetermined level to output a voltage shifted level of the
`input signal. The predetermined level is within an operative
`range of detection of the detection circuit,
`The input signal sensed by the level shifting circuit has a
`voltage close to ground. The detection circuit in the opera-
`tive range is capable of distinguishing signal level differ-
`ences at
`least as small as about 0115 volts so that input
`
`ZTE/SAMSUNG 1018-0203
`
`|PR2018-00274
`
`'41r:
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`u.m
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`00
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`ZTE/SAMSUNG 1018-0203
`IPR2018-00274
`
`

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`m
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`It!
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`signals at least as little as about 0.15 volts above ground are
`reliably sensed.
`The level shitting circuit shifts the voltage of the input
`signal to the predetermined level within a wide range of
`selected voltages including the operative range olithe detec-
`tion circuit. The predetermined level is where the detection
`circuit has the most gain, speed and accuracy.
`The detection circuit comprises a differential amplifier
`having two dilTerential outputs and the detection circuit
`comprises a pair of cross coupled current sources to provide
`matched current sources to the differential amplifier, The
`pair of current sources are symmetric, balanced, have the
`same capaCitive loading and the same impedance. The pair
`of cross coupled current sources initially provide two equal
`current sources, but become unmatched based on the output
`of the dilIerential amplifier. The differential amplifier
`includes circuitry for providing positive feedback from the
`outputs to the pair ofcurrent sources to increase the gain and
`speed of the differential amplifier.
`The pair of current sources have two cross coupled l‘Li'l‘s
`and the gain of the cross coupler] current source is controlled
`primarily by the two cross coupled FETs. A range of gains
`is provided to the ditI'erentia] amplifier by varying the
`width-to-lenglh ratio or the two cross coupled I‘E'l's. The
`
`pair of current sources funher comp i'
`two FL’Ts connected
`in parallel
`to the cross coupled Hills. The gain of the ,
`ditierential amplifier also is further controlled by varying the
`widthitoilength ratio of the two parallel coupled FETs.
`The improvement
`further comprises two inverters to
`block half-level outputs of the dilferential amplitier until
`both outputs of the detection ctreuit have been latched,
`The invention is also an improvement in a method of
`detecting an input signal level the improvement comprising
`[he steps of receiving the input signal, and shifting the
`voltage of the input signal to a voltage shifted output level.
`The voltage shifted output level is within an predetermined
`operative range of detection of a detection circuit. The
`voltage shifted output level
`is detected to distinguish the
`sigma] level of the input signal level.
`Virtual Ground and Bit Line Decoder
`The design described in the eopending application,
`M387—D for the virtual ground and bit line decoder, and the
`present virtual ground and bit line decoder both multiplex a
`selected main bit line. mBLi The previous NMOS ROM
`decoder selects one virtual ground line and drives this line
`to ground.All other virtual ground Lines are preeharged to an
`internal low supply voltage of about 2 volts, The present
`design selects two virtual ground lines These two lines are
`initially driven low. During the read cycle, one of the lines
`is driven high and the other line remains driven low. The
`virtual ground line that is driven high is determined by an
`address, AY[4].
`Like the NMOS decoder described in copendil‘lg applica-
`tion Seri No. ti8,’(l16,fill, entitled Improvements in a Very
`Large Scale Integrated Planar Read Only Memory.
`the
`CMOS virtual ground and bit line decoder multiplexes a
`selected main bit
`line and one virtual ground line. The
`CMOS decoder provides a better precharge than the NMOS
`decoder.
`In the CMOS design, Pal is an input
`to the
`addresses YDLflF'I] and YDU[0—7]. When PCB is high
`during core preeharge, all
`the addresses YDl.[0a7] and
`Yl)U[[L7] are high, all i-‘L-Ts in the decode are turned on,
`and all the virtual ground line and bit lines are precharged.
`This additional preeharging technique is not used in the
`present design although this technique is compatible with
`the present design.
`In Comparison to the prior designs, the improved interlock
`method provides the same function with fewer gates. This
`
`5,812,461
`
`8
`method is inherently faster and uses less silicon die area
`because fewer gates are used.
`In comparison to the previous NMOS ROM patent and
`the CMOS virtual ground and bit line decoder, the present
`decoder is designed for use with a memory core that is
`precltarged to ground. The previous decoder was designed
`for use with a memory core that
`is precharged to a low
`voltage of about 2 volts: in the present design an additional
`decode is done by means of the SELV lines. Because this
`additional decode is done by means of the SELV lines, the
`present decoder uses fewer Hits and less area than would
`otherwise be possible,
`Crowbar currents may be very large in inverters and logic
`gates with large FE' si When CMOS inverters and logic
`gates switch, there is a period of time where both the PMOS
`and the NMOS FETs are partially turned on. The current that
`flows through these FETS is called a “erowbar current".
`Crowbar current is normally not significant but can become
`
`very significant when large [7
`are used. This interlock
`method avoids these crowbar currents
`The invention is an improvement in a method for decod-
`ing a plurality of virtual ground lines and bit lines in a
`memory comprising the steps of driving all vifluat ground
`lines in the memory Core low. Two virtual ground lines in a
`memory core are multiplexed by holding a selected first
`virtual ground line low and keeping a selected second virtual
`ground line low for memory wre discharge, and by driving
`the selected second virtual ground line high for core evalu»
`ation. The core is then read or evaluated All unselected
`virtual ground lines are kept floating during the step of
`evaluating the cure. The second virtual ground line is then
`switched low for memory core discharge in preparation for
`subsequent cure evaluation.
`The improvement further comprising the step of precharg-
`ing a BIT line to ground prior to the step of evaluating the
`core, The BIT line is selectively coupled to the bit lines in
`the memory,
`for producing two
`The invention is also a decoder
`memory multiplexing signals, SELVI] and SELVI, capable
`of driving a large capacitive memory load. The decoder
`comprises decode circuitry for selectively decoding an
`addres.
`'gnal to drive one of the two memory multiplexing
`signals, 5111.th and SliLVl, high and the other low. Drive
`circuitry generates the two memory multiplexing signals,
`SELVO and SELVl, in response to the decode circuitry. The
`drive circuitry is tristated.
`The drive circuitry is comprised of a pair of two large
`l‘E't‘s coupled in series. The memory multiplexing signals,
`SELVtJ and SELVI, are derived respectively from the cou-
`pling between one of the pair of the two large FETs. The
`drive circuitry comprises circuitry for turning each one of
`
`the two large I' TsolI before turning on the other one of the
`[Wit large VETS in each of the pairs of [ill—ls, so that one of
`the FETs ot'eaeh pair will always be off when the other one
`of the pair of FETs is on.
`
`The memory mUIliplexing signalsI SELW] and SL-‘LVI,
`have a voltage level set by a decoder supply voltage, V5131»
`The memory multiplexing signals, SELVO and SLLLV], have
`the highest voltage level in the memory core. Voltage levels
`ot'the memory multiplexing signals. SELW and SELVl. are
`set at a level low enough to avoid memory breakdowns in
`the memory core.
`The invention k4 also an improved method of precharging
`a memory eore having a plurality ofvirtu al ground lines and
`main bit lines comprising the steps of precharging all of the
`virtual ground lines and main bit lines in the memory core
`to ground before the core is read through a precharge block
`
`ZTE/SAMSUNG 1018-0204
`
`|PR2018-00274
`
`mr:
`
`u.m
`
`00
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`ZTE/SAMSUNG 1018-0204
`IPR2018-00274
`
`

`

`5,812,461
`
`9
`’I‘wo selected vinual ground lines are driven to ground
`before the core is read through precharge paths through the
`memory core independent of the precharge block.
`The invention is still further a driver circuit for avoiding
`c