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`PATENT DATE
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`APR 02 MI
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`PTO-2040
`12:99
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`El TERMINAL
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`|PR2018—00274
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`
`ZTE/SAMSUNG 1018-0001
`IPR2018-00274
`
`

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`PATENT APPLICATION
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`CONTENTS
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`ZTE/SAMSUNG 1018-0002
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`IPR2018-00274
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`ZTE/SAMSUNG 1018-0003
`
`|PR2018—00274
`
`ZTE/SAMSUNG 1018-0003
`IPR2018-00274
`
`

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`ZTE/SAMSUNG 1018-0004
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`|PR2018—00274
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`IPR2018-00274
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`

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`ZTE/SAMSUNG 1018-0005
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`IPR2018-00274
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`PATENT APPLICATION SERIAL N0.
`
`
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`US. DEPARTMENT OF COMMERCE
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`PTO-1556
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`ZTE/SAMSUNG 1018-0008
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`
`PETEN'I‘
`
`CIRCUIT FOR PRODUCING LOW-VOLTAGE DIFFERENTIAL SIGNALS
`Atul V. Ghia
`Suresh M. Manon
`
`David P. Schultz
`
`FIELD OF THE INVENTION
`
`This invention relates generally to methods and circuits
`
`for providing high~speed.
`
`low-voltage differential signals.
`
`mean
`The Telecommunications Industry Association LTIAI
`
`published a standard specifying the electrical characteristics
`of low-voltage differential signaling {LVDS}
`interface
`circuits that can be used to interchange binary signals.
`
`LVDS
`
`employs low—voltage differential signals to provide high—
`speed,
`low—power data communication.
`The use of differential
`signals allows for cancellation of common—mode noise, and thus
`enables data transmission with exceptional speed and noise
`
`For a detailed description of this LVDS Standard.
`immunity.
`see “Electrical Characteristics of Low Voltage Differential
`
`Signaling ILVDS} Interface Circuits," TIA/EIA-Sqé {March
`1996}. which is incorporated herein by reference.
`Figure 1
`[prior art) illustrates an LVDS generator 100
`connected to an LVDS receiver 110 via a transmission line 115.
`Generator 100 converts a single—ended digital input signal
`D_IN on a like—named input terminal into a pair of
`complementary LVDS output signals on differential output
`terminals TX_A and TX_B.
`A lUG-ohm termination load RL
`
`separates terminals TX_A and Tx_E. and sets the output
`impedance of generator 100 to the level specified in the
`above-referenced LVDS Standard.
`LVDS receiver 110 accepts the differential input signals
`
`from terminals TX_A and TX_B and converts them to a single—
`ended output signal D_OUT.
`The LVDS Standard specifies the
`
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`ZTE/SAMSUNG 1018-0009
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`|PR2018-00274
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`ZTE/SAMSUNG 1018-0009
`IPR2018-00274
`
`

`

`X-Tfld US
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`PATENT
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`
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`The present application is
`properties of LVDS receiver 110.
`directed to differential—signal generators: a comprehensive
`discussion of receiver 110 is not
`included in the present
`
`application.
`
`Figure 2 {prior art} schematically depicts LVDS generator
`100 of Figure l. Generator 100 includes a preamplifier 200
`connected to a driver stage 205. Preamplifier 200 receives
`
`the single—ended data signal D_IN and produces a pair of
`complementary data signals D and D/ {signal names terminating
`in 'l' are active low signals}. Unless otherwise specified,
`
`each signal is referred to by the corresponding node
`the
`designation depicted in the figures. Thus.
`for example,
`input
`terminal and input signal to generator 100 are both
`designated D_IN. In each instance,
`the interpretation of the
`node designation as either a signal or a physical element is
`clear from the context.
`
`Driver stage 205 includes a PMDS load transistor 20? and
`an NMOS load transistor 209. each of which produces a
`
`relatively stable drive current in response to respective bias
`
`voltages PBIAS and NBIAS. Driver stage 205 additionally
`includes four drive transistors 211. 213, 215, and 217.
`If signal D_IN is a logic one {e.g.. 3.3 volts).
`
`preamplifier 200 produces a logic one on terminal D and a
`logic zero (e.g.. zero volts} on terminal D/.
`The logic one
`on terminal D turns on transistors 211 and 21?, causing
`
`current to flow down through transistors 20? and 211, up
`
`though termination load RL. and down through transistors 21?
`and 209 to ground {see the series of arrows 219). The current
`through termination load RL develops a negative voltage
`between output
`terminals TK_A and TX_B.
`
`Conversely. if signal D_IN is a logic zero, preamplifier
`
`200 produces a logic zero on terminal D and a logic one on
`terminal DE.
`The logic one on terminal DI
`turns on
`
`transistors 213 and 215, causing current to flow dOwn through
`
`ZTE/SAMSUNG 1018-0010
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`|PR2018-00274
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`ZTE/SAMSUNG 1018-0010
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`

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`x-T 84 US
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`PATENT
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`termination load RL,
`transistor 215.
`transistor 207.
`transistor 213, and transistor 209 to ground lsee the series
`of arrows 221}. The current through termination load RL
`
`develops a positive voltage between output terminals Tx_a and
`Tx_B.
`
`Figure 3 {prior art) is a waveform diagram 300 depicting
`the signaling sense of the voltages appearing across
`termination load RL of Figures 1 and 2. LVDS generator 100
`produces a pair of differential output signals on terminals
`TXHA and Tx_B. The LVDS Standard requires that the voltage
`between terminals TX_A and Tx_E remain in the range of 250 mv
`
`to 450 mv. and that the voltage midway between the two
`differential voltages remains at approximately 1.2 volts.
`Terminal TX_A is negative with respect
`to terminal Tx_fl to
`represent a binary one and positive with respect to terminal E
`to represent a binary zero.
`A programmable logic device {PLDJ is a well-known type of
`IC that may be programmed by a user (e.g., a circuit designer)
`to perform specified logic functions. Most PLDs contain some
`type of inputfoutput block (Ion:
`that can be configured either
`
`to receive external signals or to drive signals off chip. One
`type of PLD.
`the field—programmable gate array {FPGA}.
`
`typically includes an array of configurable logic blocks
`{CLBs} that are programmably interconnected to each other and
`
`to the programmable IOBs. Configuration data loaded into
`internal configuration memory cells on the FPGA define the
`operation of the FPGA by determining how the CLBs.
`interconnections, block RAM. and 1035 are configured.
`
`IOBs configured as output circuits typically provide
`
`single—ended logic signals to external devices. As with other
`types of circuits. PLDs would benefit from the performance
`advantages offered by driving external signals using
`differential output signals. There is therefore a need for
`
`loss that can be configured to provide differential output
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`ZTE/SAMSUNG 1018-0011
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`|PR2018-00274
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`ZTE/SAMSUNG 1018-0011
`IPR2018-00274
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`

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`X-Tsfl US
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`signals. There is also a need for LVDS output circuits that
`can be tailored to optimize performance for different loads.
`
`SUMMARY
`
`The present invention addresses the need for
`
`differential—signal output circuits that can be tailored for
`use with different loads.
`In accordance with one embodiment,
`
`to
`one or more driver stages can be added. as necessary,
`provide adequate power for driving a given load. Driver stages
`are added by programming one or more programmable elements,
`such as memory cells,
`fuses, and antifuses.
`A differential driver in accordance with another
`
`embodiment includes a multi—stage delay element connected to a
`number of consecutive driver stages. The delay element
`produces two or more pairs of complementary input signals in
`response to each input-signal transition. each successive
`signal pair being delayed by some amount relative to the
`
`previous signal pair. The pairs of complementary signals are
`conveyed to respective driver stages. so that each driver
`stage successively responds to the input-signal transition.
`The output terminals of the driver stages are connected to one
`another and to the output
`terminals of
`the differential
`
`driver. The differential driver thus responds to each input-
`signal transition with increasingly powerful amplification.
`The progressive amplification produces a corresponding
`progressive reduction in output resistance, which reduces the
`noise normally associated with signal reflection.
`
`Extendable and multi-stage differential amplifiers in
`accordance with the invention can be adapted for use in PLDs.
`In one embodiment. adjacent pairs of IOBs are each provided
`with half of the circuitry required to produce LVDS signals.
`Adjacent pairs of rose can therefore be used either
`
`individually to provide single-ended input or output signals
`or can be combined to produce differential output signals.
`
`4 A
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`ZTE/SAMSUNG 1018-0012
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`|PR2018-00274
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`ZTE/SAMSUNG 1018-0012
`IPR2018-00274
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`

`

`iii-784 US
`
`PATENT
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`This summary does not limit the invention. which is
`instead defined by the appended claims.
`
`BRIEF DESCRIPTION OF THE FIGURES
`
`Figure 1 {prior art} illustrates an LVDS generator 100
`connected to an LVDS receiver 110 via a transmission line 115.
`
`Figure 2 (prior art) schematically depicts LUBE generator
`100 of Figure 1.
`Figure 3 (prior art} is a waveform diagram 300 depicting
`the signaling sense of the voltages appearing across
`termination load RL of Figures 1 and 2.
`
`Figure 4 depicts an extensible differential amplifier 400
`in accordance with an embodiment of the invention.
`
`Figure 5A is a schematic diagram of predriver 405 of
`Figure-4.
`Figure 53 is a schematic diagram of driver 415 of Figure
`
`Figure 5C is a schematic diagram of extended driver 410
`of Figure 4.
`
`Figure 6 depicts a multi—stage driver 600 in accordance
`with another embodiment of the invention.
`
`Figure 7A schematically depicts a predriver 700 in which
`a predriver is connected to delay circuit 505 of Figure 5
`to
`develop three complementary signal pairs.
`Figure 1B schematically depicts differential-amplifier
`
`sequences 610 and 615 and termination load 620. all of Figure
`6.
`
`Figures 8A and SB schematically depict a programmable
`bias-voltage generator 800 in accordance with an embodiment of
`the invention.
`
`DETAILED DESCRIPTION
`
`Figure 4 depicts an extensible differential amplifier duo
`in accordance with an embodiment of the invention. amplifier
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`ZTE/SAMSUNG 1018-0013
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`|PR2018-00274
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`ZTE/SAMSUNG 1018-0013
`IPR2018-00274
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`

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`X—T all US
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`PATENT
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`400 includes a predriver 405 connected to a pair of driver
`
`stages 410 and 415. The combination of predriver 405 and
`driver 415 operates as described above in connection with
`
`to convert the single-ended input on terminal
`Figures 2 and 3
`D_IN into differential output signals on lines Tx_A and TX_E.
`In accordance with the invention. driver 410 can be activated
`as needed to provide additional drive power. In one
`
`embodiment. drivers 410 and 415 reside within a pair of
`
`adjacent programmable IUBs {collectively labeled 417: and
`lines TX_A and TxfiB connect to the respective input/output
`
`(I/O) pads of the pair. This aspect of the invention is
`detailed below.
`
`The program state of a configuration bit 420 determines
`whether amplifier 400 is enabled, and the program state of a
`second configuration bit 425 determines whether the driver
`
`stage of amplifier 400 is extended to include driver 410. An
`
`exemplary configuration bit is described below in connection
`with Figure 8A.
`
`If hit 420 is programmed to provide a logic one on
`“enable differential signaling" line ENFDS,
`then predriver 405
`and driver 415 function in a manner similar to that described
`above in connection With Figure 2. If desired.
`the drive
`
`circuitry can be extended to include driver 410 by programming
`bit 425 to provide a logic one on “extended differential
`
`signaling" line K_DS. The signals on lines x_os and EN_DS are
`logically combined using an AND gate 430 to produce an ~enable
`termination load" signal EN_T to driver 415. This signal and
`
`its purpose are described below in connection with Figure SB.
`Figure SA is a schematic diagram of an embodiment of
`predriver 405 at Figure 4. Predriver 405 includes a pair of
`conventional
`tri—state drivers 500 and 502. A conventional
`inverter 504 provides the complement of signal EN_DS.
`Amplifier 400 is inactive when signals EN_DS and EN_D5I
`are low and high, respectively. These logic levels cause
`
`32
`33
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`d]
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`ZTE/SAMSUNG 1018-0014
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`|PR2018-00274
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`ZTE/SAMSUNG 1018-0014
`IPR2018-00274
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`

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`K— 784 US
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`PATENT
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`tristate drivers 500 and 502 to disconnect input terminal D_IN
`
`from respective tristate output terminals T1 and T2. Signal
`EN_DS and its complementary signal EN_DSX also connect
`terminals T1 and T2 to respective supply voltages VCCO and
`ground by turning on a pair of transistors 505 and 503. Thus.
`terminals T1 and T2 do not change in response to changes on
`
`input terminal D_IN when differential signaling is disabled.
`In the case where amplifier 400 is implemented using 1035 in a
`
`programmable logic device, amplifier 400 may be disabled to
`allow the Ions to perform some other input or output function.
`Amplifier 400 is active when signals EN_DS and EN_DS/ are
`high and low. respectively. These logic levels cause tristate
`drivers 500 and 502 to connect input
`terminal D_IN to
`
`respective tristate output terminals T1 and T2. Signal EN_Ds
`and its complementary signal Eansf also disconnect
`terminals
`T1 and T2 from respective supply voltages VCCO and ground by
`
`terminals T1 and T2
`turning off transistors 505 and 508. Thus,
`change in response to signal D_IN when differential signaling
`is enabled.
`
`Tristate output terminals Tl and T2 connect to the
`respective input terminals of an inverting predriver 510 and a
`non—inverting predriver 512. Predriver 510 includes a pair of
`conventional inverters 514 and 516. Inverter 514 produces a
`
`signal D, an inverted and amplified version of the signal on
`line Tl;
`inverter 515 provides a similar signal to a test pin
`518. Predriver 512 includes three conventional inverters 520,
`
`522. and 52s. Predriver 512 produces a signal DI.
`
`the
`
`complement of signal D. Inverter 524 provides a similar signal
`to a test pin 526.
`
`Each inverter within predrivers 510 and 512 is a CMOS
`inverter in which the ratios of the PMOS and NMDS transistors
`
`are as specified. These particular ratios were selected so
`that signals D and D/ transition simultaneously. or very
`nearly so. Different ratios may be appropriate, depending upon
`
`7
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`L.
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`ZTE/SAMSUNG 1018-0015
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`|PR2018-00274
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`ZTE/SAMSUNG 1018-0015
`IPR2018-00274
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`

`

`X—‘i’ 34 US
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`PATENT
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`the process used to produce amplifier 400. Adjusting layout
`and process parameters to produce synchronized complementary
`signals is within the skill of those in the art.
`As discussed above in connection with Figure 4. amplifier
`400 can be extended to include additional drive circuitry.
`
`which may be needed to drive some loads while remaining in
`
`compliance with the LVDS Standard. Returning to Figure 5A, a
`pair of NOR gates 528 and 530 facilitates this extension by
`producing a pair of complimentary extended—data signals DX and
`DX/ when signal x_osi is a logic zero.
`indicating the extended
`driver is enabled. Extended—data signal Dx is substantially
`
`the same as signal D, and extended data signal ex; is
`substantially the same as signal DI. Signals DX and ox: are
`
`the operation of which is
`conveyed to extended driver 410;
`detailed below in connection with Figure 5C.
`
`Figure SB is a schematic diagram of driver 415 of Figure
`4. Driver 415 is similar to driver stage 205 of Figure 2.
`like—numbered elements being the same. Unlike driver 205,
`
`however, driver 415 includes a programmable termination load
`
`540. Further,
`
`load transistors 20? and 209 of Figure 2 are
`
`replaced with pairs of parallel transistors, so that
`transistors 211 and 215 connect to VCCO via respective PMOS
`transistor 532 and 533.
`instead of via a single transistor
`
`20?. and transistors 213 and 217 connect to ground via
`respective NMUS transistors 534 and 535r
`instead of via a
`single transistor 209.
`Employing pairs of load transistors allows driver 415 to
`be separated into two similar parts 535 and 538. each
`associated with a respective one of terminals TK_A and TX_B.
`
`for example. when driver
`Such a configuration is convenient,
`415 is implemented on a PLD in which terminals Tx_A and TX_B
`connect
`to neighboring 110 pins. Each part 536 and 535 can be
`
`implemented as a portion of the 103 {not shown} associated
`with the respective one of terminals Tx_A and Tx_e.
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`ZTE/SAMSUNG 1018-0016
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`|PR2018-00274
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`ZTE/SAMSUNG 1018-0016
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`

`

`3-784 US
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`PATENT
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`Termination load 540 can be part of either 103, neither Ioa.
`
`transistor
`or can be split between the two. In one embodiment.
`542 is included in the 103 that includes part 536, and
`transistor 543 is included in_the 103 that includes part 5331
`
`Programmable termination load 540 includes a pair of
`transistors 542 and 543,
`the gates of which connect
`to
`
`the signal EN_T is
`terminal EN_T. As shown in Figure 4,
`controlled through AND gate 430 by configuration hits 420 and
`425. Termination load 540 is active {conducting} only when
`
`differential signaling is enabled in the non-extended mode.
`This condition is specified when configuration bit 420 is set
`
`to a logic one and configuration bit 425 is set to a logic
`zero.
`
`Driver 415 includes a number of terminals that provide
`
`appropriate bias voltages. Terminals Pains and NBIAS provide
`respective bias levels establish the gain driver 415. and
`common terminals PCOM and NCOM conventionally establish the
`
`high and low voltage levels on output terminals TXwA and Tx_B.
`Driver 415 shares the bias and common terminals with extended
`
`driver 410 (gee Figure SCI.
`The bias levels PBIAS and NBIAS are important
`
`in defining
`
`In one embodiment. NMOS transistors 534
`LVDS signal quality.
`and 535 are biased to operate in saturation to sink a
`
`relatively stable current. whereas PMOS transistors 532 and
`533 are biased to operate in a linear region. Operating
`transistors 532 and 533 in a linear region reduces-e???—fluw~
`
`smeeeeee the output resistances of those devices, and the
`reduced resistance tends to dissipate signal reflections
`
`returning to terminals Tx_a and TX_E. Reduced reflections
`translate into reduced noise. and reduced noise allows signals
`to be conveyed at higher data rates. Circuits for developing
`appropriate bias levels for the circuits of Figures 5A-7E are
`discussed below in connection with Figures 8A and SB.
`
`Figure 5C is a schematic diagram of one embodiment of
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`ZTE/SAMSUNG 1018-0017
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`|PR2018-00274
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`ZTE/SAMSUNG 1018-0017
`IPR2018-00274
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`

`

`X—784 85
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`PATENT
`
`extended driver 410 of Figure 4. Extended driver 410 includes
`
`a pair of driver stages 544 and 546 and a programmable
`termination load 548. Driver stages 544 and 545 can be
`included,
`for example,
`in respective adjacent 1035 on a PLD.
`Termination lead 548 can be part of either 10B. neither IOB.
`or can be split between the two. The various terminals of
`
`Figure 5C are connected to like~named terminals of Figures SA
`and 53.
`
`Driver stage 544 includes a PMOS load transistor 550, a
`pair of NMDS ditferential-driver transistors 552 and SSé
`
`having their gates connected to respective extended—driver
`input signals ox and DXI. a diode-connected PMOS transistor
`555. and a PMOS transistor 558 connected as a capacitor
`between terminal VCCO and terminal PCOM. Transistors 550, 552.
`
`and 554 combined amplify the extendedrdriver signals DX and
`
`to produce an amplified output signal on output terminal
`DX/
`TX_A.
`In one embodiment,
`transistor 555 is diode-connected
`
`between terminals PCOM and VCCO to establish the appropriate
`level for line PCOM. which is common to both drivers 410 and
`415. Finally,
`transistor 558 can be sized or eliminated as
`desired to minimize noise on line Peon.
`
`Driver stage 546 is identical to driver stage 544, except
`that lines Dx and ox! are connected to the opposite
`differential driver transistors. Consequently,
`the signals on
`
`output terminals TX_A and TX_E are complementary. Driver
`stages 544 and 546 thus supplement the drive strength provided
`by driver stage 415.
`
`the extend-differential-signaling
`As shown in Figure 4,
`signal X_DS is a logic one when CBIT 425 is programmed.
`However, programming CBIT 425 causes AND gate 430 to output a
`logic zero. disabling termination load 532 of Figure SB. Thus,
`
`programming CBIT 425 substitutes termination load 543 for
`termination load 532.
`thereby increasing the termination load
`resistance to an appropriate level. In one embodiment.
`the
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`ZTE/SAMSUNG 1018-0018
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`|PR2018-00274
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`ZTE/SAMSUNG 1018-0018
`IPR2018-00274
`
`

`

`X- 7" 3 II US
`
`PATENT
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`resistance of termination lead 532 is selected so that the
`
`resulting output signal conforms to the DVDS Standard.
`Figure 6 depicts a multi—stage driver 600 in accordance
`with another embodiment of the invention. Driver 600 includes
`
`a multi—stage delay circuit 505. a first sequence of
`differential amplifiers 610. a second sequence of differential
`
`amplifiers 515. and a termination load 620. For illustrative
`
`the amplifiers of sequences 610 and 615 are referred
`purposes.
`to as "high-side" and "low-side" amplifiers, respectively.
`In
`different embodiments, each amplifier sequence 610 and 6l5 can
`
`be implemented as a portion of the 103 [not shown} associated
`with the respective one of terminals TXFA and Tx_B.
`Termination load 620 can be part of either 103, neither IDB,
`
`or can be split between the two.
`
`Delay circuit 505 receives a pair of complementary
`
`signals D and D! on a like—named pair of input terminals. A
`sequence of delay elements -F conventional buffers 525 in the
`depicted example —— provides a first pair of delayed
`complementary signals D1 and D1} and a second pair of del