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`UNITED STATES PATENT AND TRADEMARK OFFICE
`________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`________________
`
`INTEL CORPORATION, and CAVIUM, INC.,
`
`Petitioners,
`
`v.
`
`ALACRITECH INC.,
`
`Patent Owner
`________________
`
`Case IPR2018-002341
`U.S. Patent 8,805,948
`________________
`
`PATENT OWNER’S RESPONSE
`PURSUANT TO 37 C.F.R. § 42.120
`
`
`
`
`
`
`
`
`1 Cavium filed a Petition in Case IPR2018-00403 and has been joined as a
`
`petitioner in this proceeding.
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`

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`I.
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`II.
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` Case No. IPR2018-00234
`U.S. Patent No. 8,805,948
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`TABLE OF CONTENTS
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`Page
`
`INTRODUCTION .................................................................................1
`
`BACKGROUND OF THE TECHNOLOGY .......................................1
`
`III. OVERVIEW OF THE ’948 PATENT ..................................................7
`
`A.
`
`B.
`
`The ’948 Patent Specification .....................................................7
`
`The ’948 Patent Claims ............................................................ 11
`
`IV. PROSECUTION HISTORY OF THE ’948 PATENT ...................... 11
`
`V. OVERVIEW OF THE ASSERTED PRIOR ART ............................. 12
`
`A.
`
`B.
`
`C.
`
`Thia, A Reduced Operation Protocol Engine (ROPE) for
`a Multiple-layer Bypass Architecture (“Thia”) ........................ 12
`
`Tanenbaum, Computer Networks, 3rd ed. (1996)
`(“Tanenbaum”) ......................................................................... 18
`
`Stevens, TCP/IP Illustrated Volume 2: The
`Implementation (“Stevens”) (Ex. 1063) ................................... 21
`
`VI. CLAIM CONSTRUCTION ............................................................... 22
`
`VII. LEVEL OF ORDINARY SKILL IN THE ART ................................ 23
`
`VIII. THE CITED REFERENCES DO NOT RENDER THE
`CHALLENGED CLAIMS OBVIOUS .............................................. 23
`
`A.
`
`B.
`
`C.
`
`The Combination Does Not Show or Suggest “checking,
`by the network interface, whether the packets have
`certain exception conditions, including checking whether
`the packets are IP fragmented” (claim 1) / “the network
`interface adapted to parse the headers of received packets
`. . . to check whether the packets have certain exception
`conditions, including whether the packets are IP
`fragmented” (claim 17) ............................................................ 24
`
`The Combination Does Not Show or Suggest Packet
`Processing for the “Checking” Limitations. ............................ 31
`
`The Combination Does Not Show or Suggest “if the first
`packet has any of the exception conditions, then protocol
`processing the first TCP header by the protocol
`processing stack; [and] if the second packet has any of
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`U.S. Patent No. 8,805,948
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`D.
`
`the exception conditions, then protocol processing the
`second TCP header by the protocol processing stack”
`(claim 1) / “the network interface having logic that
`directs any of the received packets that have the
`exception conditions to the protocol stack for processing”
`(claim 17) ................................................................................. 38
`
`The Combination Does Not Show or Suggest “if the
`packets do not have any of the exception conditions, then
`bypassing host protocol processing of the TCP headers
`and storing the first payload data and the second payload
`data together in a buffer of the host computer, such that
`the payload data is stored in the buffer in order and
`without any TCP header stored between the first payload
`data and the second payload data” (claim 1) / “the
`network interface having logic that . . . directs the
`received packets that do not have any of the exception
`conditions to have their headers removed and their
`payload data stored together in a buffer of the host
`computer, such that the payload data is stored in the
`buffer in order and without any TCP header stored
`between the payload data that came from different
`packets of the received packets” (claim 17) ............................ 39
`
`E.
`
`There is No Motivation To Combine Thia with
`Tanenbaum or Stevens ............................................................. 42
`
`1.
`
`2.
`
`There is No Motivation To Combine Thia with
`Tanenbaum ..................................................................... 43
`There is No Motivation To Combine Thia with
`Tanenbaum or Stevens ................................................... 49
`
`IX. THE STRONG EVIDENCE OF SECONDARY
`CONSIDERATIONS WEIGHS AGAINST OBVIOUSNESS ......... 50
`
`1.
`
`2.
`
`3.
`
`The Claimed Invention Addresses a Long-felt, Yet
`Unresolved Need in the Art for Accelerated
`Network Communications ............................................. 50
`The Claimed Inventions Were Commercially
`Successful ...................................................................... 52
`The Claimed Invention Received Praise in the
`Industry .......................................................................... 53
`
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`U.S. Patent No. 8,805,948
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`4. Many Others Tried and Failed to Develop the
`Claimed Technology ...................................................... 54
`Experts Were Skeptical of the Claimed Invention
`and Taught Away From It .............................................. 55
`
`5.
`
`X.
`
`THE BOARD SHOULD DENY THE PETITION BECAUSE
`IT IS TIME BARRED 35 U.S.C. § 315(B) AND RECENT
`PRECEDENT ..................................................................................... 57
`
`A.
`
`B.
`
`C.
`
`D.
`
`E.
`
`F.
`
`G.
`
`Procedural Background ............................................................ 60
`
`Burden of Proof ........................................................................ 65
`
`Dell, CenturyLink, and Wistron Benefit From the IPR
`and Are Real Parties in Interest ................................................ 65
`
`The Established Relationships Among Intel, Dell,
`CenturyLink, and Wistron Justify the Finding of Real
`Parties-in-Interest ..................................................................... 67
`
`Finding Dell, CenturyLink, and Wistron Are Real
`Parties-in-Interest Is Consistent with Legislative Intent .......... 70
`
`Patent Owner Is Not Able to Amend Claims Due to
`Petitioner’s Late Filing ............................................................. 72
`
`Intel’s and Cavium’s Independent Interest Is Not a
`Defense ..................................................................................... 72
`
`XI. CONCLUSION .................................................................................. 74
`
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`U.S. Patent No. 8,805,948
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`TABLE OF AUTHORITIES
`
`Page
`
`Cases
`
`Applications in Internet Time, LLC v. RPX Corp.,
`897 F.3d 1336 (Fed. Cir. 2018) ............................. 59, 62, 64, 67, 70, 72, 73
`Beckman Instruments v. LKB Produkter AB,
`892 F.2d 1547 (Fed. Cir. 1989) ................................................................. 13
`In re CSB-System International, Inc.,
`832 F.3d 1335 ............................................................................................ 71
`Wi-Fi One, LLC v. Broadcom Corp.,
`878 F.3d 1364 (Fed. Cir. 2018) ........................................................... 57, 59
`Worlds Inc. v. Bungie, Inc.,
`Case. Nos. 2017-1481, -- F.3d -- (Fed. Cir. Sept. 7, 2018) ....................... 59
`
`Statutory Authorities
`
`35 U.S.C. § 312(a)(2) .................................................................................... 59
`35 U.S.C. § 315(b) ........................................................... 57, 59, 63, 64, 71-73
`Fed. R. Civ. P. 24 .............................................................................. 60, 65, 66
`
`Rules and Regulations
`
`37 C.F.R. §§ 42.22, 42.23, and 42.120 ......................................................... 73
`37 CFR §§ 42.8(b)(1), 42.104(a) .................................................................. 59
`
`Other Authorities
`
`H.R. Rep. No. 112–98, at 48 (2011) ............................................................. 69
`Office Patent Trial Practice Guide, 77 Fed. Reg. 48,756, 48,759
`(Aug. 14, 2012).................................................................................... 59, 70
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`U.S. Patent No. 8,805,948
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`PATENT OWNER’S LIST OF EXHIBITS
`
`Ex. 2026
`
`Declaration of Kevin Almeroth, Ph.D. in Support of
`Patent Owner’s Response to the Petition
`
`Ex. 2027
`
`Curriculum Vitae of Kevin Almeroth, Ph.D.
`
`Ex. 2031
`
`The Architecture of a Gb/s Multimedia Protocol Adapter
`
`Ex. 2032
`
`A Fast Track Architecture for UDP/IP and TCP/IP
`
`Ex. 2033
`
`A Communication Architecture for High-speed
`Networking
`
`Ex. 2034
`
`Server Network Scalability and TCP Offload
`
`Ex. 2035
`
`Alacritech and NetXen Join Forces to Deliver Solutions
`for Microsoft TCP Chimney Offload Technology
`
`Ex. 2036
`
`QLogic Licenses Alacritech
`
`Ex. 2037
`
`Neterion Licenses Alacritech’s Patents
`
`Ex. 2038
`
`Alacritech Licenses (Confidential)
`
`Ex. 2039
`
`Ex. 2040
`
`An Evaluation of an Attempt at Offloading TCP/IP
`Protocol Processing onto an i960RN-based iNIC
`
`Alacritech, Pioneer In Network Acceleration, Unveils
`Appliance To Alleviate Enterprise Storage Woes
`
`Ex. 2041
`
`TCP offload is a dumb idea whose time has come
`
`Ex. 2042
`
`TCP/IP Headers (https://nmap.org/book/tcpip-ref.html)
`
`Ex. 2043
`
`TCP/IP message processing
`(http://www.thegeekstuff.com/2011/11/tcp-ip-
`fundamentals/)
`
`Ex. 2051
`
`Intel’s Motion to Intervene Dell
`
`Ex. 2052
`
`Intel’s Motion to Intervene CenturyLink
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`U.S. Patent No. 8,805,948
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`Ex. 2053
`
`Intel’s Motion to Intervene Wistron
`
`Ex. 2054
`
`Kyriacou Declaration
`
`Ex. 2055
`
`Cavium Motion to Intervene Dell
`
`Ex. 2056
`
`Belli Declaration
`
`Ex. 2057
`
`Petition History
`
`Ex. 2058
`
`Alacritech v. Dell docket
`
`Ex. 2059
`
`Alacritech v. Wistron docket
`
`Ex. 2060
`
`Alacritech v. CenturyLink docket
`
`Ex. 2300
`
`Horst Paper
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`I.
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`INTRODUCTION
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`U.S. Patent No. 8,805,948
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`Patent Owner Alacritech Inc. respectfully submits this Patent Owner
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`Response. Petitioners Intel Corporation and Cavium, Inc. (“Petitioners”) filed
`
`respective Petitions for Inter Partes Review (“Petition”) of claims 1, 3, 6-8, 17, 19,
`
`21, and 22 of U.S. Patent No. 8,805,948 (“the ’948 Patent”), and the Board
`
`instituted proceedings (Paper No. 7, “Institution Decision”) on June 5, 2018.
`
`The challenged claims are not obvious over the combined disclosures of
`
`Thia, Tanenbaum, and Stevens relied upon in Ground 1 because: (1) the references,
`
`alone or in combination, fail to disclose all the limitations recited in the challenged
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`claims; and (2) there would have been no motivation to combine the references
`
`with any expectation of arriving at the claimed subject matter, as well as the
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`evidence of secondary considerations of non-obviousness.
`
`II. BACKGROUND OF THE TECHNOLOGY
`
`Both in 1997 and today, sending and receiving information over the Internet
`
`involves the use of many different protocols that set out the rules for how devices
`
`on the Internet can communicate with one another. (Ex. 2026, ¶ 54.) Multiple
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`conceptual models exist for characterizing the interactions between these protocols
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`in the context of the Internet and other telecommunication or computing systems.
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`The Open Systems Interconnection model (or “OSI model”) is one well known
`
`example, describing a seven layer stack where a particular layer serves the layer
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`above it and is served by the layers below it. The seven layers of the OSI model
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`are:
`
`Layer 7: Application Layer
`
`Layer 6: Presentation Layer
`
`Layer 5: Session Layer
`
`Layer 4: Transport Layer
`
`Layer 3: Network Layer
`
`Layer 2: Data Link Layer
`
`Layer 1: Physical Layer
`
`with layer 1 (the Physical Layer) being the lowest layer in the model. (Id.)
`
`The Internet Protocol (or “IP”) is an example of a well-known network
`
`(layer 3) protocol. (Id., ¶ 56.) IPv4 was published as RFC 760 in January 1980
`
`while its successor IPv6 was published as RFC 2460 in December 1998. The IP
`
`protocol describes a set of rules for dividing a message into multiple parts (called
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`“IP packets”) and then transmitting those packets from an IP sender to an IP
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`destination across multiple routers or other links in a computer network. Each
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`packet of information includes an IP address for its destination, analogous to
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`sending a letter through the mail by placing the letter inside an envelope that has
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`the recipient’s postal address printed on it. The format of an IP header is depicted
`
`below:
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`(Ex. 2042; Ex. 2026, ¶ 57.)
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`
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`The Transmission Control Protocol, referred to as “TCP,” is one of the main
`
`protocols used to send and receive information over the Internet. TCP is well
`
`known in the computer networking industry—one early TCP rule set was
`
`published as a Request for Comment (or “RFC”) by the Internet Engineering Task
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`Force (“IETF”) in September 1981 (RFC 793). That rule set was based on an even
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`earlier rule set published in December 1974 as RFC 675. TCP is an example of a
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`transport (layer 4) protocol in the OSI model. TCP is responsible for adding
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`reliability and ordering to the stream of network information—for example, the
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`packets of information sent using IP as the network-layer protocol may not arrive
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`at the destination in the same order intended by the sender of the message. (Ex.
`
`2026, ¶¶ 58-60.) TCP sets rules for breaking up and transmitting the message so
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`that the recipient is able to reliably receive and reassemble the message. Another
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`common analogy from the physical world is the example of sending a multi-page
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`letter through the mail by separately numbering each page and mailing it in its own
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`envelope. IP, like the postal service, will route the envelope-like packets to the
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`destination, but TCP (like the numbering of the individual pages) sets the rules to
`
`allow the recipient to verify that all the pages have been received and to
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`reassemble the pages in the right order. (Id.)
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`
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`TCP describes, for example, how two devices on the Internet may establish a
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`connection over which TCP data packets may be communicated between them. By
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`way of a negotiation process known as a three-way handshake, such a connection
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`can be established between two nodes, and once that connection establishment
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`phase completes, data transfer can begin. Typically, a TCP connection is managed
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`by a device operating system so that applications such as a web browser or a web
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`server like a CDN caching server can pass data to the operating system’s TCP
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`protocol “stack,” and the operating system will manage transmission of that data to
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`the receiver and will pass received data from the other device up to the application
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`layer. The format of a TCP header is depicted below:
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`(Ex. 2042; Ex. 2026, ¶¶ 61-62.)
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`
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`Transmitting a message requires processing each layer in that protocol stack
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`sequentially so that the message can then be transmitted over the data medium.
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`The receiving computer is also required to process those same layers in reverse
`
`until the message is handed off to the appropriate program (e.g., a web server).
`
`One example of processing a message using TCP/IP is depicted below:
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`(Ex. 2043; Ex. 2026, ¶ 63.)
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`
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`Much of this processing is typically handled by the CPU. Thus, sending and
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`receiving data over a network can negatively impact the CPU’s ability to perform
`
`other functions, particularly as the volume of data sent or received increases. For
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`the purposes of this case, the manner by which the CPU handles the required
`
`protocol processing—i.e., the specific software steps it takes to perform the needed
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`TCP and IP processing—is immaterial. At most, it is sufficient that the CPU does
`
`perform or is capable of performing that processing, whether through software
`
`included as part of the operating system or through some other means. (Ex. 2026,
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`¶¶ 64-69.)
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`III. OVERVIEW OF THE ’948 PATENT
`
`A. The ’948 Patent Specification
`
`The ’948 patent describes a novel system for accelerating network
`
`processing. An intelligent network interface card (INIC) of a communication
`
`processing device (CPD) works with a host computer for data communication.
`
`(Ex. 1001 at Abstract.) The INIC provides “a fast-path that avoids host protocol
`
`processing for most large multipacket messages, greatly accelerating data
`
`communication.” (Id.)
`
`As explained in the ’948 patent, when a conventional network interface card
`
`prepares to send data from a first host to a second host, “some control data is added
`
`at each layer of the first host regarding the protocol of that layer, the control data
`
`being indistinguishable from the original (payload) data for all lower layers of that
`
`host.” (Id. at 2:39-42.) This process of adding a layer header to the data from the
`
`preceding layer is sometimes referred to as “encapsulation” because the data and
`
`layer header is treated as the data for the immediately following layer, which, in
`
`turn, adds its own layer header to the data from the preceding layer. (Ex. 2026, ¶¶
`
`72-73.) Each layer is generally not aware of which portion of the data from the
`
`preceding layer is the preceding layer header of user data; as such, each layer treats
`
`the data it receives from the preceding layer as some generic payload. (Id.)
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`(Ex. 1008.034, Figure 1.7 (adapted from Petition at 27).)
`
`On the receiving side, the receiving host generally performs the reverse of
`
`the sending process, beginning with receiving the bit packets from the network.
`
`(Ex. 1001 at 2:58-60.) Headers are removed, one at a time, and the received data is
`
`processed, in order, from the lowest (physical) layer to the highest (application)
`
`layer before transmission to a destination within the receiving host (e.g., to the
`
`operating system space where the received data may be used by an application
`
`running on the receiving host). (Id. at 2:60-63.) Each layer of the receiving host
`
`recognizes and manipulates only the headers associated with that layer, since to
`
`that layer the higher layer header data is included with and indistinguishable from
`
`the payload data. (Id. at 2:63-66.) “Multiple interrupts, valuable central
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`processing unit (CPU) processing time and repeated data copies may also be
`
`necessary for the receiving host to place the data in an appropriate form at its
`
`intended destination.” (Id. at 2:66-3:3.)
`
`The host CPU processes the data by constructing (transmit side) or
`
`destructing (receive side) the packet. The host CPU must be interrupted at least
`
`one time per layer and, in response, the host CPU processes each layer, which
`
`typically involves a copy and data manipulation operation (for example a
`
`checksum computation operation). (Ex. 2026, ¶ 74.) An interrupt is a signal to the
`
`processor emitted by hardware or software indicating an event that needs
`
`immediate attention. (Id.) When the host CPU is interrupted, it generally must stop
`
`all other tasks it is currently working on, including tasks unrelated to the network
`
`processing. (Id.) Frequent interrupts to the host CPU can be very disruptive to the
`
`host system generally and cause system instability and degraded system
`
`performance. (Id.)
`
`The invention of the ’948 patent includes a “fast-path” where the host CPU
`
`is relived of certain TCP/IP processing, which is instead performed by the INIC.
`
`The fast-path “bypasses conventional protocol processing of headers that
`
`accompany the data” and “employs a specialized microprocessor designed for
`
`processing network communication, avoiding
`
`the delays and pitfalls of
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`conventional software layer processing, such as repeated copying and interrupts to
`
`the CPU.” (Ex. 1001 at 3:57-62.)
`
`The fast-path is shown in Figure 6 of the ’948 patent (reproduced below). In
`
`this embodiment, the INIC performs at least the IP and TCP layer processing,
`
`freeing up the CPU on the host (“client”) computer to do other tasks. The fast-path
`
`also reduces or eliminates the number of interrupts sent to the CPU on the
`
`host/client. The more traditional “slow-path” is also shown, where the host/client
`
`is responsible for the IP and TCP layer processing. In the slow-path, the CPU on
`
`the host/client is interrupted at least one time for each layer for processing.
`
`
`
`Advantageously, the claimed invention allows for more efficient network
`
`processing by relieving the host CPU of per-frame processing and reducing the
`
`number of interrupts as only one interrupt occurs at the beginning and end of an
`
`entire upper-layer message transaction for fast-path communications. (Id. at 9:1-
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`10.) As discussed above, the claimed arrangement allows for enhanced network
`
`and system performance, a stark reduction or elimination of unnecessary
`
`processing by the host CPU, faster data throughput, increased system stability, and
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`an overall better user experience. (Ex. 2026, ¶ 78.)
`
`B.
`
`The ’948 Patent Claims
`
`The ’948 patent includes twenty two claims. The Petition challenged claims
`
`1, 3, 6-8, 17, 19, 21, and 22, of which claims 1 and 17 are independent.
`
`IV. PROSECUTION HISTORY OF THE ’948 PATENT
`
`The ’948 patent issued on August 12, 2014. It was filed on September 26,
`
`2013 as Application No. 14/038,297, which was a continuation of Application No.
`
`09/692,561, filed October 18, 2000, which was a continuation of Application No.
`
`09/067,544, filed April 27, 1998, which claims the benefit of Provisional
`
`Application No. 60/061,809, filed on October 14, 1997.
`
`The ’948 patent was subject to a thorough examination. In connection with
`
`the allowed claims, the Examiner stated:
`
`None of the prior art of record taken singularly or in
`
`combination teaches or suggests a network interface of a
`
`host computer for checking whether received packets
`
`have a certain exception conditions, including whether
`
`the packets are IP fragmented, have a FIN flag set, or
`
`out of order; processing any of the received packet that
`
`have the exception conditions, and storing payload data
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`of the received packets that do not have any of the
`
`exception conditions in a buffer of the host computer
`
`and without any TCP header stored between the
`
`payload data of the received packets.
`
`(Ex. 1002.117 (emphasis added).) An Issue Notification was mailed on July 23,
`
`2014.
`
`V. OVERVIEW OF THE ASSERTED PRIOR ART
`
`The Petition relies on the Thia, Tanenbaum, and Stevens references. The
`
`following sections summarize these references and underscore their respective
`
`shortcomings with respect to the challenged claims.
`
`A. Thia, A Reduced Operation Protocol Engine (ROPE) for a Multiple-
`layer Bypass Architecture (“Thia”)
`
`Thia is an academic article theorizing a potential processor architecture for
`
`“bypassing” protocol processing functions within certain layers in the OSI model,
`
`and describes itself as a “feasibility study for a new approach to hardware
`
`assistance.” (Ex. 1015.002.) Notably, Thia explicitly declined to create a real-
`
`world device, noting that the “final step of generating a chip layout for
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`fabrication and fault analysis was not performed.” (Ex. 1015.008 (emphasis
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`added).) Thus Thia presents a feasibility study on the theoretical benefits of
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`bypassing certain layers in the OSI model. (Id. at .013: “It can be concluded from
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`this study that it is feasible to implement the bypass stack (at least for the transport
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`and session layers) in VLSI and that the performance would be at least an order of
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`magnitude higher than software protocol processing.”)
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`Accordingly, Thia discloses (at best) an inoperative device, and is a non-
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`enabling reference. (Ex. 2026, ¶¶ 84-86, 90.) While a non-enabling reference is
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`prior art under § 103(a) “for all that it teaches,” Beckman Instruments v. LKB
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`Produkter AB, 892 F.2d 1547, 1551 (Fed. Cir. 1989), Thia fails to teach much of
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`the subject matter of the challenged claims. Thia’s feasibility study describes—at
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`a high level—the idea of offloading presentation, session and transport layer
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`processing to a Reduced Operation Protocol Engine (“ROPE”) chip, but does not
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`disclose many of the implementation details that would be required to enable the
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`implementation. (Ex. 2026, ¶¶ 84-86, 90.)
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`Thia describes a bypass stack on the ROPE chip that provides a hardware
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`“fast path” for bulk data transfer. (Ex. 1015.002-003.) Thia’s disclosure of the
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`bypass architecture of the ROPE chip consists of the bare flowcharts shown below,
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`which lack many of the implementation details necessary for one of ordinary skill
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`to implement the device (Ex. 2026, ¶¶ 84-86, 90):
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`(Ex. 1015.003.)
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`Thia discloses that its proposed bypass architecture is applicable to both the
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`transmission and reception of packets at a host computer system. With respect to
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`reception of packets, which Thia refers to as “Protocol Data Units” or “PDUs,”
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`Thia discloses that the bypass architecture performs a “receive bypass test” (“RX
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`Bypass Test” in Fig. 1, above) to determine whether certain processing of the
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`received PDU may be performed by the ROPE chip instead of the Standard
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`Protocol Stack (or “SPS”) of the host computer system. (Ex. 2026, ¶ 87.) For
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`example, Thia theorizes that certain procedures performed in the presentation,
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`session, and transport layers for protocols conforming to the OSI model may be
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`performed by the ROPE bypass chip as opposed to the host. (Id., ¶ 88.) These
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`procedures are identified in Table 1 of Thia and include such procedures as header
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`decoding and checking checksums, among others:
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`(Ex. 1015.006 (“Table 1 identifies procedures which are strong candidates for
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`implementation in the bypass chip, and those which are better handled by the host,
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`during the data transfer phase.”).)
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`When a PDU is received, Thia determines whether the ROPE chip may
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`perform any of the bypassable functions for that PDU by executing the “receive
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`bypass test.” According to Thia, the receive bypass test matches the headers of the
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`incoming PDU with a template using header prediction:
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`(Ex. 1015.003 (adapted from Petition at 72).) However, Thia does not address or
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`disclose how the bypass test is implemented, what values of the incoming headers
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`must match the template in order to identify predicted bypassable headers, or what
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`the template even is. (Ex. 2026, ¶ 90.)
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`If the received PDU is a “bypassable” PDU, then certain operations may be
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`performed by the bypass stack on the separate ROPE chip, as opposed to the
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`standard protocol stack on the host (as explained above). (Ex. 2026, ¶ 91; see also
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`Ex. 1015.003, .013-.014.)
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`Once the relevant bypassable operations have been performed by the ROPE
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`chip, the PDU is copied to the host for further processing, such as reassembly into
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`a larger data block. (Ex. 1015.007 (“Movement of data across the host bus
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`interface are minimized by using an on-chip DMA for fast block data transfer
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`to/from the host system memory”), .009.) Thia’s bypass chip performs some of the
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`protocol processing functions (such as validating checksums, decoding headers,
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`etc.) but then provides the PDU to the host for reassembly into a larger data block.
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`(Ex. 2026, ¶¶ 92-93.)
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`Additionally, Thia specifically discloses that it is directed to “the design of a
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`ROPE chip for the OSI Session and Transport layer protocols.” (Ex. 1015.001
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`(emphasis added).) Thus, Thia is not directed to Internet Protocol, or TCP/IP,
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`which does not fit the OSI model. (Ex. 2026, ¶¶ 94-95; Ex. 1006.054.) Indeed,
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`Table 1 of Thia references OSI’s Presentation and Session layers, which do not
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`exist in TCP/IP, and nowhere identifies layers specific to the TCP/IP protocol.
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`(Ex. 2026, ¶¶ 94-95; Ex. 1006.054.) Moreover, Thia’s Figure 2 suggests that its
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`NIA is an “FDDI or ATM” device, which refers to Fiber Distributed Data Interface
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`and Asynchronous Transfer Mode, respectively. Neither FDDI nor ATM utilizes
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`the TCP/IP protocol. (Ex. 2026, ¶ 95.) Thia contemplates use with “standard
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`protocols” conforming to the OSI model, but nowhere discloses that its bypass
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`architecture is compatible with TCP/IP, nor does it test the “feasibility” of its
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`bypass chip with TCP/IP. (Id., ¶ 96.)
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`Accordingly, Thia does not contain any teaching or explanation of a
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`dedicated NIA that implements or even tests TCP header bypass, let alone using
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`flow keys and operation codes, and no explanation of how one would actually
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`implement the theorized, generalized header prediction bypass stack in an actual
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`NIC using the TCP protocol. These details are hardly trivial—they are exactly the
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`prior art hurdles the ’948 patent addressed and overcame. (Ex. 2026, ¶ 97.)
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`B.
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`Tanenbaum, Computer Networks, 3rd ed. (1996) (“Tanenbaum”)
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`Tanenbaum is the third edition of a textbook relating to computer networks.
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`Tanenbaum describes “fast” transport protocol data unit (“TPDU”) processing.
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`(Ex. 1006.583-86.) On the sending side, Tanenbaum notes that “[i]n the normal
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`case, the headers of consecutive data TPDUs are almost the same.” (Id. at .583.)
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`In view of this observation, a “prototype header” is defined. (Id.) In order to
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`construct a packet for transmission, at the TCP layer, the TCP prototype header is
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`copied into the output buffer, the sequence number is filled in, the TCP checksum
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`is computed, and the sequence number is incremented in memory. (Id. at .584.)
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`Then, the TCP header and data is handed “to a special IP procedure” at the IP
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`layer, where the IP prototype header is copied into the output buffer, the
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`“Identification” field is inserted, and the IP checksum is computed. (Id.) The
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`packet is then ready for transmission.
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`On the receive side, a “connection record” is stored in a hash table for
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`lookup (or the last record is tried first). (Id. at .585.) Then conditions for a special
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`“fast path” TCP procedure is checked:
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`The TPDU is then checked to see if it is a normal one:
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`the state is ESTABLISHED, neither side is trying to
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`close the connection, the TPDU is a full one, no special
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`flags are set, and the sequence number is the one
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`expected. These tests take just a handful of instructions.
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`If all conditions are met, a special fast path TCP
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`procedure is called.
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`(Id. at .585.)
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`The connection record is updated, and data is copied to the user. (Id.)
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`During the copy process, the fast path computes the checksum. (Id.) Tanenbaum
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`explains that this general scheme of first making a quick check to see if the header
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`is what is expected, and having a special procedure to handle that case, is called
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`“header prediction.” (Id.) However, Tanenbaum discloses conditions that relate to
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`checking TPDUs, i.e. transport protocol data units, and not packets. (Id.; Ex. 2026,
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`¶¶ 98-101.) The test is performed at the transport layer and not the network layer
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