Universal Serial Bus Specification Revision 2.0
`
`Table 6-7. USB Electrical, Mechanical, and Environmental Compliance Standards (Continued)
`
`Test Description
`
`Test Procedure
`
`Performance Requirement
`
`UL 94 V-0
`
`specified in Table 7-9 (20).
`
`
` UL 94 V-0
`
`The manufacturerwill require its
`thermoplastic resin vendor to
`supply a detailed C of C with each
`This procedure is to ensure
`resin shipment. The C of C shall
`thermoplastic resin compliance to
`clearly show theresin’s UL listing
`UL flammability standards.
`number, lot number, date code,
`etc.
`
`Flammability
`
`The manufacturerwill require its
`thermoplastic resin vendor to
`supply a detailed C of C with each
`resin shipment. The C of C shall
`clearly showthe resin’s UL listing
`number, lot number, date code,
`etc.
`
`Impedance mustbein the range
`
`Flammability
`
`This procedure is to ensure
`thermoplastic resin compliance to
`UL flammability standards.
`
`
`
`Cable Impedance
`(Only required for high-/full-speed)
`
`The object of this test is to insure
`the signal conductors have the
`proper impedance.
`
`1. Connect the Time Domain
`Reflectometer (TDR) outputs
`to the impedance/delay/skew
`test fixture (Note 1). Use
`separate 50 © cables for the
`plus (or true) and minus (or
`complement) outputs. Set the
`TDR head to differential TDR
`mode.
`
`Connect the Series "A" plug of
`the cable to be tested to the
`text fixture, leaving the other
`end open-circuited.
`
`Define a waveform composed
`of the difference betweenthe
`true and complement
`waveforms, to allow
`measurementofdifferential
`impedance.
`
`Measure the minimum and
`maximum impedances found
`between the connector and the
`open circuited far end of the
`cable.
`
`110
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`

`Universal Serial Bus Specification Revision 2.0
`
`Table 6-7. USB Electrical, Mechanical, and Environmental Compliance Standards (Continued)
`
`
`
`
`
`Test Description
`
`Signal Pair Attenuation
`(Only required for high-/full-speed)
`
`Test Procedure
`
`Performance Requirement
`
`Theobject of this test is to insure
`that adequate signal strengthis
`presented to the receiver to
`maintain a low error rate.
`
`Refer to Section 7.1.17 for
`frequency range and allowable
`attenuation,
`
`1. Connect the Network Analyzer
`output port (port 1) to the input
`connector on the attenuation
`test fixture (Note 2).
`
`Connect the Series “A” plug of
`the cable to be tested to the
`test fixture, leaving the other
`end open-circuited.
`
`Calibrate the network analyzer
`andfixture using the
`appropriate calibration
`standards over the desired
`frequency range.
`
`Follow the methodlisted in
`Hewlett Packard Application
`Note 380-2 to measure the
`open-ended responseof the
`cable.
`
`Short circuit the Series “B” end
`(or bare leads end, if a captive
`cable) and measure the short-
`circuit response.
`
`Using the software in H-P App.
`Note 380-2 or equivalent,
`calculate the cable attenuation
`accounting for resonance
`effects in the cable as needed.
`
`11
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`

`Universal Serial Bus Specification Revision 2.0
`
`Test Procedure
`
`The purpose ofthetestIs to verify
`the end to end propagation of the
`cable.
`
`1. Connect one output of the
`TDR sampling head to the D+
`and D- inputs of the
`impedance/delay/skewtest
`fixture (Note 1). Use one 50 2
`cable for each signal and set
`the TDR headto differential
`TDR mode.
`
`High-/full-speed.
`
`See Section 7.1.1.1,
`Section 7.1.4, Section 7.1.16, and
`Table 7-9 (TFSCBL).
`
`Low-speed.
`
`See Section 7.1.1.2,
`Section 7.1.16, and Table 7-9
`(TLSCBL),
`
`Table 6-7. USB Electrical, Mechanical, and Environmental Compliance Standards (Continued) Test Description
` Performance Requirement
`
`
`Propagation Delay
`
`Connect the cable to be tested
`to the testfixture.
`If
`detachable, plug both
`connectors in to the matching
`fixture connectors.
`If captive,
`plug the series “A” plug into
`the matching fixture connector
`and solder the stripped leads
`on the other endto the test
`fixture.
`
`Measure the propagation delay
`of the testfixture by
`connecting a short piece of
`wire acrossthefixture from
`input to output and recording
`the delay.
`
`Removethe short piece of wire
`and remeasure the
`propagation delay. Subtract
`from it the delay of the test
`fixture measuredin the
`previous step.
`
`112
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`

`Universal Serial Bus Specification Revision 2.0
`
`Table 6-7. USB Electrical, Mechanical, and Environmental Compliance Standards (Continued)
`
`Test Description
`
`Test Procedure
`
`Performance Requirement
`
`This test insures that the signal on
`both the D+ and D-lines arrive at
`the receiver at the sametime.
`
`Propagation skew must meetthe
`requirements aslisted in
`Section 7.1.3.
`
`Propagation Delay Skew
`
`Connect the TDR tothefixture
`with test sample cable, as in
`the previous section.
`
`. Measure the difference in
`delay for the two conductorsin
`the test cable. Use the TDR
`cursorsto find the open-
`circuited end of each
`
`conductor (where the
`impedance goesinfinite) and
`subtract the time difference
`between the two values.
`
`The purpose ofthis test is to insure|See Section 7.1.1.2 and Table 7-7
`the distributed inter-wire
`(CLINUA).
`capacitance is less than the
`lumped capacitance specified by
`the low-speed transmit driver.
`
`measure the capacitance.
`
`Capacitive Load
`
`Only required for low-speed
`
`
`
`1. Connect the one lead of the
`Impedance Analyzer to the D+
`pin on the
`impedance/delay/skew fixture
`Note
`1
`id the
`other
`lead t
`
`Nad ae © omeriese
`
`te
`
`Connect the series "A" plug to
`the fixture, with the series “B”
`end leads open-circuited.
`
`Set the Impedance Analyzer to
`a frequency of 100 kHz, to
`
`Note1:
`
`Impedance, propagation delay, and skewtest fixture
`This fixture will be used with the TDR for measuring the time domain performance of the cable under test. The
`fixture impedance should be matched to the equipment, typically 50 2. Coaxial connectors should be provided
`on thefixture for connection from the TDR.
`
`Note 2: Attenuation text fixture
`This fixture provides a means of connection from the network analyzer to the Series "A" plug. Since USB
`signals are differential in nature and operate over balanced cable, a transformer or balun (North Hills NH13734
`or equivalent) is ideally used. The transformer converts the unbalanced (also known as single-ended) signal
`from the signal generator whichis typically a 50 © output to the balanced (also knownasdifferential) and likely
`different impedance loaded presented by the cable. A second transformer or balun should be used on the other
`end of the cable undertest to convert the signal back to unbalanced form of the correct impedance to match the
`network analyzer.
`
`113
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`Universal Serial Bus Specification Revision 2.0
`
`6.7.1 Applicable Documents
`
`American National Standard/Electronic Industries Association
`
`ANSI/EIA-364-C (12/94)—Electrical Connector/Socket Test Procedures
`Including Environmental Classifications
`
`American Standard Test Materials
`
`ASTM-D-4565
`
`ASTM-D-4566
`
`Physical and Environmental Performance Properties
`of Insulation and Jacket for Telecommunication
`
`Wire and Cable, Test Standard Method
`
`Electrical Performance Properties of Insulation and
`Jacket for Telecommunication Wire and Cable, Test
`Standard Method
`
`Underwriters’ Laboratory, Inc.
`
`UL STD-94
`
`Test for Flammability of Plastic materials for Parts
`in Devices and Appliances
`
`UL Subject-444
`
`Communication Cables
`
`6.8 USB Grounding
`The shield must be terminated to the connector plug for completed assemblies. The shield and chassis are
`bonded together. The user selected grounding scheme for USB devices, and cables must be consistent with
`accepted industry practices and regulatory agency standards for safety and EMI/ESD/RFI.
`
`6.9 PCB Reference Drawings
`The drawings in Figure 6-12, Figure 6-13, and Figure 6-14 describe typical receptacle PCB interfaces.
`These drawings are included for informational purposes only.
`
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`

`otherwise noted.
`
`manufacturer to manufacturer.
`
`3. All dimensions are in millimeters (mm) unless
`
`iI
`
`1II1!1
`
`:
`
`@ 2.30 + 0.10 (2)
`eee eee ee si
`dei
`Sie ta Sms a
`Printed Circuit Board (PCB) Layout;
`
`Figure 6-12. Single Pin-type Series "A" Receptacle
`
`115
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`
`
`
`Reference Drawing Only
`
`6.5 REF
`
`2.80+0.10
`
`16.0 REF
`
`13.9 REF
`
`er rer—|
`Te
`
`14.3 REF
`
`
`
`
`
`=
`
`15.0 REF——+| —7.6 REF
`
`6.00+o.10-|+—§+|
`
`12.5 + 0.10
`le 141+ 0.10—»|
`=
`
`R 0.64 + 0.13 Typical (2)
`
`1.84 + 0.05
`
`5.12 + 0.10
`
`2.56 + 0.05
`
`Thermoplastic Insulator UL 94-VO
`
`1II1I
`
`2.00 + 0.05
`
`=
`
`-— i
`
`250+eya+0.05~~1.0+0.05Wide-SelectivelyPlated Contact(4)
`|B 0.92 +0.10 (4)
`NOTES:
`7,00 + 0.10
`1. Critical Dimensions are TOLERANCED
`2.00 + 0.10
`and should not be deviated.
`2. Dimensions that are labeled REF are
`typical dimensions and mayvaryfrom
`
`=
`
`2.714010
`
`/!
`
`‘ oo )
`Pace
`< 43.14 +0.10 +
`
`

`

`3
`
`| | | | | || | || | | | || | |
`
`11.40 REF :
`
`10.28 + 0.20
`
`@ 0.92 + 0.10 (8)
`
`@ 2.3 + 0.10 (4)
`
`—— Connector Front Edge ——
`
`Printed Circuit Board (PCB) Layout
`
`1. Critical Dimensions are TOLERANCED
`and should not be deviated.
`
`. Dimensions that are labeled REF are
`typical dimensions and may vary from
`manufacturer to manufacturer.
`
`
`
`Dual Pin-Type
`
`. All dimensionsare in millimeters (mm
`
`Series "A" Receptacle
`usgiewaned CL|
`
`|.
`
`SCALE: NIA
`
`4
`
`aFT]
`
`Figure 6-13. Dual Pin-type Series "A" Receptacle
`
`116
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`
`
`
`
`
`15.60 REF
`
`14.70£0.10
`
`13.78 + 0.10
`
`12.30 REF
`
`>| ia
`Is
`|+>|-2.00 REF
`
`12.50+0.10
`
`| 3.07 + 0.10 (2)
`!
`2.00+40.10
` :
`959+40,10
`
`7.00 + 0.10
`2.50 + 0.10
`
`nee+X>.O-O-20-4
`soefomne O-O--6-- ntae
`
`

`

`
`pe
`|ae
`
`Universal Serial Bus Specification Revision 2.0
`
`peneeT
`
`2.71 +0.10
`
`4.71 +0.10
`
`3.01 + 0.10
`
`2.00 + 0.10
`
`
`
`11
`
`2.00 REF
`
`I
`
`10,30 REF—|
`
`16.00 REF:
`
`NOTES:
`
`B092+0,1 (4)
`
`B2.30+0.1 (2)
`
`1. Critical Dimensions are TOLERANCED
`and should not be deviated.
`
`Printed Circuit Board (PCB) Layoutee eeee
`
`2. Dimensions that are labeled REF are
`typical dimensions and may vary from
`manufacturer to manufacturer.
`
`6
`
`5
`
`Reference Drawing Only
`
`Single Pin-Type
`
`2/98 4
`
`Series "B" Receptacle
`3. All dimensions are in millimeters (mm)
` DRAWING NUMBERSIZE|DATE REV
`
`
`unless otherwise noted.
`A
`N/A
`c
`SHEET iof1
`
`Figure 6-14. Single Pin-type Series 'B" Receptacle
`
`117
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`1.0 + 0.05 Wide- Selectively Plated Contacts (4)
`
`Thermoplastic Insulator UL 94-V0
`
`
`11.50 REF
`
`7.78 + 0.10
`
`
` 3.50 REF
`
`

`

`Universal Serial Bus Specification Revision 2.0
`
`118
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`Universal Serial Bus Specification Revision 2.0
`
`Chapter7
`Electrical
`
`It contains signaling, power distribution, and
`This chapter describes the electrical specification for the USB.
`physical layer specifications. This specification does not address regulatory compliance.
`It is the responsibility
`of product designers to make sure that their designs comply with all applicable regulatory requirements.
`
`The USB 2.0 specification requires hubs to support high-speed mode. USB 2.0 devices are not required to
`support high-speed mode. A high-speed capable upstream facing transceiver must not support low-speed
`signaling mode. A USB 2.0 downstream facing transceiver must support high-speed, full-speed, and low-speed
`modes.
`
`To assurereliable operation at high-speed datarates, this specification requires the use of cables that conform to
`all current cable specifications.
`
`In each of
`In this chapter, there are numerousreferencesto strings of J’s and K’s,or to strings of 1’s and 0’s.
`these instances, the leftmost symbolis transmitted/received first, and the rightmostis transmitted/receivedlast.
`
`7.1 Signaling
`The signaling specification for the USBis described in the following subsections.
`
`Overview of High-speed Signaling
`
`A high-speed USB connection is made througha shielded, twisted pair cable that conformsto all current USB
`cable specifications.
`
`119
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`Universal Serial Bus Specification Revision 2.0
`
`+3.3V
`
`Rpu_Enable p—---—--—-—-—--—-—-----—-—--—--—-—---—_-—----ey
`
`LSIFS Driver
`
`Rs
`
`i
`
`‘the circuitry required to enable and
`disable 4, ane only required In
`upstream facing ransceivers
`
`|
`HS_Current_Source_Enable
`<a 1
`Note: TheRpupull-upresistor,and
`|
`HighSpeedCurentDriver
`
`LS/FS_Data_Driver_Input Daleputleaa | Rpu
`
`
`
`Assert_Single_Ended_Zero
`FS_Edge_Mode_Sel
`LS/FS_Driver_Output_Enable
`
`ae 6
`
`Rs
`
`HS Differential DataReceiver
`“PD
`LS/FS_Differential_Receiver_Output ot
`HS_Disconnect
`<1Detector
`
`Transmission Envelope Date
`
`olor
`
`LSVFS Differential Data Receiver
`
`P
`
`Disconnection Envelope
`
`Data+
`
`Data-
`
`[
`
`r
`
`.
`
`SE_Data+_Receiver_Output
`5
`SE_Data-_Receiver_Output
`
`|
`
`a
`Single Ended Receivers
`
`Note: The Rad resisters to ground
`are only required in downstream
`facing tanscelvers
`
`Rpd
`
`Rpd
`
`Figure 7-1, Example High-speed Capable Transceiver Circuit
`
`Figure 7-1 depicts an example implementation whichlargely utilizes USB 1.1 transceiver elements and adds the
`new elements required for high-speed operation.
`
`High-speed operation supports signaling at 480 Mb/s. To achievereliable signaling at this rate, the cable is
`terminated at each end with a resistance from each wire to ground. The valueofthis resistance (on each wire)is
`nominally set to 1/2 the specified differential impedance of the cable, or 45 ©. This presents a differential
`termination of 90 Q.
`
`For a link operating in high-speed mode, the high-speed idle state occurs when the transceivers at both ends of
`the cable present high-speed terminations to ground, and when neither transceiver drives signaling current into
`the D+ or D- lines. This state is achieved by using the low-/full-speed driver to assert a single ended zero, and to
`closely control the combinedtotal of the intrinsic driver output impedance andthe Rs resistance (to 45 Q,
`nominal), The recommendedpractice is to makethe intrinsic driver impedanceas low as possible, and to let Rs
`contribute as much of the 45 Q as possible. This will generally lead to the best termination accuracy with the
`least parasitic loading.
`
`In order to transmit in high-speed mode, a transceiver activates an internal current source whichis derived from
`its positive supply voltage and directs this current into one of the two data lines via a high speed current steering
`switch.
`In this way, the transceiver generates the high-speed J or K state on the cable.
`
`The dynamic switching of this current into the D+ or D- line follows the same NRZI data encoding scheme used
`in low-speed or full-speed operation and also in the bit stuffing behavior. To signal a J, the current is directed
`into the D+ line, and to signal a K, the currentis directed into the D- line. The SYNC field and the EOP
`delimiters have been modified for high-speed mode.
`
`120
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`
`The magnitudeofthe current source and the value ofthe termination resistors are controlled to specified
`tolerances, and together they determine the actual voltage drive levels. The DC resistance from D+ or D- to the
`device ground is required to be 45 £2 +10% when measured withouta load, and the differential output voltage
`measuredacrossthe lines (in either the J or K state) must be +400 mV +10% when D+and D-are terminated
`with precision 45 Q resistors to ground.
`
`The differential voltage developed across the lines is used for three purposes:
`
`e
`
`e
`
`e
`
`A differential receiver at the receiving end of the cable receives the differential data signal.
`
`A differential envelope detector at the receiving end of the cable determines whenthelink is in the Squelch
`state. A receiver uses squelch detection as indication that the signal at its connectoris not valid.
`
`Inthe case of a downstream facing hub transceiver, a differential envelope detector monitors whether the
`signalat its connectoris in the high-speed state. A downstream facing transceiver operating in high-speed
`modeis required to test for this state at a particular point in time whenit is transmitting a SOF packet, as
`described in Section 7.1.7.3. This is used to detect device disconnection.
`In the absence of the far end
`terminations, the differential voltage will nominally double (as compared to when a high-speed device is
`present) when a high-speed J or K are continuously driven for a period exceeding the round-trip delay for
`the cable and board-traces between the two transceivers.
`
`USB 2.0 requires that a downstreamfacing transceiver must be able to operate in low-speed, full-speed, and
`high-speed signaling modes. An upstream facing high-speed capable transceiver must not operate in low-speed
`signaling mode, but mustbe able to operate in full-speed signaling mode. Therefore, a 1.5 kQ pull-up on the D-
`line is not allowed for a high-speed capable device, since a high-speed capable transceiver must neversignal
`low-speed operation to the hub port to whichit is attached.
`
`Table 7-1 describes the required functional elements of a high-speed capable transceiver, using the diagram
`shownin Figure 7-1 as an example.
`
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`
`Table 7-1. Description of Functional Elements in the Example Shownin Figure 7-1
`
`Description
`
`
`
` The low-/full-speed driver is used for low-speed andfull-speed transmission.
`It
`Low-/full-speed Driver
`is required to meetall specifications called out in USB 1.1 for low-speed andfull-
`
`speed operation, with one exception. The exceptionis that in high-speed
`
`
`capable transceivers, the impedance of each output, including the contribution of
`
`
`Rs, must be 45 QO +10%.
`
`
`
`
`The line terminations for high-speed operation are created by having this driver
`
`
`
`(This is equivalent to driving SEO in the full-speed or
`drive D+ and D- to ground.
`low-speed mode.) Becauseof the output impedance requirement described
`above, this provides a well-controlled high-speed termination on each data line
`
`to ground. This is equivalent to a 90 Q differential termination.
`
`
`
` Low-/full-speed Differential
`
`The low-/full-speed differential receiver is used for receiving low-speed and full-
`speed data.
`The single ended receivers are used for low-speed and full-speed signaling.
`
`
`Single Ended Receivers
`
`
`The high-speed currentdriver is used for high-speed data transmission. A
`High-speed Current Driver
`current source derived from a positive supply is switched into either the D+ or D-
`
`
`lines to signal a J or a K, respectively. The nominal value of the current source
`
`is 17.78 mA. Whenthis current is applied to a data line with a 45 © termination
`
`to ground at each end, the nominal high level voltage (VHSOH) is +400 mV. The
`
`nominal differential high-speed voltage (D+ - D-) is thus 400 mV for a J and
`
`-400 mV fora K.
`
`
`
`Receiver
`
`
`
`
`
`
`
`The current source must comply with the Transmit Eye Pattern Templates
`specified in Section 7.1.2.2, starting with the first symbol of a packet. One
`
`meansof achieving this is to leave the current source on continuously when a
`
`transceiver is operating in high-speed mode.
`If this approach is used, the
`
`current can be directed to the port ground when the transceiver is not
`
`transmitting (the example design in Figure 7-1 shows a controlline called
`
`HS_Current_Source_Enable to turn the current on, and another called
`
`HS_Drive_Enable to direct the current into the data lines.) The penalty of this
`
`approachis the 17.78 mAofstanding current for every such enabled transceiver
`
`in the system.
`
`
`
`
`The preferred design is to fully turn the current source off when the transceiver
`is not transmitting.
`
`
`
`
`It
`The high-speed differential data receiver is used to receive high-speed data.
`High-speed Differential Data
`Receiver
`is left to transceiver designers to choose betweenincorporating separate high-
`
`
`
`
`
`
`speed and low-/full-speed receivers, as shown in Figure 7-1, or combining both
`
`functions into a single receiver.
`
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`Table 7-1. Description of Functional Elements in the Example Shownin Figure 7-1 (Continued)
`
`speedoperation.
`
`Transmission Envelope
`Detector
`
`Disconnection Envelope
`Detector
`
`Pull-up Resistor (Rev)
`
`This envelope detector is used to indicate that data is invalid when the
`amplitude of the differential signal at a receiver's inputs falls below the squelch
`threshold (VHSsq).
`It must indicate Squelch when the signal drops below
`100 mV differential amplitude, and it must indicate that the line is not in the
`Squelch state when the signal exceeds 150 mV differential amplitude. The
`response time of the detector must be fast enough to allow a receiver to detect
`data transmission, to achieve DLLlock, and to detect the end of the SYNC field
`within 12 bit times, the minimum number of SYNCbits that a receiveris
`guaranteed to see. This envelope detector mustincorporatea filtering
`mechanism that prevents indication of squelch during the longestdifferential
`data transitions allowed by the receiver eye pattern specifications.
`
`This envelope detector is required in downstream facing ports to detect the high-
`speed Disconnect state on the line (VHSoSc). Disconnection mustbe indicated
`when the amplitude of the differential signal at the downstream facing driver's
`connector 2625 mV, and it must not be indicated when the signal amplitude is
`<525 mV. The outputof this detector is sampled at a specific time during the
`transmission of the high-speed SOF EOP, as described in Section 7.1.7.3.
`
`This resistor is required only in upstream facing transceivers and is used to
`indicate signaling speed capability. A high-speed capable device is required to
`initially attach as a full-speed device and musttransition to high-speed as
`describedin this specification. Once operating in high-speed, the 1.5 kQ
`resistor must be electrically removed from the circuit.
`In Figure 7-1, a control
`line called Reu_Enableis indicated for this purpose. The preferred embodiment
`is to attach matched switching devices to both the D+ and D-lines so as to keep
`the lines' parasitic loading balanced, even though a pull-up resistor must never
`be used on the D-line of an upstream facing high-speed capable transceiver.
`When connected, this pull-up must meetall the specifications called out for full-
`
`Pull-down Resistors (Rep)
`
`These resistors are required only in downstream facing transceivers and must
`conform to the same specifications called out for low-speed andfull-speed
`operation.
`
`7.1.1 USB Driver Characteristics
`
`The USB usesa differential output driver to drive the USB data signal onto the USBcable.
`
`For low-speed and full-speed operation, the static output swing of the driverin its low state must be below Voi
`(max) of 0.3 V with a 1.5 kQ load to 3.6 V, andin its high state must be above the Vou (min)of 2.8 V with a
`15 kQ load to groundas listed in Table 7-7. Full-speed drivers have more stringent requirements, as described
`in Section 7.1.1.1. The output swings betweenthe differential high and low state must be well-balanced to
`minimize signal skew. Slew rate control on the driver is required to minimize the radiated noise andcrosstalk.
`The driver’s outputs must support three-state operation to achieve bi-directional half-duplex operation.
`
`Low-speed and full-speed USB drivers must never“intentionally” generate an SE] on the bus. SE] is a state in
`which both the D+ and D- lines are at a voltage above Vose1 (min), whichis 0.8 V.
`
`High-speed drivers use substantially different signaling levels, as described in Section 7.1.1.3.
`
`USBports must be capable of withstanding continuous exposure to the waveforms shownin Figure 7-2 while in
`any drive state. These waveformsare applied directly into each USB data pin from a voltage source with an
`
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`Universal Serial Bus Specification Revision 2.0
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`output impedance of 39 Q. The open-circuit voltage of the source shown in Figure 7-2 is based on the expected
`worst-case overshoot and undershoot.
`
`AC Stress Evaluation Setu
`
`D+ or D- pin
`on USB connector
`nearest device
`
`USB
`
`Device
`
`Se
`
`Rsrac = 390 42%
`The signal produced by the voltage generator may be
`distorted when observedat the data pin due to input
`protection devices possibly incorporated in the USB
`device,
`
`-1.0V
`
`166.7ns
`
`
`
`(6MHz)
`
`
`
`Figure 7-2. Maximum Input Waveforms for USB Signaling
`
`Short Circuit Withstand
`
`A USBtransceiver is required to withstand a continuous short circuit of D+ and/or D- to VBUS, GND, other data
`line, or the cable shield at the connector, for a minimum of 24 hours without degradation. It is recommended
`that transceivers be designed so as to withstand such short circuits indefinitely. The device must not be damaged
`underthis short circuit condition when transmitting 50% ofthe time and receiving 50% ofthe time(in all
`supported speeds). The transmit phase consists of a symmetricalsignal that toggles between drive high and
`drive low. This requirement must be met for max value of VBUS(5.25 V).
`
`It is recommendedthat these AC and short circuit stresses be used as qualification criteria against which the
`long-term reliability of each device is evaluated.
`
`7.1.1.1 Full-speed (12 Mb/s) Driver Characteristics
`A full-speed USB connection is made through a shielded, twisted pair cable with a differential characteristic
`impedance (Zo) of 90 2 15%, a common mode impedance (Zc) of 30 Q +30%, and a maximum one-way
`delay (Trscsc) of 26 ns. When the full-speed driveris not part of a high-speed capable transceiver, the
`impedance ofeach ofthe drivers (Zprv) must be between 28 2 and 44 Q,i.e., within the gray area in Figure 7-4.
`Whenthe full-speed driver is part of a high-speed capable transceiver, the impedanceofeach ofthe drivers
`(ZHspRV) must be between 40.5 Q and 49.5 Q,i.e., within the gray area in Figure 7-5.
`
`For a CMOSimplementation,the driver impedance will typically be realized by a CMOSdriver with an
`impedancesignificantly less than this resistance with a discrete series resistor making up the balance as shown in
`Figure 7-3. The series resistor Rs is included in the buffer impedance requirement shownin Figure 7-4 and
`Figure 7-5.
`In the rest of the chapter, references to the buffer assume a buffer with the series impedance unless
`stated otherwise.
`
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`Buffer Output Imped. (Zeur)
`
`D+ (28Q to 44Q Equiv. Imped.)
`ye Buffers D-
`
`
`Identical
`CMOS
`
`(28Q to 44Q Equiv. Imped.)
`
`Figure 7-3. Example Full-speed CMOSDriver Circuit (non High-speed capable)
`
`Full-speed Buffers in Transceivers Which are Not High-speed Capable
`
`The buffer impedance must be measured fordriving high as well as driving low. Figure 7-4 showsthe
`composite V/I characteristics for the full-speed drivers with included series dampingresistor (RS). The
`characteristics are normalized to the steady-state, unloaded output swing of the driver. The normalized driver
`characteristics are found by dividing the measured voltages and currents by the actual swing of the driver under
`test. The normalized V/I curve for the driver must fall entirely inside the shaded region. The V/I region is
`bounded by the minimum driver impedance above and the maximum driver impedance below. The minimum
`drive region is intersected by a constant current region of |6.1 VOH| mA when driving low and -|6.1 VOH| mA
`whendriving high.
`In the special case of a full-speed driver which is driving low, and whichis part of a high-
`speed capable transceiver, the low drive region is intersected by a constant current region of 22.0 mA. Thisis
`the minimum currentdrive level necessary to ensure that the waveform at the receiver crosses the opposite
`single-ended switching levelon the first reflection.
`
`Whentesting, the current into or out of the device need not exceed +10.71*VOH mAandthe voltage applied to
`D+/D- need not exceed 0.3*VOHfor the drive low case and need not drop below 0.7*VOHfor the drive high
`case.
`
`Full-speed Buffers in High-speed Capable Transceivers
`
`Figure 7-5 shows the V/I characteristics for a Full-speed buffer whichis part of a high-speed capable
`transceiver. The output impedance, Zusprv (including the contribution of RS), is required to be between 40.5 2
`and 49.5 9. Additionally, the output voltage must be within 10mV of ground when no current is flowing in or
`out of the pin (VHsTERM).
`
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`Universal Serial Bus Specification Revision 2.0
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`drive low
`
`lout
`(m4)|Slope = 1/28Q
`-
`. >
`Test Limit
`
`10.71% [Vou
`
`
`
`
`6.1 * [Vou
`
`2.32
`
`;
`
`0
`
`0.3V
`
`0
`
`1
`
`0.27°Vou
`
`I
`0.3"VoH yy (Volts)
`
`Vox
`
`drive high
`
`SI
`
`s[aace
`ope = Oe
`
`6.1*|Voul
`
`.
`Test Limit
`
`
`-10.71*[Vout Slope = 1/28Q
`
`lout
`(mA)
`
`0
`
`Vout (Volts)
`
`0.7*Von 0.73*Vox
`
`Vox
`
`Figure 7-4. Full-speed Buffer V/I Characteristics
`
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`Universal Serial Bus Specification Revision 2.0
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`drive low
`
`Slope = 1/40.5Q
`“a
`
`Test Limit
`
`lout
`(mA)
`
`10.74 * [Vou
`
`22.0
`
`|
`
`
`= Slope = 1/49.5Q
`
`0
`
`1.09V 0.434*V
`
`"Vout (Volts)
`
`ative Tigi
`
`sl
`
`ope =
`
`4/49 ne
`
`:
`
`-6.1*|Voul
`
`10.74 * Vout
`
`lout
`(mA)
`
`Testlinae
`
`Slope = 1/40.50
`
`1
`
`0
`
`Vout (Volts)
`
`0.566*VoH 0.698*V5y
`
`Vox
`
`Figure 7-5. Full-speed Buffer V/I Characteristics for High-speed Capable Transceiver
`
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`One-Way
`Trip Cable
`Delay
`
`
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`Universal Serial Bus Specification Revision 2.0
`
`Figure 7-6 showsthe full-speed driver signal waveforms.
`
`Driver
`Signal Pins
`
`Vss
`
`Receiver
`Signal Pins
`
`Vss
`
`Vin(min)
`Se\
`Signal pins pass
`
`input spec levels
`after one cable
`delay
`
`
`VIL (max)
`
`Figure 7-6. Full-speed Signal Waveforms
`
`7.1.1.2 Low-speed (1.5 Mb/s) Driver Characteristics
`A low-speed device must have a captive cable with the Series A connector on the plug end. The combination of
`the cable and the device must have a single-ended capacitance of no less than 200 pF and no more than 450 pF
`on the D+ or D-lines.
`
`The propagation delay (TLSCBL) of a low-speed cable must be less than 18 ns. This is to ensure that the
`reflection occurs duringthe first half of the signal rise/fall, which allows the cable to be approximated by a
`lumped capacitance,
`
`Figure 7-7 shows the low-speed driver signal waveforms.
`
`
`
`4+.
`
`Signal pins
`pass output
`speclevels
`with minimal
`reflections and
`ringing
`
`Vin (min)
`Driver
`si
`1 Pi
`ignal
`Pins
`
`Figure 7-7. Low-speed Driver Signal Waveforms
`
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`7.1.1.3 High-speed (480 Mb/s) Driver Characteristics
`A high-speed USB connection is made through a shielded, twisted pair cable with a differential characteristic
`impedance (Zo) of 90 Q +15%, a common mode impedance (Zcm) of 30 2 +30%, and a maximum one-way
`delay of 26 ns (Trsca_). The D+ and D- circuit board traces which run betweena transceiverandits associated
`connector should also have a nominal differential impedance of 90 Q, and together they may add an additional
`4 ns of delay between the transceivers. (See Section 7.1.6 for details on impedancespecifications of boards and
`transceivers.) The differential output impedance of a high-speed capable driver is required to be 90 2 10%.
`Wheneither the D+ or D- lines are driven high, VHsou (the high-speed mode high-level output voltage driven on
`a data line with a precision 45 © load to GND) must be 400 mV +10%. Ona line whichis not driven, either
`becausethe transceiveris not transmitting or because the oppositeline is being driven high, Vxsot (the high-
`speed mode low-level output voltage driven on a data line with a 45 Q load to GND) must be 0 V+ 10 mV.
`
`Note: Unless indicated otherwise, all voltage measurements are to be made with respectto the local circuit
`ground.
`
`Note: This specification requires that a high-speed capable transceiver operating in full-speed or low-speed
`mode must have a driver impedance (ZxHsprv) of 45 2 +10%.
`It is recommendedthat the driver impedances be
`matched to within 5 © within a transceiver. For upstream facing transceivers which do not su