ete Tem
`
`4 MEG x 4 SDRAM
`
`MT48LC4M4R1(S)
`
`4 MEG x 4SDRAM
`SYNCHRONOUS
`Pulsed RAS, Dual Bank,
`DRAM
`BURSTMode, 3.3V, SELF REFRESH
`
`
`ADVANCE
`
`PIN ASSIGNMENT(Top View)
`
`44-Pin TSOP
`FORWARD
`(DD-7)
`
`
`
`WVYGSNONOYHONAS
`
`=
`
`FEATURES
`* Fully synchronous;all signals (excluding clock enable)
`registered to positive edge of system clock
`* Meets all JEDEC functional specifications
`* Dualinternal banks: dual 2 Meg x 4 architecture
`Programmable burst-lengths: 2, 4, 8 cycles or full-page
`burst
`Programmable burst-sequence: sequential or interleave
`Burst termination
`Multiple burst READ,single WRITE capability
`Hidden precharge capability with optional automatic
`precharge command
`Programmable READlatency:1, 2 or 3 clocks
`Industry-standard x8 pinouts, timing, functions and
`packages
`* Refresh modes: AUTO and SELF
`* Standard and extended AUTO REFRESHrates
`* High-performance CMOSsilicon-gate process
`= Lead-over-chip assembly architecture
`" Single +3.3V £0.3V power supply
`* Low power, mW standby; 200mW active, typical
`« LVTTL-compatible
`¢ CKE-controlled power-down and suspend operations
`© Moderegister programming
`¢ JEDEC-standard commandset(pulsed RAS)
`OPTIONS
`MARKING
`with a synchronous interface. Each byte is uniquely ad-
`
`* Timing
`dressed through a bank-select bit and 20 addressbits. The
`(S100 MHz)
`10ns access
`bank select and address are enteredfirst by RASregistering
`( <83 MHz)
`12ns access
`(row active command) 12 bits (A0-A10, BA) and then
`13.3ns access ( <75 MHz)
`CASregistering 11 bits (A0-A9, BA). At CAS registration
`« Auto Refresh
`(READor WRITE command), addressbit A10 defines auto-
`
`prechargestate (active HIGH). Bankselection is controlled
`4,096-cycle iné4ms—(15.6us/row) none
`
`by BA during both RAS and CASregistration.
`4,096-cycle in 128ms (31.25,18/row)
`Ss
`The MT48LC4M4R_1is designed to operate in a synchro-
`* SELF REFRESH
`none
`nous, 3.3V memorysystem. All input and output signals,
`Not allowed
`with the exception of clock enable (CKE) during POWER-
`Allowed
`S
`DOWNand SELF REFRESH modes, are synchronized to
`© Plastic Packages
`the positive-going edge of the system clock (CLK).
`TG
`44-pin TSOP (400 mil)—-forward
`The synchronous DRAMhasseveral programmablefea-
`tures to allow maximum performanceineachuser’s system.
`* Part Number Example: MT48LC4M4R1TG-10 5
`Additionally, bank switching between the two internal
`memory banks in conjunction with the programmable
`GENERAL DESCRIPTION
`BURST modeprovides very high-speed performance.
`The MT48LC4M4R1(S) is a randomly accessed, solid-
`The synchronous DRAM allows both AUTO REFRESH
`(during normal operation) and SELF REFRESH {for low-
`state memory containing 16,777,216 bits organized ina x4
`power, data-retention operation).
`configuration.It is structured as a dual 2 Meg x 4 DRAM
`Micron Serricorductor, Ine.reserves the right 30 change products o¥ specifications withour natice.
`MT4SLCAMABISI
`3°094. Micron Semiconductor, inc.
`EV. 494
`2-1
`
`orE=
`owT
`==a2+e
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`
`
`-10
`-12
`-13
`
`IPR2018-00047
`ASUS Computer EX1010 Page 1 of 2
`
`IPR2018-00047
`ASUS Computer EX1010 Page 1 of 2
`
`

`

`4 MEG x 4 SDRAM
`
`MICRON
`areata
`
`ADVANCE
`MT48LC4M4R1(S)
`
`FUNCTIONAL BLOCK DIAGRAM
`
`
`DATA-IN
`
`
` BUFFER
`
`
`
`
`
`
`DATA-OUT
`BUFFER
`
`
`
`WVYdSNONOYHONASi
`
`
`
`
`
`
`CONTROLLOGIC
`
`COMMAND
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`
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`ROWDECODER
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`ADDRESS
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`ADDRESS
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`NO.
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`Row-
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`BUFFERS
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`MT42LCAMMR{S) Micron Semicenductar, Inc,raserves the right “r change prod..cts oF specifications without notice.
`REV. 494
`2-2
`<sr9a8, Micron SemeaonduetaIne
`
`IPR2018-00047
`ASUS Computer EX1010 Page 2 of 2
`
`IPR2018-00047
`ASUS Computer EX1010 Page 2 of 2
`
`