a2, United States Patent
`US 6,172,928 B1
`(10) Patent No.:
`Jan. 9, 2001
`(45) Date of Patent:
`Ooishi
`
`US006172928B1
`
`(54) SEMICONDUCTOR MEMORYDEVICE
`WITH NORMAL MODE AND POWER DOWN
`MODE
`
`5,959,927 *
`
`9/1999 ‘Yamagata et al. o...... ce 365/229
`
`FOREIGN PATENT DOCUMENTS
`
`(75)
`
`Inventor: Tsukasa Ooishi, Hyogo (JP)
`
`9-231756
`
`9/1997 (JP).
`
`(73) Assignee: Mitsubishi Denki Kabushiki Kaisha,
`Tokyo (JP)
`
`* cited by examiner
`
`(*) Notice:
`
`Under 35 U.S.C. 154(b), the term of this
`patent shall be extended for 0 days.
`
`(21)
`
`(22)
`
`(30)
`
`Appl. No.: 09/323,819
`
`Filed:
`
`Jun. 2, 1999
`
`Foreign Application Priority Data
`
`Dec. 4, 1998
`
`(TP) cesssssessssnsesssseenssensesenstsnesee 10-346051
`
`TInt. Cn eeeceeeesssssssssnnsesceesnnnnesseseesnnnees GUC 7/00
`(SL)
`
`(52) US. Ch. wee . 365/222; 365/229; 365/226
`(58) Field of Search 0... 365/226, 222,
`365/229, 230.06, 189.05
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`Primary Examiner—David Nelms
`Assistant Examiner—Thong Le
`(74) Attorney, Agent, or Firm—McDermott, Will & Emery
`
`(57)
`
`ABSTRACT
`
`A semiconductor memory device includes a logic unit, a
`DRAM unit, and first and second PMOStransistors. In a
`normal mode, the first PMOStransistor is off and the second
`PMOStransistor is on, whereby power supply voltage is
`supplied to all the circuits. In a power down mode,thefirst
`PMOStransistor is on and the second PMOStransistor is
`off, so that power is not supplied to circuitry that is not
`required for a self refresh operation. Power supply voltage
`is provided to circuitry that is required for a self refresh
`operation. Thus, current consumption during self refresh can
`be reduced.
`
`5,856,951 *
`
`1/1999 Arimoto et al. wee 365/226
`
`16 Claims, 19 Drawing Sheets
`
`MODE
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`IPR2018-00047
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`

`

`U.S. Patent
`
`Jan. 9, 2001
`
`Sheet 1 of 19
`
`US 6,172,928 B1
`
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`U.S. Patent
`
`Jan. 9, 2001
`
`Sheet 2 of 19
`
`US 6,172,928 B1
`
`FIG.2
`
`Vcc Py
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`Vcc po
`
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`SELF REFRESH
`
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`U.S. Patent
`
`Jan. 9, 2001
`
`Sheet 3 of 19
`
`US 6,172,928 B1
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`U.S. Patent
`
`Jan. 9, 2001
`
`Sheet 4 of 19
`
`US 6,172,928 B1
`
`FIG.4
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`8-BIT INPUT
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`

`U.S. Patent
`
`Jan. 9, 2001
`
`Sheet 5 of 19
`
`US 6,172,928 B1
`
`FIG.5
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`U.S. Patent
`
`Jan. 9, 2001
`
`Sheet 6 of 19
`
`US 6,172,928 B1
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`U.S. Patent
`
`Jan. 9, 2001
`
`Sheet 7 of 19
`
`US 6,172,928 B1
`
`FIG.8
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`IPR2018-00047
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`

`U.S. Patent
`
`Jan. 9, 2001
`
`Sheet 8 of 19
`
`US 6,172,928 B1
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`U.S. Patent
`
`Jan. 9, 2001
`
`Sheet 9 of 19
`
`US 6,172,928 B1
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`

`U.S. Patent
`
`Jan. 9, 2001
`
`Sheet 10 of 19
`
`US 6,172,928 B1
`
`FIG.11
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`NORMAL MODE
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`

`Jan. 9, 2001
`
`Sheet 11 of 19
`
`US 6,172,928 B1
`
`U.S. Patent
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`U.S. Patent
`
`Jan. 9, 2001
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`Sheet 12 of 19
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`US 6,172,928 B1
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`U.S. Patent
`
`Jan. 9, 2001
`
`Sheet 13 of 19
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`US 6,172,928 B1
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`U.S. Patent
`
`Jan. 9, 2001
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`Sheet 14 of 19
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`U.S. Patent
`
`Jan. 9, 2001
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`Sheet 15 of 19
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`US 6,172,928 B1
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`U.S. Patent
`
`Jan. 9, 2001
`
`Sheet 16 of 19
`
`US 6,172,928 B1
`
`FIG.18
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`U.S. Patent
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`Jan. 9, 2001
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`Sheet 17 of 19
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`US 6,172,928 B1
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`U.S. Patent
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`Jan. 9, 2001
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`Sheet 18 of 19
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`US 6,172,928 B1
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`U.S. Patent
`
`Jan. 9, 2001
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`Sheet 19 of 19
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`US 6,172,928 B1
`
`1
`SEMICONDUCTOR MEMORY DEVICE
`WITH NORMAL MODE AND POWER DOWN
`MODE
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`
`The present invention relates to semiconductor memory
`devices, and moreparticularly to a semiconductor memory
`device having a normal mode and a power down mode.
`2. Description of the Background Art
`In a semiconductor memory device referred to as a
`DRAM (Dynamic Random Access Memory), a refresh
`operation is carried out to maintain the data stored in a
`memory cell. This refresh operation is carried out on the
`basis of a word line. Upon application of a pulse to a selected
`word line, a read out of small signals*amplifyeand rewrite
`operation are carried out for all the memory cells on the
`selected word line, whereby all the memory cells on the
`word line are refreshed at the same time. By sequentially
`selecting a word line in such a manner,all the memorycells
`will be refreshed. The method of executing a refresh opera-
`tion includes the methodof carrying out a refresh operation
`of one cycle (one word line)
`for every predetermined
`interval, and the method of refreshing all the memory cells
`at a burst at an elapse of a predetermined time.
`During the execution of such a refresh operation, not only
`circuitry required for the refresh operation, but also circuitry
`irrelevant to the refresh operation operates. Therefore, leak-
`age current is generated in association with activation of the
`transistors included in the circuitry that is not required for
`the refresh operation. This leakage current becomesso great
`as to reduce the threshold value of the transistor. Although
`the threshold value must be lowered in accordance with
`microminiaturization of the transistor,
`the entire current
`consumption of circuitry that uses such a transistor will
`increase.
`
`SUMMARYOF THE INVENTION
`
`An object of the present invention is to provide a semi-
`conductor memory device that can reduce current consump-
`tion during a self refresh operation.
`According to an aspect of the present invention, a semi-
`conductor memory device with a normal mode and a power
`down mode includesa plurality of memorycells, a plurality
`of first word lines, a plurality of bit line pairs, a sense
`amplifier, an address buffer, a self refresh control circuit, a
`row decoder, a plurality of first word line drivers, a first
`power supply, and a second power supply. The plurality of
`memory cells are arranged in rows and columns. The
`plurality of first word lines are arranged in rows. The
`plurality ofbit line pairs are arranged in columns. The sense
`amplifier amplifies the data signal ofthe plurality of bit line
`pairs. The address buffer generates an internal address signal
`in response to an external address signal. The self refresh
`control circuit generates a refresh address signal when in a
`power down mode. The row decoderresponds to an internal
`address signal to generate a decode signal when in a normal
`mode, and respondsto a refresh address signal to generate
`a decode signal when in a power down mode. Theplurality
`of first word line drivers are provided corresponding to the
`plurality of first word lines to render a correspondingfirst
`word line active in response to a decode signal. The first
`power supply supplies a power supply voltage to the sense
`amplifier, the address buffer, the self refresh control circuit,
`the row decoder, and the plurality of first word line drivers
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
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`
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`whenin a normal mode, and does not supply a power supply
`voltage to the sense amplifier, the address buffer, the self
`refresh control circuit, the row decoder, and the plurality of
`first word line drivers when in a power down mode. The
`second power supply provides a powersupply voltage to the
`sense amplifier,
`the self refresh control circuit,
`the row
`decoder, and the plurality of first word line drivers when in
`a power down mode, and doesnot supply of a power supply
`voltage to the sense amplifier, the self refresh control circuit,
`the row decoder and the plurality of first word line drivers
`when in a normal mode.
`
`In the above semiconductor memory device, power con-
`sumption during a self refresh operation can be reduced
`since poweris not supplied to the address buffer that is not
`required for the self refresh operation when in a power down
`mode.
`
`According to another aspect of the present invention, a
`semiconductor memory device that has a normal mode and
`a power down mode includes a main power supply line, a
`main ground line,first and second sub-power supply lines,
`first and second sub-ground lines, a plurality of memory
`cells, a plurality of first word lines, a plurality of bit line
`pairs, a sense amplifier, an address buffer, a self refresh
`control circuit, a row decoder, a plurality of first word line
`drivers, a first connection circuit, a second connection
`circuit, a third connection circuit and a fourth connection
`circuit. The main power supply line receives a power supply
`voltage. The main ground line receives a ground voltage.
`The plurality of memory cells are arranged in rows and
`columns. The plurality of first word lines are arranged in
`rows. The plurality of bit line pairs are arranged in columns.
`The sense amplifier amplifies the data signal of the plurality
`of bit line pairs. The address buffer generates an internal
`address signal in response to an external address signal. The
`self refresh control circuit generates a refresh address signal
`when in a power down mode. The row decoder generates a
`decode signal in response to an internal address signal when
`in a normal mode andin responseto a refresh address signal
`when in a power down mode. Theplurality of first word line
`drivers are provided corresponding to the plurality of first
`word lines to render a correspondingfirst word line active in
`response to a decode signal. The first connection circuit sets
`the main power supply line and the first sub-power supply
`line connected and unconnected whenin a normal mode and
`in a power down mode,respectively. The second connection
`circuit sets the main groundline andthe first sub-groundline
`connected and unconnected when in a normal modeand in
`
`a power down mode, respectively. The third connection
`circuit sets the main power supply line and the second
`sub-powersupply line connected and unconnected when in
`a power down mode and in a normal mode, respectively. The
`fourth connection circuit sets the main ground line and the
`second sub-ground line connected and unconnected when in
`a power down mode and in a normal mode, respectively. The
`address buffer includes a plurality offirst logic circuits and
`a plurality of secondlogic circuits. The plurality offirst logic
`circuits are connected between the main power supply line
`andthe first sub-groundline to output a signal of a high logic
`level when in a power down mode. The plurality of second
`logic circuits are connected between the first sub-power
`supply line and the main groundline to output a signal of a
`low logic level when in a power down mode. Theself refresh
`control circuit includesa plurality of third logic circuits, and
`a plurality of fourth logic circuits. The plurality of third logic
`circuits are connected between the main power supply line
`and the second sub-groundline to output a signal of a high
`logic level when in a normal mode. The plurality of fourth
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`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 4 is a block diagram showing a structure of a
`predecoder of FIG. 1.
`FIG. 5 showsan example of a pass transistor logic circuit
`of FIG. 4.
`
`FIG. 11 is a timing chart for describing an operation of the
`main word driver of FIG. 10.
`
`FIG. 12 is a circuit diagram showing a structure of a sub
`word driver of FIG. 9.
`FIG. 13 shows in detail a structure of the sub decode
`driver of FIG. 9.
`
`FIG. 6 is a circuit diagram showing a structure of the pass
`transistor logic circuit of FIG. 5.
`FIG. 7 is a timing chart for describing a self refresh
`operation by the semiconductor memory device of FIG. 1.
`FIG. 8 is a block diagram showing a powersupply system
`of a semiconductor memory device according to a second
`embodiment of the present invention.
`FIG. 9 is a block diagram showing a structure of a
`memory cell array unit provided corresponding to each
`memory bank in a semiconductor memory device according
`to a third embodimentof the present invention.
`FIG. 10 showsin detail a structure of one of the plurality
`of main word drivers of FIG. 9.
`
`3
`logic circuits are connected between the second sub-power
`supply line and the main groundline to output a signal of a
`FIG. 1 is a block diagram showing an entire structure of
`low logic level when in a normal mode.
`a semiconductor memory device accordingto a first embodi-
`In the above semiconductor memory device, the address
`ment of the present invention.
`buffer does not operate when in a power down mode.
`FIG. 2 is a block diagram showing a powersupply system
`Therefore,
`the subthreshold current flowing through the
`of the semiconductor memory device of FIG. 1.
`plurality of first and second logic circuits can be reduced by
`FIG. 3 is a block diagram showingastructure of a self
`setting the main power supply line and the first sub-power
`refresh control circuit of FIG. 1.
`supply line unconnected and the main ground line and the
`first sub-ground line unconnected by the first and second
`connection circuits, respectively. In a normal mode, theself
`refresh control circuit does not operate. Therefore,
`the
`subthreshold current flowing through the plurality of third
`and fourth logic circuits can be reduced by setting the main
`power supply line and the second sub-power supply line
`unconnected and the main ground line and the second
`sub-ground line unconnected by the third and fourth con-
`nection circuits, respectively.
`According to a further aspect of the present invention, a
`semiconductor memory device having a normal mode and a
`power down modeincludes a logic unit with a plurality of
`logic circuit groups, and a DRAM unit. The DRAM unit
`includesa plurality of memorycells, a plurality of first word
`lines, a plurality of bit line pairs, a sense amplifier, an
`address buffer, a self refresh control circuit, a row decoder,
`and a plurality of first word line drivers. The plurality of
`memory cells are arranged in rows and columns. The
`plurality of first word lines are arranged in rows. The
`plurality ofbit line pairs are arranged in columns. The sense
`amplifier amplifies the data signal ofthe plurality of bit line
`pairs. The address buffer generates an internal address signal
`in response to an external address signal. The self refresh
`control circuit generates a refresh address signal when in a
`FIG. 14 is a block diagram showingastructure of a driver
`power down mode. The row decoder generates a decoded
`35
`that provides control of a decode signal.
`signal
`in response to an internal address signal and in
`response to a refresh address signal when in a normal mode
`FIG. 15 is a block diagram showinga structure of a driver
`and in a power down mode, respectively. The plurality of
`of an equalize signal.
`first word line drivers are provided corresponding to the
`FIG. 16 is a block diagram showingan entire structure of
`plurality of first word lines to render a correspondingfirst
`a semiconductor memory device according to a fourth
`wordline active in response to a decoded signal.
`embodiment of the present invention.
`The semiconductor memory device further includesa first
`FIG. 17 is a block diagram showing the structure of a
`power supply, a second powersupply, and a temporary save
`logic unit of FIG. 16.
`circuit. The first power supply supplies a power supply
`FIG. 18 is a block diagram showinga structure of a flip
`voltage to the logic unit, the sense amplifier, the address
`flop circuit of FIG. 17.
`45
`buffer, the self refresh control circuit, the row decoder, and
`FIG. 19 is a circuit diagram showingastructure of a
`clocked inverter of FIG. 18.
`the plurality of first word line drivers when in a normal
`mode, and does not supply a power supply voltage to the
`FIG. 20 is a circuit diagram showingastructure of a
`logic unit, the sense amplifier, the address buffer, the self
`transfer gate of FIG. 18.
`refresh control circuit, the row decoder, and the plurality of
`FIG. 21 is a block diagram showinga structure of a serial
`first word line drivers when in a power down mode. The
`register of FIG. 16.
`second powersupply supplies a power supply voltage to the
`FIG. 22 is a timing chart for describing an operation of
`sense amplifier,
`the self refresh control circuit,
`the row
`transferring serial data from a logic unit to a DRAM unit.
`decoder and the plurality of first word line drivers when in
`FIG. 23 is a timing chart for describing an operation of
`a power down mode, and does not supply a power supply
`returning the serial data transferred to the DRAM unit to the
`voltage to the sense amplifier, the self refresh control circuit,
`logic unit.
`the row decoder, and the plurality of first word line drivers
`DESCRIPTION OF THE PREFERRED
`when in a normal mode. The temporary save circuit tem-
`EMBODIMENTS
`porarily saves the data ofthe plurality of logic circuit groups
`into the DRAM unit before a power down modeis entered.
`The semiconductor memory device does not have the data
`in the logic unit lost even when poweris not supplied to the
`logic unit during a power down mode.
`The foregoing and other objects, features, aspects and
`advantages of the present
`invention will become more
`apparent from the following detailed description of the
`present
`invention when taken in conjunction with the
`accompanying drawings.
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`Embodiments of the present invention will be described
`hereinafter with reference to the drawings. In the drawings,
`the same or corresponding component have the samerefer-
`ence characters allotted, and their description will not be
`repeated.
`
`First Embodiment
`
`Referring to FIG. 1, a semiconductor memory device
`according to a first embodiment of the present invention
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`column predecoder 14. Sense amplifier SA amplifies a data
`signal of a memory cell MC read out on bit line pair BL.
`Input/output circuit I/O transfers a data signal between the
`bit line pair BL selected by column decoder CD and global
`input/output line pair G-I/O.
`P channel MOStransistor PT1 is connected between a pin
`P1 receiving an external power supply voltage Vcc and a
`power supply node Vccl to be turned on/off in response to
`a signal /CKE whichis an inverted version of clock enable
`signal CKE. P channel MOStransistor PT2 is connected
`between a pin P2 receiving an external powersupply voltage
`Vcc and a power supply node Vcc2 to be turned on/off in
`response to clock enable signal CKE.
`Referring to the block diagram of FIG. 2 of the power
`supply system of the semiconductor memory device of FIG.
`1, the circuitry forming the semiconductor memory device is
`mainly divided into circuitry 300 required for a self refresh
`operation and circuitry 400 not required for a self refresh
`operation. Circuitry 300 required for a self refresh operation
`includes self refresh control circuit SRC, predecoder PD,
`and memory banks BANK0—BANK7ofthe semiconductor
`memory device of FIG. 1. Circuitry 400 not required for a
`self refresh operation includeslogic unit 100, control signal
`generation circuit 26, mode decoder 2, moderegister 16, row
`address latch 8, column address latch 12, bank address latch
`18, data conversion unit 22, burst address counter 28, bank
`decoder 20, row predecoder 10, and column predecoder 14.
`The semiconductor memory device enters a normal mode
`when clock enable signal CKE is at an H level. Here, P
`channel MOStransistor PT1 is off and P channel MOS
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`includes a logic unit 100 and a DRAM unit 200, and P
`channel MOStransistors PT1 and PT2, formed on the same
`chip 1000. Between logic unit 100 and DRAM unit 200 are
`transferred complementary control signals CLK and /CLK
`whichare the reference of the operation of the entire DRAM
`unit 200, a clock enable signal CKE that allows input to
`DRAM 200, a signal /CS identifying input of a command,a
`signal /RAS indicating input of a row related command, a
`signal /CASindicating input of a column related command,
`a signal /WE whichis an identification signal of read and
`write, a reference potential Vref determining the H level
`(logical high)/L level (logical
`low) of an input signal,
`address signals AOQ—-A12, bank addresses BAO-BA2 of eight
`incorporated memory banks, and input/output signals
`DQO-DQ31 of data of 32 bits.
`DRAM unit 200 does not operate when clock enable
`signal CKE is not rendered active. During this inactive
`period, DRAM unit 200 attains a power down modeora self
`refresh mode.
`
`During activation of signal ICS, a commandis recognized
`at a rising edge of a clock.
`As to address signals AO-A12, all the thirteen bits are
`used as an input of a row address, whereasten bits out of the
`thirteen bits are used for an input of a column address. Also,
`the address signals are partially used for writing into a mode
`register.
`DRAM unit 200 includes a control signal generation
`circuit 26 receiving control signals CLK and /CLK to
`generate an internal control clock signal, a mode decoder 2
`recognizing an input command, a moderegister 16 retaining
`an operation mode, a row address latch 8 receiving a row
`address, a column address latch 12 receiving a column
`address, a bank address latch 18 receiving a bank address
`signal from the bank address, and a bank decoder 20
`decoding the bank address from bank address latch 18 to
`render a corresponding bankactive.
`DRAM unit 200 further includes a self refresh control
`circuit SRC generating a refresh address in a refresh
`operation, and a predecoder PD receiving a refresh address
`from self refresh control circuit SRC to output a correspond-
`ing signal to row decoder RD.
`DRAM unit 200 further includes a row predecoder 10
`receiving an address output from row address latch 8 to
`output a corresponding signal to row decoder RD, a burst
`address counter 28 generating a column address continu-
`ously in a burst operation, and a column predecoder 14
`receiving an address output from burst address counter 28 to
`output a corresponding signal to column decoder CD.
`DRAM unit 200 further includes a data conversion unit 22
`converting the data rate between an external source of
`DRAM unit 200 and a global data bus G-I/O to transferdata,
`and memory banks BANKO-BANK7to transfer data with
`global data bus G-I/O according to the outputs of row
`predecoder 10, column predecoder 14 and bank decoder 20.
`Global data bus G-I/O transfers data with eight memory
`banks BANK0-BANK7.
`
`transistor PT2 is on. Accordingly, power supply voltage
`Vec2 from pin P2 is supplied to circuitry 300 required for a
`self refresh operation and circuitry 400 not required for a self
`refresh operation,1.e., to all the circuits in the semiconductor
`memory device. Thus, the semiconductor memory device
`operates in a normal mode.
`The semiconductor memory device enters a power down
`mode when clock enable signal CKE is at an L level. P
`channel MOStransistor PT1 is on and P channel MOS
`transistor PT2 is off. Power supply is not supplied to
`circuitry 400 that is not required for a self refresh operation.
`Therefore,
`leakage current will not be generated in the
`transistors included in such circuitry.
`As a result, current consumption is reduced in the power
`down mode. In contrast, power supply voltage Vecl from
`pin P1 is supplied to circuitry 300 required for a self refresh
`operation. A refresh operation is carried out by power supply
`voltage Vccl even during a power down mode. Therefore,
`the data of memory cell MCis retained.
`Referring to the block diagram of FIG. 3, self refresh
`control circuit SRC includes a timer circuit 310, a trigger
`pulse generation circuit 320, a cycle time count timer circuit
`330, a RAS clock generation circuit 340, an address counter
`350, and a delay circuit 360 for control. Timer circuit 310
`counts a predetermined time in response to inverted signal
`/CKE of clock enable signal CKE,self refresh set signal SR
`from mode decoder 2 shown in FIG. 1, and a timer reset
`Each of memory banks BANKO-BANK7includes a
`signal TR from address counter 350. Since timercircuit 310
`memory cell array MA, a row decoder RD, a column
`is formed of a transistor of a high threshold value, leakage
`decoder CD, a sense amplifier SA, and an input/output
`current during operation is small. Trigger pulse generation
`circuit I/O. Memory cell array MAincludesa plurality of
`memory cells MC arranged in rows and columns,a plurality
`circuit 320 generates a trigger pulse signal at the end of
`
`of word lines WLarranged in rows, andaplurality ofbit line measurementof the predetermined time by timercircuit 310.
`pairs BL arranged in columns. Row decoder RD generates a
`Cycle time count timer circuit 330 generates a cyclic pulse
`decode signal in response to a signal from row predecoder
`signal for every predetermined time in responseto a trigger
`10 or predecoder PD. Column decoder CD selects a corre-
`pulse signal from trigger pulse generation circuit 320. RAS
`sponding bit line pair BL in response to a signal from
`clock generation circuit 340 generates a RASclock signal in
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`7
`response to a cyclic pulse signal. Address counter 350
`sequentially increments the address in response to the RAS
`clock signal to output the incremented address as a refresh
`address signal, and generates a timer reset signal TR when
`one round of the address is completed. The address is reset
`by a poweron reset signal POR whenthe poweris turned on
`or by signal /CKE whichis an inverted version of the clock
`enable signal. Delay circuit 360 for control delays the RAS
`control signal to generate a word line activation signal XD,
`an equalize signal ES, and a sense amplifier activation signal
`SEN.
`
`Referring to block diagram of FIG. 4, predecoder PD is
`formed of an inverter IV and a pass transistor logic. FIG. 4
`showsan example of 8-bit input and 256-bit output. FIG. 5
`showsa passtransistor logic circuit that receives two inputs
`A and B and provides output signals Outl and /Outl out of
`the pass transistor logics of FIG. 4. Referring to the circuit
`diagram of the pass transistor logics circuit of FIG. 6, the
`pass transistor logic circuit provides inputs A, /A and inputs
`B, /B as signals Out1, /Out1 when input B is at an H level
`and an L level, respectively. The pass transistor logic circuit
`has the logic formed in a composite manner of serial
`connection and parallel connection of N channel MOS
`transistor NT, and is characterized in that the power and
`ground are absent in the pass transistor logic circuit. This
`means that no leakage current will be generated if inputs A
`and B towardsthe passtransistor logic circuit are fixed at the
`L level. Therefore, the threshold value of N channel MOS
`transistor NT forming the passtransistor logic circuit can be
`reduced significantly to allow increase in speed.
`The self refresh operation of the semiconductor memory
`device of the above structure will be described here with
`reference to FIG. 7.
`
`The power down mode is entered when clock enable
`signal CKE attains an L level. In response, address counter
`350 is reset. Address counter 350 outputs the self refresh
`address signal of the initial value. Predecoder PD selects a
`word line WL corresponding to this self refresh address
`signal.
`The self refresh mode is entered when signal /CS indi-
`cating input of a commandand signal /RASindicating input
`of a row related commandbothattain an L level at the same
`
`time. Mode decoder 2 provides an active self refresh set
`signal SR to timer circuit 310.
`In response, timer circuit 310 initiat