UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________________
`
`SAMSUNG ELECTRONICS AMERICA, INC. and
`ASUS COMPUTER INTERNATIONAL, INC.
`
`Petitioner,
`
`V.
`
`JAMES B. GOODMAN,
`
`Patent Owner,
`__________________
`
`Case IPR2017-020211
`Patent No. 6,243,315
`__________________
`
`Before BRIAN J. McNAMARA, PATRICK M. BOUCHER, and
`
`KIMBERLY McGRAW, Administrative Patent Judges.
`
`
`
`
`
`PATENT OWNER’S RESPONSE TO THE DECISION ON THE PETITION
`
`By James B. Goodman
`Patent Owner
`
`
`
`
`1 Case IPR2018-00047, filed by ASUS Computer International, Inc. has been joined with this
`proceedings.
`
`
`
`1
`
`

`

`
`
`I.
`
`
`
`RELATED CASES
`
`A final decision in this proceeding could affect the following cases pending in the U.S.
`
`District Courts in which the ‘315 Patent is asserted: Goodman v. Hewlett-Packard Co., C.A. No.
`
`16-CV-03195 (S.D. Tex.) (“HP Case”); Goodman v. ASUS Computer International, C.A. 17-
`
`CV-05542 (N.D. Cal. 05542) (Transferred from the S.D. Texas.); Goodman v. Samsung
`
`Electronics America, Inc., C.A. No. 17-CV-05539 (S.D. N.Y.); and Goodman v. Lenovo (United
`
`States) Inc., C.A. 17-CV-06782.
`
`
`
`In addition, an IPR has been instituted against the present patent, U.S. Patent No.
`
`6,423,315, by HP Inc. (Case IPR2017-01994).
`
` II.
`
`THE CLAIMED INVENTIONS OF THE ‘315 PATENT
`
`
`
`Fig. 1 of the ‘315 Patent is shown below. As stated in the ‘315 Patent at 5:41-42, “Fig. 1
`
`is a block diagram of a preferred embodiment of the low power down memory system.”
`
`
`
`2
`
`
`
`

`

`
`
`The following is independent claim 1:
`
`1. A memory system for use in a computer system, said memory system
`comprising:
`
`a plurality of volatile solid state memory devices that retain information when an
`electrical power source is applied to said memory devices within a predetermined
`voltage range and capable of being placed in a self refresh mode; said memory
`devices having address lines and control lines;
`
`a control device for selectively electrically isolating said memory devices from
`respective address lines and respective control lines so that when said
`memory devices are electrically isolated, any signals received on said
`respective address lines and respective control lines do not reach said
`memory devices; and
`
`a memory access enable control device coupled to said control device and to
`said control lines for determining when said memory system is not being
`accessed and for initiating a low power mode for said memory system
`wherein said control device electrically isolates said memory devices and
`places said memory devices in said self refresh mode, thereby reducing the
`amount of electrical energy being drawn from an electrical power supply for said
`computer system. (Emphasis added)
`
`
`
`The phrase “a control device … “ has been highlighted to draw attention to this important
`
`aspect of the claimed invention. Electrically isolating the memory devices from the respective
`
`address lines and the respective control lines so that any signals on those lines do not reach the
`
`memory devices is critical for avoiding any corruptions of the data in the memory devices from
`
`unwanted signals during the self refresh mode.
`
`
`
`The phrase “a memory access enable control device …” has been highlighted to point to
`
`the important issue of when the low power down mode for the memory system starts: It starts
`
`when the memory system is not being accessed.
`
`Claims 2-9 depend on claim 1.
`
`3
`
`
`
`
`
`
`
`
`
`

`

`
`
`Fig. 4 of the ‘315 Patent is shown below. The embodiment shown in Fig. 4 features a
`
`memory system with a backup battery to avoid a loss of data when the initial battery fails. In
`
`addition, data in the memory devices are protected against corruption when the initial battery is
`
`less than the minimum voltage to maintain the data in the memory devices. Claims 10-20 are
`
`directed to a system with battery backup.
`
`
`
`
`
`
`
`
`
`4
`
`

`

`
`
`
`
`The following is independent claim 10:
`
`10. A memory system for use in a computer system, said memory system
`comprising:
`
`a plurality of volatile solid state memory devices that retain information when an
`electrical power source having a voltage greater than a predetermined voltage is
`applied to said devices; said memory devices having address lines and control
`lines;
`
`said computer system including a first electrical power source for operating said
`computer and being capable of producing a first voltage applied to said memory
`devices;
`
`a control device for monitoring said first voltage to determine when said first
`voltage is less than said predetermined voltage and for selectively electrically
`isolating said memory devices from respective address lines and respective
`control lines so that when said memory devices are electrically isolated, any
`signals received on said respective address lines and respective control lines
`do not reach said memory devices; and
`
`a second electrical power source operable for supplying a second voltage to said
`memory devices greater than said predetermined voltage;
`
`said control device being operable for disconnecting said first electrical power
`source from said memory devices and connecting said second electrical power
`source to said memory devices when said first voltage is less than said
`predetermined voltage;
`
`whereby, data in said memory devices is preserved by said second electrical
`power source when said first electrical power source fails to maintain at least said
`predetermined voltage on said memory devices, and said memory devices are
`isolated from errant signals. (Emphasis added)
`
`The subsystem starting with “control device” has been made bold to draw attention to this
`
`particular feature. It is known in the prior art to use backup batteries and the like as an electrical
`
`power source in the event of a failure of the power source being used initially. The “control
`
`source” protects data in the memory devices when the first electrical power source is less than
`
`the minimum required for the memory devices by electrically isolating address and control lines
`
`from the memory devices so that errant signals cannot reach the memory devices and potentially
`
`
`
`5
`
`

`

`corrupt data. When the data in the memory devices is protected against errant signals, a
`
`transition from the first electrical source to the second electrical source can be made without data
`
`corruption
`
`
`
`Claims 11-20 depend on claim 10.
`
`III. THE ASSERTED GROUNDS OF UNPATENTABILITY IN THE DECISION
`
`
`
`Reference is being made herein to the Decision in the IPR dated March 9, 2018
`(“Decision”.
`
`A.
`
`The Decision States that The Petitioner cites six grounds for invalidating the claims
`in the ‘315 Patent:
`
`Ground 1: Claims 1 and 5 are unpatentable under 35 U.S.C. § 102 over U.S. Patent
`
`No. 6,327,664 (Ex. 1004, “Dell”).
`
`Ground 2: Claims 10 and 16 are unpatentable under 35 U.S.C. § 103 over Dell and
`
`U.S. Patent No. 5,590,082 (Ex. 1005, “Abe”).
`
`Ground 3: Claims 2-4 and 6-9 are unpatentable under 35 U.S.C. § 103 over Dell and
`
`JESED21-C (Ex. 1006, “JESED21-C”).
`
`Ground 4: Claims 11-15 and 17-20 are unpatentable under 35 U.S.C. § 103 over
`
`Dell, Abe, and JESED21-C.
`
`Ground 5: Claims 1 and 5 are unpatentable under 35 U.S.C. § 103 over U.S. Patent
`
`No. 6,172,928 (Ex. 1008, “Ooishi”) and U.S. Patent No. 6,144,219 (Ex. 1009,
`
`“Palaniswami”).
`
`Ground 6: Claims 10 and 16 are unpatentable under 35 U.S.C. § 103 over Ooishi,
`
`Palaniswami, and Abe.
`
`The Decision precludes any additional grounds in this IPR.
`
`6
`
`
`
`
`
`
`
`

`

`B.
`
`Overview of the Asserted References
`
`None of the descriptions of the cited references provided by the Decision are
`
`disputed.
`
`DELL (Ex. 1004)
`
`The Decision at p. 8 presents the following description of the Dell patent:
`
`
`Dell, titled “Power Management on a Memory Card Having a
`Signal Processing Element,” describes a memory module having
`individually addressable banks of memory chips that can be placed
`into a higher or lower power state by a system memory controller
`or digital signal processor (“DSP”). Ex. 1004, 1:48–63. The
`memory module of Dell is able to selectively and expeditiously
`reduce power to individual banks of memory (or portions thereof)
`when they are not being accessed. Id. at 1:40-45.
`
`ABE (Ex. 1005)
`
`
`
`The Decision at p. 9 presents the following description of the Abe patent:
`
`Abe is directed to a memory control circuit for initiating a self-
`refresh mode for a dynamic random access memory (“DRAM”)
`when the power supply voltage is lowered and for the self-refresh
`mode to consume less power. Ex. 1005, 1:5–10, 1:48–56. Abe
`discloses a main power supply and an auxiliary power supply,
`wherein the auxiliary supply is used for self-refresh functions
`when the main power supply is cut off. Id. at 3:5-8.
`
`
`
`
`
`JESD21-C (1007)
`
`The Decision determined that the JEDEC is a prior art printed publication under 35
`
`U.S.C. § 102(b). The Patent Owner is not disputing this finding. JEDEC is a specification
`
`relating to the Configuration of Solid State Memories.
`
`
`
`
`
`
`
`
`
`7
`
`

`

`
`
`
`
`
`
`
`
`OOISHI (EX. 1008)
`
`The Decision at p. 9 presented the following description of the Ooishi patent.
`
`Ooishi is directed to a semiconductor memory device that reduces
`power consumption during a self-refresh operation. Ex. 1008,
`1:41–43. The memory device of Ooishi has both a normal mode
`and a power down mode, and further includes a self-refresh circuit
`that generates a refresh address signal when in power down mode.
`Id. at 1:44–50; 1:56–58. Ooishi also discloses a first power supply
`that is used when the device is in normal mode and second power
`supply that is used when the device is in a power down mode. Id.
`at 1:64–2:11.
`
`PALANISWAMI (EX. 1009)
`
`The Decision at p. 10 presents the following description of the Palaniswami patent:
`
`Palaniswami is directed to an isolation mechanism located between
`a digital signal processor (”DSP”) and a dynamic random access
`memory (“DRAM”) controller that isolates DSP outputs from a
`DRAM controller upon occurrence of a low power condition. Ex.
`1009, Abstract, 2:65–3:15, Fig. 2. The stated goal of
`Palaniswami’s isolation mechanism is to prevent corruption of
`DRAM due to faulty DSP signals and attributable to lost or
`depleted battery supply. Id. at 2:1–5.
`
`IV. DISCUSSION
`
`
`
`
`
`A.
`
`Level of Skill in the Art
`
`The Patent Owner agrees with the statement of the Decision at p. 7 as to the level of skill
`
`for a person with ordinary skill in the art (“POSITA”): “[w]e determine that it is not necessary to
`
`state explicitly a specific level of skill as the prior art itself reflects an appropriate level of skill.
`
`See Okajima v. Bourdeau, 261 F. 3d 1350, 1355 (Fed. Cir. 2001)”
`
`
`
`
`
`B.
`
`Claim Construction
`
`The Decision at p. 7, states that the claim terms in an unexpired patent are construed in
`
`the broadest reasonable construction in light of the specification of the patent in which they
`
`appear. Citing 36 C.F.R. § 42.100(b). The Decision cites:
`
`
`
`8
`
`

`

`Consistent with the broadest reasonable construction, claim terms
`are presumed to have their ordinary and customary meaning as
`understood by a person of ordinary skill in the art in the context of
`the entire patent disclosure. In re Translogic Tech. Inc., 504 F. 3d
`1249, 1257 (Fed. Cir. 2007)
`
`The Decision points out at p. 8, last paragraph the Petitioner decided that the phrase
`
`
`
`“selectively electrically isolating said memory devices from respective address lines and
`
`respective control lines” to mean “in the context of conventional memory devices and signals is
`
`that such signals are inhibited from arriving at the given memory devices.” The Petitioner cited
`
`“Ex. 1002 ¶ 47”. The Patent Owner is not disputing the proposed claim construction from the
`
`Petitioner.
`
`
`
`It is respectfully pointed out that both HP and the Patent Owner have dealt with the issue
`
`of claim construction in Goodman v. Hewlett-Packard Co., C.A. No. 16-CV-03195 (S.D. Tex.),
`
`and both parties agreed on the claim construction for each and every term of the claims that the
`
`parties believed needed construction. See Exhibit A. In addition, the District Court accepted the
`
`claim construction as stated by the parties. See Exhibit B.
`
`C.
`
`Principles of Law
`
`Patent Owner believes that the applicable law is as follows:
`
`A claim is unpatentable under 35 U.S.C. § 103(a) if “the
`differences between the subject matter sought to be patented and
`the prior art are such that the subject matter as a whole would have
`been obvious at the time the invention was made to a person
`having ordinary skill in the art to which said subject matter
`pertains.” KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406
`(2007).
`
`The question of obviousness is resolved on the basis of underlying
`factual determinations, including: (1) the scope and content of the
`prior art; (2) any differences between the claimed subject matter
`and the prior art; (3) the level of skill in the art; and (4) objective
`evidence of nonobviousness, i.e., secondary considerations. See
`Graham v. John Deere Co, 383 U.S. 1, 17–18 (1966).
`
`9
`
`
`
`
`
`
`
`

`

`
`
`
`
`
`
`
`
`
`D.
`
`Asserted Anticipation of Claims 1 and 5 by Dell
`
`
`
`The Decision starting at p. 11 states (note that paragraphs have been labeled as
`
`“sections” for easy reference):
`
`
`
`[SECTION A]
`Petitioner contends that Dell discloses all of the limitations
`of, and therefore anticipates, claims 1 and 5 of the ’315 patent. Pet.
`12–22. For example, in mapping claim element 1a, Petitioner states
`that Dell discloses a plurality SDRAMs that necessarily include a
`“plurality of volatile solid state memory devices that retain
`information when an electrical power source is applied to said
`memory devices within a predetermined voltage range.”
`Id. at 13–14.
`
`[SECTION B]
`Petitioner also states that “memory address/control bus 16”
`has “address lines and control lines” (id. at 14–15 (citing Ex. 1004,
`2:32–37; 2:44–45, Fig. 1; Ex. 1002 ¶ 75)) and that the SDRAM
`memory devices “are capable of being placed in a self-refresh
`mode” (id. at 3:42–47, 3:56–60,
`4:11–13, 4:19–22; Ex. 1002 ¶ 74).
`
`[SECTION C]
`Petitioner also asserts Dell’s bus controller 34, which
`controls FET switch 52, is a “control device” as recited in claim
`element 1b that selectively isolates memory devices from address
`and control lines by opening the FET switch so that address and
`control signals transmitted from memory controller 28 do not reach
`the memory devices. Pet. 15–19 (citing Ex. 1004, Fig. 1, 3:42–47,
`3:30–35, 5:29–57; Ex. 1002 ¶¶ 78, 80–83).
`
`[SECTION D]
`Petitioner also argues that Dell’s memory controller 28,
`which is coupled to bus controller 34 (i.e., control device) and to
`memory address/control bus 16, is a “memory access enable
`control device” as recited in claim element 1c. Id. at 19 (citing Ex.
`1004, 2:57–60, Fig. 1). Petitioner explains that memory controller
`28 monitors activity on the SDRAM memory devices and initiates
`a low power/self-refresh mode when the devices are not being
`accessed. Id. at 20–21 (citing Ex. 1004, 1:40–45, 3:33–35, 3:42–
`
`10
`
`

`

`
`
`
`
`55; 4:13–15, 4:19–22, 5:49–57, Fig. 1; Ex. 1002 ¶¶ 85–87; see also
`Ex. 1002 ¶¶ 32, 36 (stating that sensing inactivity and initiating
`self-refresh mode in response was a conventional use of DRAM
`memory controller in the prior art).
`
`[SECTION E]
`Petitioner also states that Dell discloses the limitations of
`dependent claim 5, which requires the memory devices of claim 1
`to be DRAM semiconductor microchips. Id. at 22; Ex. 1004 at
`2:32–37; Ex. 1002 ¶ 90.
`
`RESPONSE
`
` Sections A and B are not disputed.
`
`Section C is disputed because opening FET switch 52 only isolated address and control
`
`lines from the system memory controller, not the DSP. Many tasks of the DSP are accomplished
`
`when the memory module is not being addressed for either a read or write function by the CPU
`
`memory controller 28. Id., 3:41. Both the system controller and the DSP have access to both
`
`banks of memory chips and both sections thereof can rewrite data and change the condition of
`
`the chips when accessed by either the system memory controller, or the DSP. Id., 4:29-35, and
`
`4:57-61. In addition, Fig. 2 of Dell is a flow diagram of the operation of the DSP 36 access to
`
`system memory bank 13a-13b showing that DSP can deactivate the FET switches. Id., 5:58-67.
`
`Thus, the open FET does not, in fact, isolate all of the memory devices as urged by
`
`Petitioner.
`
`Section D is disputed because the portions of the Dell patent relied on for support by the
`
`Petitioner do not, in fact, support the conclusions urged by the Petitioner. Petitioner states that
`
`Dell’s bus controller 34, which controls FET switch 52, is a “control device” as recited in claim
`
`1 of the ‘315 Patent that selectively isolates memory devices from address and control lines.
`
`Petitioner, however, ignores the fact that when the FET switch is open, the DSP can still reach
`
`
`
`11
`
`

`

`the memory devices. See Fig. 1 showing a flow diagram for the DSP access to system memory,
`
`and note that the FET switches are deactivated for the DSP to access the system memory in
`
`contrast to Petitioner’s arguments. As noted in the discussion Section C above, all memory can
`
`be access by both the system memory controller and the DSP.
`
`Section E is disputed because Dell fails to render claim 1 unpatentable, and dependent
`
`claim 5 is also not met by Dell.
`
`The Decision at pp. 12-13 adds the following comment in response to the Patent Owner’s
`
`Preliminary Response:
`
`Patent Owner responds that Dell
`does not disclose the “control device” and
`“memory access enable control device” of
`claim 1 because Dell does not disclose
`“placing all banks in a reduced power state
`at the same time, in contrast to the ’315
`Patent” and because Dell allows “a control
`line, CKE to remain connected to a
`memory bank even when the memory
`bank is in a power down state.” Prelim.
`Resp. 10, 11 (citing Ex. 1004, 1:40–45,
`1:48–60, 3:18–25, 6:11–13, 6:29–38,
`6:55–7:9).
`record, we are not
`this
`On
`persuaded by Patent Owner’s arguments.
`Claim 1 of the ’315 patent does not recite
`that all memory banks be placed into a
`reduced power state at the same time or
`that all memory devices are electrically
`isolated from respective address and
`control lines. Significantly, the preferred
`embodiments of the ’315 patent do not
`appear to isolate the memory devices from
`all address and control
`lines.
` For
`example, the ’315 patent states that the
`control device shown
`in Figure 1
`electrically isolates control bus 22 and
`address bus 17 from the memory devices,
`but does not state that RAS and WE
`
`12
`
`
`
`

`

`lines 26, 28 are electrically
`control
`isolated from the memory devices. Ex.
`1001, Fig. 4, 5:60–67; see also id. at 9:24–
`26 (stating that control center 115 of
`Figure 4 electrically isolates memory
`devices 5 isolated from control lines 122
`and address lines 117, but not stating that
`the memory devices are isolated from
`RAS and WE Control Lines).
`
`
`
`RESPONSE
`
`Decision indicates that the Board is not convinced as to two requirements asserted by the
`
`
`
`
`
`Patent Owner: The first is that claim 1 of the ‘315 Patent requires all of the memory banks to be
`
`placed into a reduced power state at the same time or all memory devices are electrically isolated
`
`from respective address and control lines.
`
`
`
`Claim 1 at line 19-20 introduces the claimed “memory devices” as being a “plurality of
`
`volatile solid state memory devices”. Each and every reference in claim 1 to the memory is to
`
`the “memory devices”, all of the memory banks. See Id. 13:20, 22, 24, 26, 28, 30, and 36 (which
`
`states “said memory devices in said self refresh mode”).
`
`
`
`Claim 1 is fully supported by the specification. As to the term “memory devices”, all of
`
`the memory is included: Id., 4:11-24 uses the term “memory devices” in describing the
`
`invention and identifying what is sent to self refresh, the entire memory. See also Id., 3:25-30,
`
`3:46-62; 6:21-34; 5:41-67 in connection with Fig. 1; and 6:30-34 as well as part of the detailed
`
`description of the figures.
`
`
`
`Therefore, claim 1 requires all of the memory devices, memory banks, to go into self
`
`refresh, not a portion of the memory devices.
`
`
`
`13
`
`

`

`
`
`The other issue raised by the Board is that the ‘315 Patent does not appear to isolate all
`
`address and control lines.
`
`
`
`It is respectfully submitted that the ‘315 Patent makes it clear that the claimed invention
`
`is to protect the data in the memory devices during self refresh from errant signals which might
`
`reach the memory devices. See Id., 4:11-24, particularly the statement at 5:63-67: “By isolating
`
`the memory devices from the control buss and address buss 17 the control device 15 prevents
`
`errant signals from erroneously changing or affecting data being retained by the memory devices
`
`5.
`
`
`
`The Board states that it does not appear that all address and control lines are isolated as
`
`set forth in Claim 1. In support of this position, the Board points to Fig. 1 and the specification
`
`of the ‘315 Patent showing that control bus 22 and address bus 17 are electrically isolated, but
`
`then points to the RAS and WE, 26, 28 control lines and states that the ‘315 Patent does not
`
`explicitly disclose that the RAS and WE 26, 28 control lines are electrically isolated.
`
`
`
`It is respectfully pointed out that Fig. 1 shows that the RAS and WE control lines 26, 28
`
`control lines communicate with the memory access enable control 30 in order to give notice
`
`when the memory devices 5 are not being accessed, in accordance with claim 1. Id., 6:1-14. In
`
`addition, the RAS and WE 26, 28 go to control device 15 not the memory devices 5. Thus,
`
`control device 15 isolate the RAS 26 and WE 28 control lines from the memory devices 5
`
`consistent within the requirements of the ‘315 Patent, particularly the claims 1-9.
`
`
`
`There is a third issue not directly addressed by the Petitioner, but identified at p. 13 of the
`
`Decision. Dell allows the CKE (clock enable) line to remain connected to a memory bank even
`
`when the memory bank is in a power down state. The CKE line is usually a “control line” in
`
`memory systems because, in part, the CKE line can drive the memory system into a lower power
`
`
`
`14
`
`

`

`mode, such as the self refresh mode and raise the power mode to the normal state by CKE
`
`turning the clock off and then on during enter and exit.
`
`
`
`Dell uses the two separate clock enabled lines designated as CKE lines: “clock enable
`
`(CKE) line 24” Id., 2:44-47; and “clock enable line 14” Id. 2:48-51. Dell uses the clock enable
`
`line 24 to control the system memory:
`
`The clock enable line 24 has four branches 54a-54d
`connected to the banks of memory chips 12a-12h
`and 13a-13h through FET switches 56a-56d to
`provide individual clock enable signals directly to
`the chips 12a-12h and 13a-13h without going
`through the bus controller 34 so that the chips can
`be addressed when they are in the lowest power
`state as will be described presently. Id., 3:18-25.
`
`Memory Module with more than one 'physical' memory
`banks (e.g. 12a-12h and 13a-13h), with at least one physical
`bank (e.g. 12a-12h) allocated to the DSP, and the remaining
`physical bank(s) (e.g. 13a-13h) allocated to the system.
`Id., 6:2-7
`
`
`
`
`
`The second clock enable line does not appear in the figures and is referred to as a “local
`
`CKE”:
`
`Local CKE control: The physical memory space allocated
`to the DSP, is placed in the lowest power mode possible,
`when not in use. (For this example, this is defined as one
`physical bank of memory assigned to the DSP, with any
`remaining physical banks of memory assigned to the
`system.) Accesses to all other physical memory banks on the
`memory card 8 are still permitted (as long as those banks are
`in the appropriate state), since the bus controller will ensure
`the DSP memory is not disturbed (CKE held
`inactive). Id., 6:29-38
`
`
`
`
`
`15
`
`

`

`The system CKE line are used to select a memory bank. Id., 6:11-14; The system CKE
`
`line, however, does not directly affect the DSP memory. Id., 6:22-28, and the DSP can place the
`
`memory under its control into a lowest power mode using the local CKE. Id., 5:29-38.
`
`The respective CKE lines control the memory mode as for memory banks as to whether a
`
`bank can be addressed, or unavailable when the bank is in its lowest power state such as self
`
`refresh. Under the claim construction shown in Ex. 2, p. 1, each of the CKE lines is a control line
`
`because each CKE line determines the memory mode.
`
`Dell discloses that when a memory bank is in its power down mode, all receivers are
`
`deactivated except for the clock enable. Id., 4:1-3; 4:11-15
`
`As shown above, claim 1 of the ‘315 Patent requires all address and control lines to be
`
`electrically isolated from the memory devices 5 to avoid erratic signals from corrupting data in
`
`the memory devices 5.
`
`Thus, the operation disclosed by Dell does not anticipate claim 1 or 5 of the ‘315 Patent.
`
`In addition, Dell does not suggest claim 1 or 5.
`
`E.
`
`Asserted Obviousness of Claims 10 and 16 over Dell and Abe
`
`The Decision starting at p. 14 states (note that paragraphs have been labeled as
`
`“sections” for easy reference):
`
`[SECTION A]
`Petitioner argues independent claim 10 and dependent
`claim 16 would have been obvious over the combined teachings of
`Dell and Abe. Pet. 23– 37. Relying on arguments similar to those
`presented with respect to claim 1, Petitioner argues Dell teaches
`the limitations of claim 10 requiring “a plurality of volatile solid
`state memory devices having “address lines and control lines, “a
`control device” for monitoring voltage and for “selectively
`electrically isolating [the] memory devices from respective address
`
`
`
`16
`
`

`

`lines and respective control lines” so that signals on the address
`and control lines do not reach the memory devices. Id. at 26–27,
`30–32.
`
`[SECTION B]
`Petitioner also asserts that Abe teaches a “first electrical
`power source” (e.g., main power supply 1) and a “second electrical
`power source” (e.g., auxiliary power supply 2 that provides power
`to the DRAM when the main power supply is cut off). Id. at 23,
`27–28 (citing Ex. 1005, Fig. 1, 1:48–56, 2:55–62; Ex. 1002 ¶¶
`129–130); see also id. at 23 (stating Abe also teaches a memory
`control circuit for initiating self-refresh mode for a DRAM when
`the power supply voltage is lowered and for the self-refresh mode
`to consume less power).
`
`[SECTION C]
`Petitioner further contends that the combination of Abe’s
`power supply monitors and diodes with the bus controller 34 and
`FET 52 of Dell teaches the control device of claim element 10c.
`Id. at 29–32. For example,
`
`[SECTION D]
`Petitioner contends that Abe’s power supply monitors
`detect when the “first voltage is less than the predetermined
`voltage.” Id. at 29–30 (citing Ex. 1005, 3:20–26, 3:40–57, 3:57–
`60; Ex. 1002 ¶ 134) and that Abe’s diodes switch between the
`main and auxiliary power supply (i.e., “disconnect[ the] first
`electrical power source . . . and connect[ the] second electrical
`power source to the memory devices when the first voltage is less
`than [a] predetermined voltage.” Id. at 34–35 (citing Ex. 1005,
`Fig. 1, 3:5–19).
`
`[SECTION E]
`Petitioner further contends that Dell’s bus controller 34 and
`FET switch 52 “selectively electrically isolate the memory devices
`from respective address and control lines” and that it would have
`been obvious to substitute the bus controller 34 and FET switch 52
`of Dell into the DRAM of Abe in order to inhibit address and
`control signals from reaching the memory devices. Id. at 30–31
`(citing Ex. 1002 ¶ 136).
`
`
`
`
`
`
`
`
`
`
`
`17
`
`

`

`
`
`RESPONSE
`
`Section A is disputed because the statement asserted by Petitioner that Dell teaches, “a
`
`control device” for monitoring voltage and for “selectively electrically isolating [the] memory
`
`devices from respective address lines and respective control lines” is not found anywhere in Dell.
`
`That is, Dell has no reason to monitor the voltage so it is logical that such language does not
`
`appear in Dell. In addition, the failure of Dell to anticipate or render claim 1 obvious limits the
`
`applicability of Dell to Abe.
`
`
`
`
`
`Section B is not disputed.
`
`Section C is disputed because there is not no technical basis provided for combining the
`
`technical aspects of Dell and Abe other than the Expert’s statement that it would have been
`
`obvious. Petition, p. 31. It is respectfully noted that the Expert has left this issue open without
`
`any proposed technical explanation for actually combining the teachings of Dell and Abe.
`
`
`
`
`
`
`
`Section D is not disputed.
`
`Section E is disputed for the same reasons given above for Section C.
`
`In view of the foregoing, Dell combined with Abe fails to render claims 10 and 16
`
`obvious.
`
`F.
`
`Asserted Obviousness of Dependent Claims 2-4, 11-15, and 17-20
`
`
`
`The Decision at p. 15 states:
`
`Claims 2–4 and 6–9 depend directly or indirectly from claim 1 and
`claims 11–15 and 17–20 depend directly or indirectly from claim
`10. Petitioner contends JESD21–C teaches the additional
`limitations of these claims, and therefore, claims 2–4 and 6–9 are
`unpatentable under § 103 over Dell and JESD21-C and that claims
`11–15 and 17–20 unpatentable under § 103 over Dell, Abe, and
`
`18
`
`
`
`
`
`
`
`

`

`JESD21-C. Specifically, Petitioner asserts JESD21C teaches the
`claim limitations requiring: compatibility with a JEDEC industry
`standard 144 PIN SODIMM connector (e.g., claims 2, 6, 12, 17),
`compatibility with a JEDEC industry standard 168 PIN DIMM
`connector (claims 3, 8, 14, 19), JEDEC standard serial presence
`detect circuitry (claims 4, 7, 9, 13, 15, and 20) and compatibility
`with a JEDEC industry standard 72 PIN SIMM connector (claims
`11, 18). Pet. 8–9, 37–48.
`
`
`
`Petitioner relies on JEDEC21-C to teach the additional limitations of the dependent
`
`claims assuming that Petitioner has established that Dell and Abe have anticipated, or rendered
`
`obvious claims 1, 5, 10, and 16. As shown above, Petitioner has failed to show that claims 1, 5,
`
`10, and/or 16 are unpatentable. Hence, JEDEC21-C fails to add the necessary teaches as to 2-4,
`
`11-15, and 17-20.
`
`
`
`
`
`G.
`
`Asserted Obviousness of Claims 1 and 5 over Ooishi and Palaniswami
`
`The Decision starting at p. 14 states (note that paragraphs have been labeled as
`
`“sections” for easy reference):
`
`[SECTION A]
`Petitioner asserts that claims 1 and 5 are unpatentable under 35
`U.S.C. § 103 over Ooishi and Palaniswami. Pet. 49–65. Petitioner
`asserts that the semiconductor memory device of Ooishi can be a
`DRAM having a plurality of volatile solid state memory devices
`that are capable of being placed in a self-refresh mode, as well as
`address and control lines, as recited in claim element 1a. Pet. 52–
`55 (citing, inter alia, Ex. 1008, 1:44–50, 1:56–58,
`3:18–26, 5:3–15, 5:38–41).
`
`[SECTION B]
`Petitioner contends that Ooishi’s teaching that, in the power down
`mode, power is not supplied to circuitry that is not required for a
`self-refresh operation, renders obvious the “control device”
`limitation of claim element 1b. Id. at 56–57.
`
`[SECTION C]
`Petitioner states that a POSITA would understand that because the
`components that connect to the address and control signals to the
`DRAM are not supplied with power, the address and control
`
`
`
`19
`
`

`

`signals are electrically isolated from the DRAM during the self-
`refresh mode. Id. (citing Ex. 1002 ¶ 101–102).
`
`[SECTION D]
`Petitioner further states that Palaniswami’s “isolation mechanism”
`20 is also a control device because the isolation mechanism
`selectively isolates DRAM 6 from output signals from digital
`signal processor (“DSP”) 4. Id. at 57–59 (citing Ex. 1009, 2:65–
`3:5, 3:8–14; Ex. 1002 ¶¶103–105.
`[SECTION E]
`Petitioner contends that a POSITA would have been motivated to
`combine the isolation mechanism of Palaniswami with the DRAM
`and address/control signals of Ooishi given Ooishi’s explicit
`suggestion that the DRAM can be isolated from control and
`address signals in low-power situations. Id. at 59 (citing Ex. 1002
`¶ 107; Ex. 1008, 6:23–28, 6:38–42). Petitioner contends that
`Ooishi’s “mode decoder” acts as the “memory access enable
`control device” of claim element