Trials@uspto.gov
`571-272-7822
`
`Paper 6
`Entered February 11, 2016
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SMART MODULAR TECHNOLOGIES, INC.,
`Petitioner,
`
`v.
`
`JAMES B. GOODMAN,
`Patent Owner.
`____________
`
`Case IPR2015-01675
`Patent 6,243,315 B1
`____________
`
`Before BRIAN J. MCNAMARA, PATRICK M. BOUCHER, and
`GARTH D. BAER, Administrative Patent Judges.
`
`BAER, Administrative Patent Judge.
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`HP Exhibit 1010 - Page 1
`
`
`571-272-7822
`
`Paper 6
`Entered February 11, 2016
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SMART MODULAR TECHNOLOGIES, INC.,
`Petitioner,
`
`v.
`
`JAMES B. GOODMAN,
`Patent Owner.
`____________
`
`Case IPR2015-01675
`Patent 6,243,315 B1
`____________
`
`Before BRIAN J. MCNAMARA, PATRICK M. BOUCHER, and
`GARTH D. BAER, Administrative Patent Judges.
`
`BAER, Administrative Patent Judge.
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`HP Exhibit 1010 - Page 1
`
`
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`Case IPR2015-01675
`Patent 6,243,315 B1
`
`Smart Modular Technologies, Inc. (“Petitioner”) filed a Petition
`
`(Paper 1, “Pet.”) requesting inter partes review of claims 1, 5, 10, and 16
`
`(“the challenged claims”) of U.S. Patent No. 6,243,315 B1 (Ex. 1001, “the
`
`’315 patent”). James B. Goodman (“Patent Owner”) did not file a
`
`Preliminary Response.
`
`Pursuant to 35 U.S.C. § 314(a), an inter partes review may not be
`
`instituted unless “the information presented in the petition . . . and any
`
`response . . . shows that there is a reasonable likelihood that the petitioner
`
`would prevail with respect to at least 1 of the claims challenged in the
`
`petition.” As set forth below, we conclude that there is a reasonable
`
`likelihood that Petitioner would prevail in establishing the unpatentability of
`
`the challenged claims. Therefore, we institute inter partes review of the
`
`challenged claims.
`
`I. BACKGROUND
`
`A. RELATED PROCEEDINGS
`
`The parties identify Case No. 4:14-cv-01380 pending in the Southern
`
`District of Texas as a related matter involving the same parties and the ’315
`
`patent. Paper 1, 1–2; Paper 5, 2.
`
`B. THE ’315 PATENT
`
`The ’315 patent is directed to volatile memory devices. Ex. 1001,
`
`Abstract. Volatile memory devices “retain the contents of their memory
`
`states when electrical power is provided and maintained on the devices,” but
`
`“[w]henever electrical power is removed from the devices, the memory
`
`contents of the device [are] lost and irretrievable.” Id. at 2:54–58.
`
`The ’315 patent’s Fig. 4 is reproduced below:
`
`2
`
`HP Exhibit 1010 - Page 2
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`
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`Case IPR2015-01675
`Patent 6,243,315 B1
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`“FIG. 4 is a block diagram of a non-volatile memory system according to the
`
`invention.” Ex. 1001, 4:41–42.
`
`According to the ’315 patent:
`
`The invention prevents the loss of data due to unexpected
`power outages and also prevents errant control and address
`signals to the memory devices by monitoring the input
`electrical power source to the memory devices for acceptable
`conditions, and electrically isolating the memory devices from
`signals received on the control lines and address lines and
`switching to an alternate internal electrical power source,
`typically a battery, whenever the input power source is
`unacceptable.
`
`Ex. 1001, 3:15–24. The ’315 patent explains further that the system
`
`“maintains the integrity of the data retained by the memory devices by
`
`isolating the devices from the external power source, control lines and
`
`address lines and placing the memory devices into a power down self-refresh
`
`mode which will maintain the data using a minimum of electrical power.”
`
`Id. at 3:25–30.
`
`3
`
`HP Exhibit 1010 - Page 3
`
`
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`Case IPR2015-01675
`Patent 6,243,315 B1
`
`
`
`
`Claims 1 and 10 (reproduced below) are illustrative of the claimed
`
`C. ILLUSTRATIVE CLAIMS
`
`subject matter.
`
`1. A memory system for use in a computer system, said
`memory system comprising:
`
`a plurality of volatile solid state memory devices that retain
`information when an electrical power source is applied to said
`memory devices within a predetermined voltage range and
`capable of being placed in a self refresh mode; said memory
`devices having address lines and control lines;
`
`a control device for selectively electrically isolating said
`memory devices from respective address lines and respective
`control lines so that when said memory devices are electrically
`isolated, any signals received on said respective address lines
`and respective control lines do not reach said memory devices;
`and
`
`a memory access enable control device coupled to said control
`device and to said control lines for determining when said
`memory system is not being accessed and for initiating a low
`power mode for said memory system wherein said control
`device electrically isolates said memory devices and places said
`memory devices in said self refresh mode, thereby reducing the
`amount of electrical energy being drawn from an electrical
`power supply for said computer system.
`
`
`
`Ex. 1001, 13:18–40.
`
`10. A memory system for use in a computer system, said
`memory system comprising:
`
`a plurality of volatile solid state memory devices that retain
`information when an electrical power source having a voltage
`greater than a predetermined voltage is applied to said devices;
`said memory devices having address lines and control lines;
`
`said computer system including a first electrical power source
`for operating said computer and being capable of producing a
`first voltage applied to said memory devices;
`
`
`
`4
`
`HP Exhibit 1010 - Page 4
`
`
`
`Case IPR2015-01675
`Patent 6,243,315 B1
`
`
`a control device for monitoring said first voltage to determine
`when said first voltage is less than said predetermined voltage
`and for selectively electrically isolating said memory devices
`from respective address lines and respective control lines so
`that when said memory devices are electrically isolated, any
`signals received on said respective address lines and respective
`control lines do not reach said memory devices; and
`
`a second electrical power source operable for supplying a
`second voltage to said memory devices greater than said
`predetermined voltage;
`
`said control device being operable for disconnecting said first
`electrical power source from said memory devices and
`connecting said second electrical power source to said memory
`devices when said first voltage is less than said predetermined
`voltage;
`
`whereby, data in said memory devices is preserved by said
`second electrical power source when said first electrical power
`source fails to maintain at least said predetermined voltage on
`said memory devices, and said memory devices are isolated
`from errant signals.
`
`Ex. 1001, 13:65–14:32.
`
`D. ASSERTED PRIOR ART
`
`The Petition relies on a supporting Declaration from Dr. Nader
`
`Bagherzadeh (Ex. 1002), as well as the following prior art references:
`
`U.S. Patent No. 5,600,605 (issued Feb. 4, 1997) (Ex. 1004, “Schaefer”);
`U.S. Patent No. 5,793,776 (issued Aug. 11, 1998) (Ex. 1005, “Qureshi”);
`U.S. Patent No. 5,204,840 (issued Apr. 20, 1993) (Ex. 1006, “Mazur”).
`
`
`E. ASSERTED GROUNDS OF UNPATENTABILITY
`
`Petitioner asserts the following grounds of unpatentability. Pet. 5.
`
`References
`Schaefer and Qureshi
`Schaefer, Qureshi, and Mazur
`
`Challenged Claims
`Basis
`§ 103(a) 1 and 5
`§ 103(a) 10 and 16
`
`
`
`5
`
`HP Exhibit 1010 - Page 5
`
`
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`Case IPR2015-01675
`Patent 6,243,315 B1
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`
`II. ANALYSIS
`
`A. CLAIM CONSTRUCTION
`
`Petitioner asserts that we should construe several claim limitations to
`
`mirror Patent Owner’s infringement allegations in the related district court
`
`proceeding in which “Patent Owner alleges that the ‘315 patent’s claims
`
`encompass any system made in accordance with the [Joint Electron Device
`
`Engineering Council] standards,” Pet. 13; see id. at 12–19. For example,
`
`Petitioner asserts that we should construe “[a] memory system for use in a
`
`computer system” as “a JEDEC-compliant system with memory devices
`
`connected to a memory controller,” id. at 14, and we should construe a
`
`“plurality of volatile solid state memory devices” as “more than one bank of
`
`JEDEC-compliant memory,” id. at 15. We decline to adopt Petitioner’s
`
`asserted constructions for this Decision, however, because we see no reason
`
`why compliance with the JEDEC standard has any bearing on the issues
`
`before us in this case—Petitioner’s asserted unpatentability challenges. See
`
`Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir.
`
`1999) (“[O]nly those terms need be construed that are in controversy, and
`
`only to the extent necessary to resolve the controversy.”). Based on the
`
`current record, we conclude that no claim construction is necessary for our
`
`determination of whether to institute inter partes review of the challenged
`
`claims.
`
`1. Schaefer (Ex. 1004)
`
`B. ASSERTED PRIOR ART
`
`Schaefer describes a volatile memory device “for storing data and
`
`responsive to command signals.” Ex. 1004, 1:60. Schaefer includes a
`
`command decoder that “controls the various circuitry of SDRAM based on
`
`
`
`6
`
`HP Exhibit 1010 - Page 6
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`
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`Case IPR2015-01675
`Patent 6,243,315 B1
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`decoded commands such as during controlled reads or writes.” Id. at 3:35–
`
`37 (reference numerals omitted). Schaefer explains that the memory device
`
`includes address and control lines, see id. at 3:30–33, and discloses a
`
`“SELF-REFRESH” command for the devices, id. at 3:60–61. According to
`
`Schaeffer, “[a]ll the input and output signals of SDRAM, with the exception
`
`of the CKE input signal during power down and self refresh modes, are
`
`synchronized to the active going edge . . . of the CLK signal.” Id. at 3:20–25
`
`(reference numerals omitted). Schaefer notes that refresh commands “are
`
`performed . . . in a manner known in the art to refresh the memory arrays.”
`
`Id. at 3:61–65. Schaffer notes also that “[i]n one preferred embodiment of
`
`the present invention, the memory device is a synchronous dynamic random
`
`access memory (SDRAM).” Id. at 2:33–35.
`
`2. Qureshi (Ex. 1005)
`
`Qureshi describes a process in which “memory such as SDRAMs are
`
`put into self refresh mode.” Ex. 1005, 1:63–64. Qureshi explains that
`
`“[o]nce the self refresh mode is entered, SDRAM ignores all inputs other
`
`than a CKE (clock enable) pin while in self refresh state.” Id. at 5:49–51
`
`(reference numerals omitted). Qureshi characterizes self refresh mode as
`
`“preferred for data retention and low power operation.” Id. at 1:65–67.
`
`3. Mazur (Ex. 1006)
`
`Mazur teaches a process “for preserving the RAM of an externally
`
`powered microprocessor on the occasion of a loss in external power.” Ex.
`
`1006, Abstract. According to Mazur, “[w]hen the power loss is detected, a
`
`signal is generated which initiates a sequence to isolate the RAM and refresh
`
`it with an independent power supply,” e.g., a rechargeable battery. Id. at
`
`Abstract, see 2:8–10.
`
`
`
`7
`
`HP Exhibit 1010 - Page 7
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`
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`Case IPR2015-01675
`Patent 6,243,315 B1
`
`
`C. ASSERTED GROUNDS
`
`1. Ground 1: Claims 1 and 5 as Obvious over Schaefer and Qureshi
`
`Petitioner contends that claims 1 and 5 would have been obvious over
`
`the combined teachings of Schaeffer and Qureshi. Pet. 15–27, 31–40. For
`
`example, in mapping independent claim 1, Petitioner explains that Schaefer
`
`discloses a plurality of volatile solid state memory devices that retain
`
`information when powered. Pet. 31–34 (citing Ex. 1004, 2:33–35, 2:36–37,
`
`3:13–16). Petitioner explains also that Schaefer’s memory has address and
`
`control lines, Pet. 34–35 (citing Ex. 1004, 3:30–33, 4:19–21), and is capable
`
`of being placed in a self refresh mode, Pet. 34 (citing Ex. 1004, 3:58–61).
`
`According to Petitioner, Schaefer and Qureshi both teach a self refresh mode
`
`in which SDRAM is electrically isolated from its address and control lines,
`
`such that signals received on those lines are ignored. Pet. 35–36 (citing Ex.
`
`1005, Abstract, 1:65–2:2, 5:49–51; Ex. 1004, 6:56–58). Petitioner asserts
`
`that the combination of Schaefer and Qureshi teaches a “memory access
`
`enable device” that decodes commands from a memory controller “so as to
`
`determine which memory bank should be addressed, including decoding
`
`Qureshi’s signal that places Schaefer’s JEDEC-compliant SDRAM into
`
`power down or self refresh mode, where all access signals are ignored.” Pet.
`
`36–38 (citing Ex. 1005, Abstract, 1:65–2:2, 5:49–51, Fig. 1; Ex. 1004, 3:20–
`
`25, 3:28–42, Fig. 1). Petitioner notes also that Qureshi teaches that the self
`
`refresh mode “is preferred for data retention and low power operation.” Pet.
`
`39 (quoting Ex. 1005, 1:65–67). According to Petitioner, the combination of
`
`Schaefer and Qureshi teaches DRAM semiconductor microchips—the
`
`additional limitation in dependent claim 5—because both references “pertain
`
`
`
`8
`
`HP Exhibit 1010 - Page 8
`
`
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`Case IPR2015-01675
`Patent 6,243,315 B1
`
`to SDRAM, which is a subset of the DRAM semiconductor microchip.”
`
`Pet. 39 (citing Ex. 1002 ¶ 63).
`
`In addition, the Petition explains, with relevant support from
`
`Petitioner’s Declarant, that combining Schaefer and Qureshi would have
`
`been obvious because one skilled in the art “would seek to use the memory
`
`controller of Qureshi to place the DRAM memory of Schaefer into the low
`
`power self-refresh mode so that existing data may be retained, while other
`
`signals may be ignored, and the amount of power consumed from the
`
`computer system is reduced.” Pet. 23 (citing Ex. 1002 ¶¶ 48–51).
`
`We note that Patent Owner has not, at this stage of the proceeding,
`
`addressed Petitioner’s analysis and supporting evidence. Based on the
`
`analysis above, we find, for purposes of this Decision, that Petitioner (1) has
`
`made an adequate showing that the combination of Schaefer and Qureshi
`
`teaches or suggests each limitation in claims 1 and 5, and (2) has articulated
`
`an adequate rationale why one of skill in the art would have combined the
`
`various aspects of Schaefer and Qureshi. Thus, on the current record, we
`
`determine that Petitioner has set forth a reasonable likelihood of succeeding
`
`on its obviousness challenge to claims 1 and 5.
`
`2. Ground 2: Claims 10 and 16 as Obvious over Schaefer, Qureshi, and
`Mazur
`
`Petitioner contends that claims 10 and 16 would have been obvious
`
`over the combined teachings of Schaeffer, Qureshi, and Mazur. Pet. 27–29,
`
`40–47. For example, in addition to referencing several elements already
`
`identified for claim 1, Petitioner explains that Mazur discloses memory
`
`devices that retain information when voltage is applied above a
`
`predetermined threshold. Pet. 40–41 (citing Ex. 1006, 5:11–15, 5:36–39,
`
`3:9–16). Petitioner explains also that Mazur teaches a first power source
`
`
`
`9
`
`HP Exhibit 1010 - Page 9
`
`
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`Case IPR2015-01675
`Patent 6,243,315 B1
`
`(i.e., the computer’s power supply), that is monitored so that when the
`
`voltage supplied from that source drops below the predetermined threshold,
`
`“the control device selectively electrically isolates the memory devices from
`
`the respective address and control lines.” Pet. 41–44 (citing Ex. 1006, 3:9–
`
`16, 4:17–32, 5:11–15, 5:36–39, Fig. 1). According to Petitioner, Mazur
`
`discloses a second electrical power source (i.e. a rechargeable battery) for
`
`supplying a second voltage to the memory device, as well as a power switch-
`
`over circuit for switching from the computer power supply to the
`
`rechargeable battery when the computer power supply falls below the
`
`threshold, thus isolating the volatile memory from errant signals and
`
`preventing corruption. Pet. 44–47 (citing Ex. 1006, 5:11–15, 4:2–6, 4:17–
`
`32, 3:9–16, 5:36–39, Fig. 1).
`
`In addition, Petitioner explains, with relevant support from its
`
`Declarant, that combining Mazur with the relevant teachings from Schaefer
`
`and Qureshi would have been obvious because one skilled in the art “would
`
`recognize that [Qureshi’s] low power mode may be supported by a battery
`
`backup instead of the primary power source, thereby enabling failure of the
`
`primary power source without the need for resetting any components.”
`
`Pet. 28 (citing Ex. 1002 ¶ 67).
`
`We note that Patent Owner has not, at this stage of the proceeding,
`
`addressed Petitioner’s analysis and supporting evidence. Based on the
`
`analysis above, we find, for purposes of this Decision, that Petitioner (1) has
`
`made an adequate showing that the combination of Schaefer, Qureshi, and
`
`Mazur teaches or suggests each limitation in claims 10 and 16, and (2) has
`
`articulated adequate rationale explaining why one of skill in the art would
`
`have combined the relevant aspects of Mazur with Schaefer and Qureshi.
`
`
`
`10
`
`HP Exhibit 1010 - Page 10
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`
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`Case IPR2015-01675
`Patent 6,243,315 B1
`
`Thus, on the current record, we determine that Petitioner has set forth a
`
`reasonable likelihood of succeeding on its obviousness challenge to claims
`
`10 and 16.
`
`III. CONCLUSION
`
`For the foregoing reasons, we determine that the information
`
`presented in the Petition establishes a reasonable likelihood that Petitioner
`
`would prevail in showing the challenged claims unpatentable. Any
`
`discussion of facts in this Decision is made only for the purposes of
`
`institution of inter partes review and is not dispositive of any issue related to
`
`any ground on which we institute review. The Board’s final determination
`
`will be based on the record as fully developed during trial.
`
`Accordingly, it is:
`
`IV. ORDER
`
`ORDERED that, pursuant to 35 U.S.C. § 314(a), an inter partes
`
`review of claims 1, 5, 10, and 16 of the ’315 patent is instituted,
`
`commencing on the entry date of this Decision;
`
`FURTHER ORDERED that, pursuant to 35 U.S.C. § 314(c) and
`
`37 C.F.R. § 42.4, notice is hereby given of the institution of a trial;
`
`FURTHER ORDERED that the trial is limited to the following
`
`grounds of unpatentability:
`
`A. claims 1 and 5 as unpatentable under 35 U.S.C. § 103(a) over
`
`Schaefer and Qureshi and
`
`B. claims 10 and 16 as unpatentable under 35 U.S.C. § 103(a) over
`
`Schaefer, Qureshi, and Mazur; and
`
`
`
`11
`
`HP Exhibit 1010 - Page 11
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`
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`Case IPR2015-01675
`Patent 6,243,315 B1
`
`
`FURTHER ORDERED that no other grounds are authorized for inter
`
`partes review.
`
`
`
`12
`
`HP Exhibit 1010 - Page 12
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`
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`Case IPR2015-01675
`Patent 6,243,315 B1
`
`
`PETITIONER:
`
`Michael Heafey
`mheafey@kslaw.com
`
`Sanjiva Reddy
`sreddy@kslaw.com
`
`
`
`PATENT OWNER:
`
`David Fink
`texascowboy6@gmail.com
`
`Kenneth Roddy
`federallitigataionlaw@gmail.com
`
`
`
`
`
`
`
`
`
`
`13
`
`HP Exhibit 1010 - Page 13
`
`
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