Unlted States Patent
`[19]
`[11] Patent Number:
`5,600,605
`
`Schaefer
`[45] Date of Patent:
`Feb. 4, 1997
`
`U8005600605A
`
`[54] AUTO-ACTIVATE 0N SYNCHRONOUS
`DYNAMIC RANDOM ACCESS MEMORY
`.
`Inventor: Scott Schaefer, Borse, Id.
`
`[75]
`
`Kazuyuki Nakamura, et 31., “A 220—MHZ Pipelined 16—Mb
`BiCMOS SRAM with PLL Proportional Self—Timing Gen-
`erator”, IEEE Journal of Solid—State Circuits, No. 11, pp.
`1317_1321 (Nov 1994)
`_
`
`[73] Assignee: Micron Technology,vInc., Boise, 1d.
`
`[21] Appl. N05 481,920
`
`[22]
`
`Filed:
`
`Jun. 7, 1995
`
`Int. Cl.6 ....................................................... GllC 7/00
`[51]
`............
`[52] US. Cl.
`365/233; 365/230.03
`
`[58] Field of Search ..................................... 365/233, 203,
`365/222, 230.03
`
`[56]
`
`References Cited
`
`‘
`U-S- PATENT DOCUMENTS
`5/1993 Walther et a1.
`......................... 365/222
`5,208,779
`..... 365/222
`7/1993 Lee et a1.
`........
`5,229,969
`
`7/1993 Lee et a1.
`5,229,970
`----- 365/222
`5,257,233 10/1993 Schaefer ......
`----- 365/227
`5,335,201
`8/1994 Walther et 21
`""" 365/222
`5,444,667
`8/1995 Obara ................... 365/233
`
`365/189.01
`5,463,581
`10/1995 Koshikawa ..
`
`5,471,430
`11/1995 Sawada
`..... 365/222
`
`
`
`FOREIGN PATENT DOCUMENTS
`0561306
`9/1993 European pal, Off,
`.
`OTHER PUBLICATIONS
`
`Primary Examiner—Viet Q. Nguyen
`Assistant Examiner—Son Mai
`
`Attorney, Agent, or Firm—Schwegman, Lundberg, Woess—
`ner & Kluth, PA.
`
`[57]
`
`7
`
`ABSTRACT
`
`.
`A synchronous dynamic random access memory (SDRAM)
`includes a memory array and is responsive to command
`signals and address bits. A command decoder/controller
`responds to selected command signals to initiate, at different
`times, a precharge command, an active command, and a
`transfer command. The command decoder/controller ini-
`
`tiates the active command during the precharge command.
`Indicating circuitry responds to the precharge command to
`provide a precharge complete signal indicating the comple-
`.
`.
`non of a precharge command operation. A row address latch
`IBSPOHdS t0 the active command to receive and hold a value
`representing a row address of the memory array as indicated
`by the address bits provided at the time the active command
`is initiated, and responds to the precharge complete signal to
`release the row address.
`"
`
`Yasuhiro Takai, et al., “250 Mbyte/s Synchronous DRAM
`Using a 3—Stage pipelined Architecture”, IEEE Journal of
`Solid—State Circuits, No. 4, pp. 426—430, (Apr. 1994).
`
`24 Claims, 4 Drawing Sheets
`
`DATA— IN—
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`24
`
`HP Exhibit 1003 - Page 1
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`HP Exhibit 1003 - Page 1
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`

`

`US. Patent
`
`Feb. 4, 1997
`
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`HP Exhibit 1003 - Page 2
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`

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`US. Patent
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`Feb. 4, 1997
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`US. Patent
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`Feb. 4, 1997
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`HP Exhibit 1003 - Page 4
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`HP Exhibit 1003 - Page 4
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`

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`US. Patent
`
`Feb. 4, 1997
`
`Sheet 4 of 4
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`HP Exhibit 1003 - Page 5
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`HP Exhibit 1003 - Page 5
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`

`

`1
`AUTO-ACTIVATE ON SYNCHRONOUS
`DYNAMIC RANDOM ACCESS MEMORY
`
`THE FIELD OF THE INVENTION
`
`invention relates semiconductor memory
`The present
`integrated circuits and, more particularly to synchronous
`dynamic random access memories.
`
`BACKGROUND OF THE INVENTION
`
`random access memory
`dynamic
`A synchronous
`(SDRAM) is designed to operate in a synchronous memory
`system. Thus, all input and output signals, with the excep-
`tion of a clock enable signal during power down and self
`refresh modes, are synchronized to an active edge of a
`system clock.
`SDRAMs offer substantial advances in dynamic memory
`operating performance. For example, some SDRAMs are
`capable of synchronously providing burst data in a burst
`mode at a high-speed data rate by automatically generating
`a column address to address a memory array of storage cells
`organized in rows and columns for storing data within the
`SDRAM. In addition, if the SDRAM includes two banks of
`memory arrays, the SDRAM preferably permits interleaving
`between the two banks to hide precharging time.
`In an asynchronous DRAM, once row and column
`addresses are issued to the DRAM and a row address strobe
`
`signal and column address strobe signal are deactivated, the
`DRAM’s memory is precharged and available for another
`access. Another row cannot be accessed in the DRAM array,
`however, until the previous row access is completed.
`By contrast, a SDRAM requires separate commands for
`accessing and precharging a row of storage cells in the
`SDRAM memory array. Once row and column addresses are
`provided to a SDRAM in a SDRAM having multiple bank
`memory array’s, a bank memory array which is accessed
`remains active. An internally generated row address strobe
`remains active and the selected row is open until a PRE-
`CHARGE command deactivates and precharges the selected
`row of the memory array.
`In a SDRAM, a transfer operation involves performing a
`PRECHARGE command operation to deactivate and pre-
`charge a previously accessed bank memory army, perform-
`ing an ACTIVE command operation to register the row
`address and activate the bank memory array to be accessed
`in the transfer operation, and performing the transfer READ
`or WRITE command to register the colurrm address and
`initiate a burst cycle. At many frequencies,
`the time to
`perform the PRECHARGE command operation, and the
`ACTIVE command operation results in wasted time which
`adds up to an extra clock cycle resulting in a wait cycle.
`Thus, there is a need to eliminate possible wasted clock
`cycles between random READS and writes in a SDRAM.
`
`SUMMARY OF THE INVENTION
`
`The present invention provides a memory device having
`a memory array of storage cells organized in rows and
`column for storing data and responsive to command signals.
`The memory device operates in synchronization with active
`edges of a system clock, and includes a command decoder/
`controller responsive to selected command signals to ini—
`tiate, at a first active edge of the system clock, a first
`command controlling a first operation on the memory array.
`The command decoder/controller further initiates, at a sec-
`ond active edge of the system clock, a second command
`
`10
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`15
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`2
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`controlling a second operation on the memory array. The
`second active edge of the system clock occurs during the fast
`operation. Indicating circuitry responds to the first command
`to provide a fast command complete signal indicating the
`completion of the first operation. Second circuitry responds
`to the second command to perform a fast portion of the
`second operation, and responds to the fast command com—
`plete signal
`to perform a second portion of the second
`operation.
`In one preferred embodiment of the present invention, the
`second command is an active command. In this embodi-
`
`the fast portion of the second operation includes
`ment,
`receiving and holding a value representing a row address of
`the memory array. The second portion of the second opera-
`tion includes releasing the row address and activating a row
`of storage cells in the memory array.
`In one preferred embodiment of the present invention, the
`first command is a precharge command wherein the first
`operation includes precharging and deactivating the memory
`array. Optionally, the first command is a transfer command
`wherein the first operation includes a first transfer operation
`portion for transferring data to or from a storage cell in the
`memory array and a second auto-precharge operation por-
`tion wherein the command decoder/controller automatically
`initiates the auto-precharge operation portion after the trans-
`fer operation portion. The transfer command ean be a read
`command or a write command.
`
`In one preferred embodiment of the memory device, the
`indicating circuitry includes a timeout circuit. In another
`preferred embodiment of the memory device, the indicating
`circuitry includes a monitoring circuit.
`In one preferred embodiment of the present invention, the
`memory device is a synchronous dynamic random access
`memory (SDRAM). The SDRAM preferably includes a
`second memory array so that the SDRAM is structured to
`include two bank memory arrays. In this preferred form of
`the present invention, the SDRAM is further responsive to
`a bank select bit for selecting the bank memory array for a
`transfer operation.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a block diagram of a SDRAM according to the
`present invention.
`FIG. 2 is a timing diagram illustrating a four cycle read
`burst transfer operation.
`FIG. 3 is a timing diagram illustrating a four cycle write
`burst transfer operation.
`FIG. 4 is a timing diagram illustrating a four cycle read
`burst
`transfer operation implementing an AUTO-PRE-
`CHARGE command following a READ command.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`In the following detailed description of the preferred
`embodiments, reference is made to the accompanying draw-
`ings which form a part hereof, and in which is shown by way
`of illustration specific embodiments in which the invention
`may be practiced. It is to be understood that other embodi-
`ments may be utilized and structural or logical changes may
`be made without departing from the’ scope of the present
`invention. The following detailed description, therefore, is
`not to be taken in a limiting sense, and the scope of the
`present invention is defined by the appended claims.
`
`HP Exhibit 1003 - Page 6
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`HP Exhibit 1003 - Page 6
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`3
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`4
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`random access memory
`dynamic
`A synchronous
`(SDRAM) according to the present invention is illustrated
`generally at 20 in FIG. 1 in block diagram form. Much of the
`circuitry of SDRAM 20 is similar to circuitry in known
`SDRAMs,
`such
`as
`the Micron Technology,
`Inc.
`MT48LC4M4R1 S 4 MEG X 4 SDRAM, which is described
`in detail
`in the corresponding Micron Technology, Inc.
`Functional Specification, which is incorporated herein by
`reference. SDRAM 20 includes a bank 0 memory array 22
`and of bank 1 memory array 24 which both comprise storage
`cells organized in rows and columns for storing data. In one
`embodiment of SDRAM 20, each bank memory array com-
`prises four separate arrays of 2048 rows x1024 columns.
`As is illustrated in FIG. 1, power is supplied to SDRAM
`20 pins Vcc and Vss. A typical SDRAM 20 provides
`optimum memory performance in a low voltage environ-
`ment such as a 3.3 V environment. A system clock (CLK)
`signal is provided through a CLK input pin and a clock
`enable signal (CKE) is provided through a CKE input pin to
`SDRAM 20. The CLK signal is activated and deactivated
`based on the state of the CKE signal. All the input and output
`signals of SDRAM 20, with the exception of the CKE input
`signal during power down and self refresh modes, are
`synchronized to the active going edge (the positive going
`edge in the embodiment illustrated in FIG. 1 ) of the CLK
`signal.
`A chip select (CS*) input pin inputs a CS* signal which
`enables, when low, and disables, when high a command
`decode 26. Command decode 26 is included in a command
`controller 28. Command decoder 26 receives control signals
`including a row address strobe (RAS*) signal on a RAS*
`pin, column address strobe (CAS*) signal on a CAS* pin,
`and a write enable (WE*) signal on a WE* pin. Command
`decoder 26 decodes the RAS*, CAS*, and WE* signals to
`place command controller 28 in a particular command
`operation sequence. Command controller 28 controls the
`various circuitry of SDRAM 20 based on decoded com-
`mands such as during controlled reads or writes from or to
`bank 0 memory array 22 and bank 1 memory array 24. A
`bank address (BA) signal is provided on a BA input pin to
`define which bank memory array should be operated on by
`certain commands issued by command controller 28.
`Address inputs bits are provided on input pins A0—A10.
`As described below, both the row and column address input
`bits are provided on the address input pins. During write
`transfer operations, data is supplied to SDRAM 20 via
`input/output pins (DQ1—DQ—4). During read transfer opera-
`tions, data is clocked out of SDRAM 20 via input/output
`pins DQ1—DQ-4. An input/output mask signal is provided
`on a DQM input pin to provide non-persistent buffer control
`for a data-in-bufier 30 and a data-out buffer 32.
`
`SDRAM 20 must be powered—up and initialized in a
`predefined manner. In addition, both bank 0 and bank 1
`memory arrays 22 and 24 must be precharged and placed in
`an idle state. The precharging of the bank memory arrays is
`preformed with a precharge command operation which is
`described in more detail below. Once in the ideal state, two
`AUTO-REFRESH operations must be performed. Two
`refresh commands are typically available in SDRAM 20
`which are an AUTO—REFRESH command and a SELF
`REFRESH command. The AUTO-REFRESH and SELF-
`REFRESH commands are performed with refresh controller
`34, self-refresh oscillator and timer 36, and refresh counter
`38 in a manner known in the art to refresh the memory
`arrays. Once the two AUTO-REFRESH operations are per-
`formed, SDRAM 20 is available for programming of a mode
`register 40. Mode register 40 is assumed to have an
`
`l0
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`unknown state when SDRAM 20 is powered up. Conse-
`quently, before performing any operational command, mode
`register 40 must be set or programmed.
`Mode register 40 is typically a persistent register wherein
`once programmed, the mode register retains the program
`op-code until
`the mode register
`is
`reprogrammed or
`SDRAM 20 loses power. Most of the possible program
`mable options of SDRAM 20 are defined in the op—codes
`stored in mode register 40. Typically mode register 40 is
`programmed by providing a desired opccode via the BA
`input pins and the A0—A10 address inputs, in conjunction
`with a SET MODE REGISTER command determined by
`CS*, RAS*, CAS*, and WE* being registered low.
`A valid ACTIVE command is initiated by command
`controller 28 with the CS* and RAS* signals low with the
`CAS* and WE* signals high on a rising edge of the CLK
`signal. During the ACTIVE command the state of the BA
`signal determines which bank memory array to activate and
`address. During the ACTIVE command a value representing
`a row address of the selected bank memory array, as
`indicated by address bits on input pins A0—A10, is latched
`in a row address latch 42 in response to a clock signal
`generated from a clock generator circuit 44. The latched row
`address is provided to a row multiplexor 46 which provides
`a row address to row address buffers 48 to be provided to
`bank 0 memory array 22 or row address buffers 50 to be
`provided to bank 1 memory array 24 depending on the state
`of the BA signal. A row decoder 52 decodes the row address
`provided from row address buffers 48 to activate one of the
`2,048 lines corresponding to the row address for read or
`write transfer operations, to thereby activate the correspond-
`ing row of storage cells in bank 0 memory array 22. Row
`decoder 54 similarly decodes the row address in row address
`buffer 50 to activate one of the 2,048 lines to bank 1 memory
`array 24 corresponding to the row address for read or write
`transfer operations, to thereby activate the corresponding
`row of storage cells in bank 1 memory array 24. In order to
`access a row once a row in the selected bank memory has
`been activated with the ACTIVE command, a bank memory
`array must be precharged with the below described PRE-
`CHARGE command or AUTO-PRECHARGE command
`before another ACTIVE command is applied to the bank
`memory array.
`A valid READ command is initiated with the CS* and
`CAS* signals low, and the RAS* and WE* signals high on
`a rising edge of the CLK signal. The READ command from
`command controller 28 controls a column address latch 56
`which receives address bits A0—A9 and holds a value
`representing a column address of the bank memory array
`selected by the BA signal at the time the READ command
`is initiated. Column address latch 56 latches the column
`address in response to a clock signal generated by a clock
`generator 58. Address pin A10 provides an input path for a
`command signal which determines whether or not an
`AUTO-PRECHARGE command, described in detail below,
`is to be initiated automatically after the READ command.
`The READ command provided from command controller 28
`also initiates a burst read cycle, described in detail below, by
`starting a burst counter 60.
`A column address buffer 62 receives the output of the
`burst counter 60 to provide the current count of the column
`address to a column decoder 64. Column decoder 64 acti-
`vates four of the 1,024 X4 lines, provided to seine amplifiers
`and input/output (I/O) gating circuit 66 and sense amplifiers
`and I/O gating circuit 68 corresponding to the current
`column address. Sense amplifiers and I/O gating circuits 66
`and 68 operate in a manner known in the art to sense the data
`
`HP Exhibit 1003 - Page 7
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`HP Exhibit 1003 - Page 7
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`stored in the storage cells addressed by the active row
`decoder line and the active column decoder lines to provide
`the selected four bit byte of data from either bank 0 memory
`array 22 or bank 1 memory array 24 respectively to data-out
`buffer 32 during a read operation. Data-out buffer 32 pro-
`vides the selected four bit byte of data to input/output data
`pins DQ1—DQ4.
`In a burst read having a length of four, the initial column
`address stored in column address latch 56 is used to activate
`sense amplifiers and I/O gating circuits 66 or 68 during the
`first burst cycle of the burst read operation. Then, during the
`next three clock cycles burst counter 60 counts up from the
`column address stored in column address latch 56, as defined
`by a sequence type, to “burst” or clock-out the next three
`memory locations of data. A full-page burst will wrap
`around and continually restart the “burst" operation until a
`BURST TERMINATION command or PRECHARGE com-
`
`mand is indicated by command controller 28 or until inter-
`rupted with another burst operation.
`A valid WRITE command is initiated with the CS*,
`CAS*, and WE* signals low and the RAS* signal high on
`the rising edge of the CLK signal. The WRITE command
`provided from command controller 28 controls clock gen—
`erator 58 to clock column address latch 56 which receives
`and holds a value representing a column address of the bank
`memory array selected by the state of the BA signal at the
`time the WRITE command is initiated, as indicated by the
`address provided on address input pins A0—A9. As with the
`read operation, during the WRITE command, address pin
`A10 provides the additional feature to select whether or not
`the below described AUTO-PRECHARGE command is to
`be initiated following the WRITE command. Burst counter
`60 initiates the burst write cycle. Column address buffer 62
`receives the output of the burst counter 60 and provides the
`current column address to column decoder 64. Colurrm
`decoder 64 activates four of the l,024><4 lines to sense
`amplifiers and I/O gating circuits 66 and 68 corresponding
`to the column address to indicate where the incoming four
`bit byte of data is to be stored in either bank 0 memory array
`22 or bank 1 memory array 24.
`During WRITE command operations data is provided on
`input/output pins DQ1—DQ4 to data-in buffer 30. Data in
`buffer 30 provides the input write data to a latch 70 corre-
`sponding to bank 0 memory array 22 and a latch 72
`corresponding to bank 1 memory array 24. The four bit byte
`of input write data is provided from latch 70 or 72 to the
`selected bank memory array with sense amplifiers and I/O
`gating circuits 66 or 68 in a manner known in the art based
`on the activated four lines corresponding to the current
`colunm address.
`
`During a burst write operation of length four, the first byte
`of data is stored at the memory array location addressed by
`the column address stored in column address latch 56.
`Similar to the read burst operation, during the next three
`clock cycles, burst counter 60 counts up from the column
`address stored in column latch 56, as defined by the
`sequence type, to “burst” or clock in the data to be stored in
`the next three memory locations. A full page burst will wrap
`around and continue writing data until terminated by the
`BURST TERMINATION command, PRECHARGE com-
`mand, or until interrupted with another burst operation.
`The burst read and write operation are controlled by the
`burst mode defined in mode register 40 which is program-
`mable during the SET MODE MEGISTER command. The
`burst operation provide for a continuous flow of data from
`or to the specified memory array location during read or
`
`10
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`write access. Burst lengths of 2, 4, 8, or full page (1,024)
`cycles are programmable into mode register 40 in one
`embodiment of SDRAM 20. In one embodiment of the
`
`present invention, a burst read/single write mode permits a
`write operation to be a burst length of one and yet allows the
`read operation to be the programmed burst length as defined
`in mode register 40.
`In addition, a burst sequence is a programmable feature
`programmed into mode register 40 during the SET MODE
`REGISTER command. Typically two types of burst
`sequences are available for selection including a sequential
`sequence or an interleaving sequence. The sequential
`sequence bursts through sequential locations in one of the
`two bank memory arrays. The interleaving sequence inter-
`leaves between bank 0 memory array 22 and bank 1 memory
`array 24. In one embodiment of SDRAM 20, both the
`sequential and interleaving sequences support bursts of 2, 4,
`and 8 cycles.
`In this one embodiment,
`the sequential
`sequence supports full page length burst cycles.
`Command controller initiates a valid PRECHARGE com-
`mand with the CS*, WE*, and the RAS* signals low and the
`CAS* signal high on the positive going edge of the CLK
`signal. The PRECHARGE command operation deactivates
`and precharges the bank memory array selected by the state
`of the BA signal at the time the PRECHARGE command is
`initiated. In this way, the row previously accessed is deac—
`tivated and precharged so that row may be refreshed or
`another row accessed. Once a bank memory array has been
`precharged, that bank memory array is in an idle state and
`must be activated prior to another READ command or
`WRITE command being issued to that bank memory array.
`In the preferred embodiment of the SDRAM 20, multiple
`READ and WRITE commands do not require precharging
`between each command provided the same row is being
`accessed.
`
`the PRE-
`In a preferred embodiment of SDRAM 20,
`CHARGE command allows either one or both banks to be
`
`precharged. Individual bank precharging is performed if the
`value on address input pin A10 is registered low at the time
`the PRECHARGE command is initiated. During individual
`bank precharging, the state of the BA signal defines which
`bank is precharged. Both banks are precharged when A10 is
`registered high at the time the PRECHARGE command is
`initiated. If A10 is registered high at the time the PRE-
`
`CHARGE command is initiated, BA is treated as a “don’t7:
`CRIB.
`
`During any ACTIVE, READ, WRITE, or PRECHARGE
`command the bank memory array to be accessed is deter-
`mined by the registering of the BA signal at the initiation of
`the command. Bank 0 memory array 22 is selected if the
`value of the BA signal is registered low and bank 1 memory
`array 24 is selected if the value of the BA signal is registered
`high. As described above, the SBA signal determines the
`selection of one of the banks during a PRECHARGE
`command only when the value on input pin A10 is low. If the
`value on input pin A10 is high during the PRECHARGE
`command, BA becomes a “don’t care.”
`When a row of a selected bank memory array is selected
`with an ACTIVE command that row of the bank memory
`array becomes activated and continues to remain active until
`a PRECHARGE command to that selected bank memory
`array is issued. In other words, the RAS* signal is only
`registered once externally, but an internally generated RAS*
`signal to the selected bank memory array remains active
`until a PRECHARGE command is provided. READ and
`WRITE commands do not necessarily require a PRE—
`
`HP Exhibit 1003 - Page 8
`
`HP Exhibit 1003 - Page 8
`
`

`

`5,600,605
`
`7
`CHARGE command to follow the command, but a bank
`memory array must be precharged prior to registering a new
`row address. When selecting a row within a bank memory
`array, the other bank memory array can remain active to
`permit READ and WRITE commands to interleave between
`the two bank memory arrays.
`Precharging a bank memory array can, in most cases, be
`hidden due to the dual bank structure of SDRAM 20. To hide
`the precharging, a PRECHARGE command is issued to the
`bank memory array not being accessed while the bank
`memory array being accessed is in a burst mode.
`During read operations within the same bank, much of the
`precharge TRP time can still be hidden when transitioning
`from one row to another. The PRECHARGE command may
`be initiated up to one clock cycle prior to the last data-out
`during a read operation, provided that the read latency is two
`or more clocks. When the read latency is one clock, the
`PRECHARGE command may only be issued when the final
`data-out is available. In any case, at least one clock cycle of
`the precharge time TRP must occur during the cycle the last
`data-out is being held valid. That is, one of two or two of
`three clock cycles of the precharge time may be hidden
`provided the read latency is two or more. Otherwise, only
`one precharge clock may be hidden.
`WRITE commands require a write recovery time (TWR)
`from the last data-in element to the beginning of the PRE-
`CHARGE comrnand when the same bank memory array is
`going from a write command to a PRECHARGE command.
`An AUTO-PRECHARGE command is a non-persistent
`feature in SDRAM 20 which performs all of the same
`individual bank precharge functions described above for the
`PRECHARGE corrunand. The AUTO-PRECHARGE com-
`mand feature of the preferred embodiment of SDRAM 20,
`permits a user to program a READ command or WRITE
`command that automatically performs a precharge upon the
`completion of the READ command or the WRITE com
`mand.
`
`By using the AUTO—PRECHARGE command feature, a
`manual PRECHARGE command does not need to be issued
`during the functional operation of SDRAM 20. The AUTO-
`PRECHARGE command insures that the precharge is ini-
`tiated at the earliest, valid stage within a burst cycle. The
`user is not allowed to issue another command until
`the
`
`is completed. Therefore, when an
`precharged time (tRP)
`AUTO-PRECHARGE command is employed in SDRAM
`20, the selected bank memory array must not be accessed
`again until tRP, is complete. For example, if a read of two
`cycles is selected and three clock periods are required to
`satisfy tRP the bank memory array cannot be accessed during
`the two clocks following the completion of a burst operation.
`If a burst of four is programmed and three clock periods are
`required to satisfy tRP, the bank memory array cannot be
`accessed during the one clock cycle following the comple-
`tion of the burst, provided that the read latency is two or
`more clocks, otherwise, the bank memory array cannot be
`accessed during the two Clocks following the completion of
`the burst cycle.
`Write operations require the write recovery time (TWR)
`from the last data-in element to the beginning of the PRE-
`CHARGE command when the same bank memory array is
`being accessed. Thus, the bank memory array cannot be
`reaccessed until TWR+tRP from the last date-in element.
`The read latency is a programmable feature of SDRAM
`20 defined in mode register 40 during the SET MODE
`REGISTER command. Typically, read latencies of 1,2, or 3
`clocks are available. The read latency guarantees at which
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`8
`clock the data will become available regardless of the
`system clock rate. Data can be made available on the
`input/output pins DQ1~DQ4 up to one clock cycle less than
`the read latency, depending on the frequency of the system
`clock. Aread latency of two clocks programmed with a cycle
`rate which is greater than the minimum access time will
`provide data almost immediately after the first clock.
`A no operation (NOP) command can be provided to
`SDRAM 20 to prevent other unwanted commands from
`being registered during idle or wait states.
`A four cycle burst read operation is illustrated in timing
`diagram form in FIG. 2. As illustrated, the system clock
`cycle time is indicated by tCK. The time from the initiation
`of an ACTIVE command to the initiation of a READ
`
`command is representing by tRCD and represents two clock
`cycles, such a between time to and time t2. The total read
`burst transfer cycle period is represented by tRC and repre—
`sents nine clock cycles as illustrated in FIG. 2. The total
`ACTIVE command period, wherein the row address strobe
`is active, is represented by tRAS, and represents four clock
`cycles as illustrated in FIG. 2. The READ access time for
`each cycle burst in represented by tAC. The time from the
`initiation of the READ command to the DQ clock first
`data-out cycle is represented by tM and indicates the column
`address strobe latency period and is two clock periods as
`illustrated in FIG. 2. The PRECHARGE command period
`(tRP) is three system clock cycles as illustrated in FIG. 2.
`As illustrated in FIG. 2, an ACTIVE command is initiated
`by command controller 28 at time to; the corresponding
`READ command is initiated at time t2; the first cycle burst
`of data is output at time t4; and the last of the four cycle data
`bursts is output at time t7. At time t6, a PRECHARGE
`command is initiated when the second to last data burst is
`output, and the next ACTIVE command is initiated at time
`t9, three clock cycles after the PRECHARGE command at
`time t5.
`A four cycle WRITE burst transfer operation is illustrated
`in timing diagram form in FIG. 3. The timing diagram of
`FIG. 3 is similar to the tinting diagram of FIG. 2 illustrating
`the four cycle READ burst transfer operation. Therefore,
`only the differences between the WRITE and READ com«
`mands are now described. During a WRITE operation, the
`data—in setup time is represented by tDS, and the data'in hold
`time is represented by tDH. The write recovery time is
`indicated by tWR, which represents one clock cycle in FIG.
`3 between t5 and Is.
`The time from when the WRITE command is initiated at
`t2 to when the write recovery time is completed after four
`data bursts have been written into one of the bank memory
`arrays represents four clock cycles as illustrated in FIG. 3
`between t2 and t6. Thus, as with the four cycle read burst
`transfer operation, the total command period (tRCA) is again
`equal to nine clock cycles for the four cycle write burst
`transfer operation.
`Both FIGS. 2 and 3 represent a four cycle burst transfer
`operation, but as described above SDRAM 20 preferably
`can be programmed to perform 2, 4, 8, or full page cycle
`burst operations and the present invention is not limited to
`a four burst transfer operation.
`A four cycle read burst transfer operation which utilizes a
`programmed READ command which automatically issues
`an AUTO-PRECHARGE command without having to issue
`and an actual PRECHARGE command is illustrated in FIG.
`4 in timing diagram form. FIG. 4 is similar to FIG. 2 except
`at time t6 a NOP command is issued rather than the PRE-
`CHARGE command since at
`time t,S
`the