`
`EXHIBIT A
`
`GOODMAN EX. 2001
`Page 1 of 3
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`
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`Case 4:16-cv-03195 Document 48-1 Filed in TXSD on 02/16/18 Page 2 of 3
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`
`
`
`TERM/PHRASE
`'memory system"
`
`CONSTRUCTION
`
`'a system capable of retaining data"
`
`COURT’S
`CONSTRUCTION
`[AGREED]
`
`'memory device"
`
`"integrated circuit or chip"
`
`[AGREED]
`
`[AGREED]
`
`[AGREED]
`
`"two or more memory devices in the
`memory system into which data may be
`written or from which data may be
`retrieved that retain information while an
`electrical power source, having a
`predetermined voltage range, is applied to
`the memory devices and when the voltage
`reaches a predetermined threshold outside
`of that range, the memory devices will no
`longer retain their current state of
`information"
`"inhibiting signals on the respective
`address and respective control lines from
`the memory devices such that signals on
`those lines do not arrive at the memory
`devices"
`
`'a plurality of
`volatile solid state
`memory device"
`
`"selectively
`electrically
`isolating said
`memory
`devices from
`respective
`address lines
`and respective
`control lines"
`'any signals
`received on said
`respective address
`lines and
`respective control
`lines do not reach
`said memory
`devices"
`'address lines"
`
`any signals received on the respective
`address lines and respective control lines
`do not arrive at the memory devices"
`
`[AGREED]
`
`"lines that carry signals specifying a
`memory location to be accessed"
`
`'control signals"
`
`"signals that control the sequence of
`addressing and the memory mode"
`
`'control lines"
`
`"lines that carry control signals"
`
`"determining
`when said
`memory system is
`not being
`accessed"
`
`
`
`"determining when there are no pending
`requests to retrieve information from or
`save information to a memory device of
`the memory system"
`
`1
`
`[AGREED]
`
`[AGREED]
`
`[AGREED]
`
`[AGREED]
`
`GOODMAN EX. 2001
`Page 2 of 3
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`
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`Case 4:16-cv-03195 Document 48-1 Filed in TXSD on 02/16/18 Page 3 of 3
`
`"for initiating a
`low power mode
`for said memory
`system"
`"low power
`mode"
`
`"said control
`device
`electrically
`isolates said
`memory devices
`and places said
`memory devices
`in said self
`refresh mode"
`"self refresh
`mode"
`
`
`
`
`
`"when it is determined that said
`memory system is not being accessed,
`initiating a low power mode for said
`memory system"
`"the memory device is in a state
`whereby it is in self refresh mode and
`is unable to respond to memory
`requests including read and write
`requests"
`"the control device isolates the
`respective address and respective control
`lines from the memory devices such that
`any signals received on the respective
`address lines and respective control lines
`do not arrive at the memory devices and
`the control device places the memory
`devices in the self refresh mode"
`
`"mode in which the volatile solid state
`memory device is capable of maintaining
`the state of the data retained by it by
`generating signals that refresh the data
`within its memory array"
`
`[AGREED]
`
`[AGREED]
`
`[AGREED]
`
`[AGREED]
`
`2
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`GOODMAN EX. 2001
`Page 3 of 3
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