Trials@uspto.gov
`571.272.7822
`
`
` Paper No. 6
`
`Filed: March 9, 2018
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`
`HP INC.,
`Petitioner,
`
`v.
`
`JAMES B. GOODMAN,
`Patent Owner.
`
`Case IPR2017-01994
`Patent 6,243,315 B1
`____________
`
`
`
`Before BRIAN J. McNAMARA, PATRICK M. BOUCHER, and
`KIMBERLY McGRAW, Administrative Patent Judges.
`
`McGRAW, Administrative Patent Judge.
`
`
`
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`
`
`571.272.7822
`
`
` Paper No. 6
`
`Filed: March 9, 2018
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`
`HP INC.,
`Petitioner,
`
`v.
`
`JAMES B. GOODMAN,
`Patent Owner.
`
`Case IPR2017-01994
`Patent 6,243,315 B1
`____________
`
`
`
`Before BRIAN J. McNAMARA, PATRICK M. BOUCHER, and
`KIMBERLY McGRAW, Administrative Patent Judges.
`
`McGRAW, Administrative Patent Judge.
`
`
`
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`
`
`
`IPR2017-01994
`Patent 6,243,315 B1
`
`
`I.
`
`INTRODUCTION
`
`HP Inc. (“Petitioner”) filed a Petition requesting an inter partes
`
`review of claims 1, 5, 10, and 16 (“the challenged claims”) of U.S. Patent
`
`No. 6,243,315 B1 (Ex. 1001, “the ’315 patent”). Paper 2 (“Pet.”). James B.
`
`Goodman (“Patent Owner”) filed a Preliminary Response. Paper 5 (“Prelim.
`
`Resp.”).
`
`We have jurisdiction under 35 U.S.C. § 314(a), which provides that an
`
`inter partes review may not be instituted unless the information presented in
`
`the Petition shows “there is a reasonable likelihood that the petitioner would
`
`prevail with respect to at least 1 of the claims challenged in the petition.”
`
`Upon consideration of the Petition, the Preliminary Response, and the
`
`evidence therein, we conclude the information presented shows there is a
`
`reasonable likelihood that Petitioner would prevail in establishing the
`
`unpatentability of claims 1, 5, 10, and 16 of the ’315 patent.
`
`Our factual findings and conclusions at this stage of the proceeding,
`
`including claim construction, are preliminary and are based on the
`
`evidentiary record developed thus far. This is not a final decision as to
`
`patentability of claims for which inter partes review is instituted. Our final
`
`decision will be based on the record as developed fully during trial.
`
`A. Related Proceedings
`
`The parties identify the following litigations as related proceedings:
`
`Goodman v. Hewlett-Packard Co., C.A. No. 16-CV-03195 (S.D. Tex.);
`
`Goodman v. ASUS Computer International, C.A. 17-CV-05542 (N.D. Cal.
`
`05542) (Transferred from the S.D. Texas.); Goodman v. Samsung
`
`Electronics America, Inc., C.A. No. 17-CV-05539 (S.D. N.Y.); and
`
`2
`
`
`
`IPR2017-01994
`Patent 6,243,315 B1
`
`
`Goodman v. Lenovo (United States) Inc., C.A. 17-CV-06782. Pet. 2; Prelim.
`
`Resp. 2.
`
`We also note that the ’315 patent is also the subject of current
`
`petitions for inter partes review by Petitioner Samsung (Case IPR2017-
`
`02021) and by Petitioner ASUS Computer International Inc. (IPR2018-
`
`00047).
`
`B. The ’315 patent
`
`The ’315 patent is directed to volatile memory devices. Ex. 1001,
`
`Abstract. Volatile memory devices “retain the contents of their memory
`
`states when electrical power is provided and maintained on the devices,” but
`
`“[w]henever electrical power is removed from the devices, the memory
`
`contents of the device [are] lost and irretrievable.” Id. at 2:54–58. Figure 4
`
`of the ’315 patent is reproduced below:
`
`
`
`
`
`3
`
`
`
`IPR2017-01994
`Patent 6,243,315 B1
`
`
`Figure 4, shown above, illustrates a block diagram of a non-volatile memory
`
`system according to the invention. Ex. 1001, 4:41–42.
`
`According to the ’315 patent:
`
`The invention prevents the loss of data due to unexpected power
`outages and also prevents errant control and address signals to
`the memory devices by monitoring the input electrical power
`source to the memory devices for acceptable conditions, and
`electrically isolating the memory devices from signals received
`on the control lines and address lines and switching to an
`alternate internal electrical power source, typically a battery,
`whenever the input power source is unacceptable.
`
`Id. at 3:15–24. The ’315 patent explains further that the system
`
`“maintains the integrity of the data retained by the memory devices by
`
`isolating the devices from the external power source, control lines and
`
`address lines and placing the memory devices into a power down self-
`
`refresh mode which will maintain the data using a minimum of
`
`electrical power.” Id. at 3:25–30.
`
`
`
`Independent claims 1 and 10 are illustrative of the claims at issue and
`
`C. Illustrative Claims
`
`are reproduced below.1
`
`1. [a] A memory system for use in a computer system, said
`memory system comprising:
`
`[b-d] a plurality of volatile solid state memory devices that
`retain information when an electrical power source is
`applied to said memory devices within a predetermined
`voltage range and capable of being placed in a self refresh
`
`
`
`1 Paragraph breaks and bracketed letters have been added for ease of
`reference and for consistency with nomenclature utilized by Petitioner.
`
`4
`
`
`
`IPR2017-01994
`Patent 6,243,315 B1
`
`
`mode; said memory devices having address lines and
`control lines;
`
`[e] a control device for selectively electrically isolating
`said memory devices from respective address lines and
`respective control lines so that when said memory devices
`are electrically isolated, any signals received on said
`respective address lines and respective control lines do not
`reach said memory devices; and
`
`[f] a memory access enable control device coupled to said
`control device and to said control lines for determining
`when said memory system is not being accessed and for
`initiating a low power mode for said memory system
`wherein said control device electrically isolates said
`memory devices and places said memory devices in said
`self refresh mode, thereby reducing the amount of
`electrical energy being drawn from an electrical power
`supply for said computer system.
`
`Id. at 13:18–40.
`
`10. [a] A memory system for use in a computer system, said
`memory system comprising:
`
`[b] a plurality of volatile solid state memory devices that
`retain information when an electrical power source having
`a voltage greater than a predetermined voltage is applied
`to said devices;
`
`[c] said memory devices having address lines and control
`lines;
`
`[d] said computer system including a first electrical power
`source for operating said computer and being capable of
`producing a first voltage applied to said memory devices;
`
`[e] a control device for monitoring said first voltage to
`determine when said first voltage is less than said
`predetermined voltage and for selectively electrically
`isolating said memory devices from respective address
`lines and respective control lines so that when said
`memory devices are electrically isolated, any signals
`
`5
`
`
`
`IPR2017-01994
`Patent 6,243,315 B1
`
`
`received on said respective address lines and respective
`control lines do not reach said memory devices; and
`
`[f] a second electrical power source operable for supplying
`a second voltage to said memory devices greater than said
`predetermined voltage;
`
`[g] said control device being operable for disconnecting
`said first electrical power source from said memory
`devices and connecting said second electrical power
`source to said memory devices when said first voltage is
`less than said predetermined voltage;
`
`[h] whereby, data in said memory devices is preserved by
`said second electrical power source when said first
`electrical power source fails to maintain at least said
`predetermined voltage on said memory devices, and said
`memory devices are isolated from errant signals.
`
`Id. at 13:65–14:32.
`
`D. Asserted Grounds of Unpatentability
`
`
`
`Relying upon the declaration testimony of Nader Bagherzadeh, Ph.D.,
`
`(Ex. 1002, “Bagherzadeh Declaration”), Petitioner challenges claims 1, 5,
`
`10, and 16 of the ’315 patent based on the asserted grounds of
`
`unpatentability (“grounds”) set forth in the table below. Pet. 3, 23–51.
`
`References
`
`Basis
`
`Challenged Claims
`
`Schaefer2 and Qureshi3
`
`§ 103(a)
`
`1 and 5
`
`Schaefer, Qureshi, and
`Mazur4
`
`
`
`§ 103(a)
`
`10 and 16
`
`
`
`2 U.S. Patent No. 5,600,605 (issued Feb. 4, 1997) (Ex. 1004, “Schaefer”)
`3 U.S. Patent No. 5,793,776 (issued Aug. 11, 1998) (Ex. 1005, “Qureshi”)
`4 U.S. Patent No. 5,204,840 (issued Apr. 20, 1993) (Ex. 1006, “Mazur”)
`
`6
`
`
`
`IPR2017-01994
`Patent 6,243,315 B1
`
`
`II. DISCUSSION
`
`A. Level of Ordinary Skill in the Art
`
`In determining whether an invention would have been obvious at the
`
`time it was made, we consider the level of ordinary skill in the pertinent art
`
`at the time of the invention. Graham v. John Deere Co, 383 U.S. 1, 17
`
`(1966). Petitioner contends a person of ordinary skill in the art at the time of
`
`the alleged invention of the ’315 patent (a “POSITA”) would have had at
`
`least a bachelor’s degree in electrical, electronics, computer engineering; or
`
`the equivalent training or experience in electrical, electronics, computer
`
`engineering, or a related discipline, and would have had approximately 2 to
`
`3 years of experience in computer systems, circuits, electronics, or a related
`
`discipline. Pet. 16; Ex. 1002 ¶¶ 31–32.
`
`Patent Owner does not articulate a level of skill for a POSITA. For
`
`the purposes of this Decision, we determine that it is not necessary to state
`
`explicitly a specific level of skill as the prior art itself reflects an appropriate
`
`level of skill. See Okajima v. Bourdeau, 261 F.3d 1350, 1355 (Fed. Cir.
`
`2001).
`
`B. Claim Construction
`
`In an inter partes review, we construe claim terms in an unexpired
`
`patent according to their broadest reasonable construction in light of the
`
`specification of the patent in which they appear. 37 C.F.R. § 42.100(b).
`
`Consistent with the broadest reasonable construction, claim terms are
`
`presumed to have their ordinary and customary meaning as understood by a
`
`person of ordinary skill in the art in the context of the entire patent
`
`disclosure. In re Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir.
`
`2007).
`
`7
`
`
`
`IPR2017-01994
`Patent 6,243,315 B1
`
`
`Neither Petitioner nor Patent Owner identifies any claim terms as
`
`warranting construction. Pet. 10; Prelim. Resp. 1–8. Based on the current
`
`record, we conclude that no claim construction is necessary for our
`
`determination of whether to institute inter partes review of the challenged
`
`claims. Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed.
`
`Cir. 1999) (“[O]nly those terms need be construed that are in controversy,
`
`and only to the extent necessary to resolve the controversy.”).
`
`C. Principles of Law
`
`A claim is unpatentable under 35 U.S.C. § 103(a) if “the differences
`
`between the subject matter sought to be patented and the prior art are such
`
`that the subject matter as a whole would have been obvious at the time the
`
`invention was made to a person having ordinary skill in the art to which said
`
`subject matter pertains.” KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406
`
`(2007). The question of obviousness is resolved on the basis of underlying
`
`factual determinations, including: (1) the scope and content of the prior art;
`
`(2) any differences between the claimed subject matter and the prior art;
`
`(3) the level of skill in the art; and (4) objective evidence of nonobviousness,
`
`i.e., secondary considerations. See Graham v. John Deere Co, 383 U.S. 1,
`
`17–18 (1966).
`
`D. Overview of the Asserted Art
`
`1. Schaefer (Ex. 1003)
`
`Schaefer describes a volatile memory device, such as a synchronous
`
`dynamic random access memory (“SDRAM”), “for storing data and
`
`responsive to command signals.” Ex. 1003, 1:60. Schaefer includes a
`
`command decoder that “controls the various circuitry of SDRAM based on
`
`decoded commands such as during controlled reads or writes.” Id. at 3:35–
`
`8
`
`
`
`IPR2017-01994
`Patent 6,243,315 B1
`
`
`37 (reference numerals omitted). Schaefer explains that the memory device
`
`includes address and control lines, see id. at 3:30–33, and discloses a
`
`“SELF-REFRESH” command for the devices, id. at 3:60–61. According to
`
`Schaeffer, “[a]ll the input and output signals of SDRAM, with the exception
`
`of the CKE input signal during power down and self refresh modes, are
`
`synchronized to the active going edge . . . of the CLK signal.” Id. at 3:20–25
`
`(reference numerals omitted). Schaefer notes that refresh commands “are
`
`performed . . . in a manner known in the art to refresh the memory arrays.”
`
`Id. at 3:61–65. Schaffer notes also that “[i]n one preferred embodiment of
`
`the present invention, the memory device is a synchronous dynamic random
`
`access memory (SDRAM).” Id. at 2:33–35.
`
`2. Qureshi (Ex. 1004)
`
`Qureshi describes a process in which “memory such as SDRAMs are
`
`put into self refresh mode.” Ex. 1004, 1:63–64. Qureshi states that the
`
`system has the “ability to dynamically enter and exit SDRAM self refresh
`
`before and after [JTAG] testing,” which saves debugging time.” Id. at 2:54–
`
`56. Qureshi explains that “[o]nce the self refresh mode is entered, SDRAM
`
`ignores all inputs other than a CKE (clock enable) pin while in self refresh
`
`state.” Id. at 5:49–51 (reference numerals omitted). Qureshi characterizes
`
`self refresh mode as “preferred for data retention and low power operation.”
`
`Id. at 1:65–67.
`
`3. Mazur (Ex. 1005)
`
` Mazur teaches a process “for preserving the RAM of an externally
`
`powered microprocessor on the occasion of a loss in external power.”
`
`Ex. 1005, Abstract. According to Mazur, “[w]hen the power loss is
`
`9
`
`
`
`IPR2017-01994
`Patent 6,243,315 B1
`
`
`detected, a signal is generated which initiates a sequence to isolate the RAM
`
`and refresh it with an independent power supply,” e.g., a rechargeable
`
`battery. Id., see also 2:8–10 (stating the “hardware comprises in coactive
`
`combination a power loss detection circuit, an independent power supply, a
`
`continuously rechargeable battery, . . . a standby refresh circuit, a switch-
`
`over circuit).
`
`E. Asserted Obviousness of Claims 1 and
`5 over Schaefer and Qureshi
`
`Petitioner contends that claims 1 and 5 are unpatentable under
`
`§ 103(a) over the combined teachings of Schaefer and Qureshi. Pet. 3. 17–
`
`19, 23–30, 39–40, 50–51. For example, in mapping independent claim 1,
`
`Petitioner contends that Schaefer discloses a plurality of volatile solid state
`
`memory devices (e.g., SDRAMs) that retain information when powered in a
`
`3.3V low voltage environment. Id. at 24–25, 39–40 (citing Ex. 1003, 2:36–
`
`37, 3:13–16, Fig. 1). Petitioner also states that Schaefer’s memory has
`
`address lines (e.g., A0-A15) and control lines (e.g., RAS, CAS, WE) and is
`
`capable of being placed in a self refresh mode, id. at 25–26 (citing Ex. 1003,
`
`3:30–33, 3:58–61, 4:19–21).
`
`Petitioner also asserts that Qureshi teaches a memory controller (i.e.,
`
`control device of claim element 1[e]) that places an SDRAM in a self-
`
`refresh mode prior to beginning JTAG testing, where “all access signals are
`
`ignored, which corresponds to electrically isolating the SDRAM.” Id. at 26
`
`(citing Ex. 1004, Abstract, 5:49–51). Petitioner states that once the self-
`
`refresh mode is entered, the SDRAM ignores all inputs other than a CKE
`
`(clock enable) pin while in the self-refresh state. Id. (citing Ex. 1004, 5:49–
`
`51); Ex. 1004, 1:65:2–2. Petitioner further asserts that a POSITA would
`
`10
`
`
`
`IPR2017-01994
`Patent 6,243,315 B1
`
`
`understand that Qureshi’s memory controller is configured to place an
`
`SDRAM, such as the SDRAM of Schaefer, into a “don’t care” state, thereby
`
`electrically isolating the address/control lines and placing it in a low power
`
`self-refresh mode, prior to performing its tests. Id. at 26–27, 41 (citing Ex.
`
`1002 ¶¶ 59–61). Petitioner states that Schaefer’s SDRAM memory includes
`
`a pin for receiving a “don’t care” signal, which then inhibits any action from
`
`the memory device, thereby electrically isolating it from the address/control
`
`lines. Id. at 27 (citing Ex. 1003 6:56–58, Fig. 1.
`
`Petitioner asserts that the combination of Schaefer and Qureshi
`
`teaches the “memory access enable device” of claim element 1[f].
`
`Specifically, Petitioner asserts that Schaefer’s command controller in the
`
`SDRAM is a “memory access enable control device” that includes circuitry
`
`for decoding read/write commands from Qureshi’s memory controller “so as
`
`to determine which memory bank should be addressed, including decoding
`
`Qureshi’s signal that places Schaefer’s SDRAM into power down or self
`
`refresh mode, where all access signals are ignored.” Id. at 27–29, 41–43
`
`(citing Ex. 1004, Abstract, 5:49–51, Fig. 1; Ex. 1003, 3:20– 25, 3:28–42,
`
`Fig. 1). Petitioner notes also that Qureshi teaches that the self-refresh mode
`
`“is preferred for data retention and low power operation.” Id. at 26 (quoting
`
`Ex. 1005, 1:65–67) (emphasis omitted).
`
`Petitioner further asserts that the combination of Schaefer and Qureshi
`
`teaches DRAM semiconductor microchips—the additional limitation in
`
`dependent claim 5—because both references “pertain to SDRAM, which is a
`
`subset of the DRAM semiconductor microchip.” Id. at 30, 50–51; Ex. 1002
`
`¶ 65.
`
`11
`
`
`
`IPR2017-01994
`Patent 6,243,315 B1
`
`
`In addition, the Petition explains, with relevant support from Dr.
`
`Bagherzadeh, that combining Schaefer and Qureshi would have been
`
`obvious because one skilled in the art “would seek to use the memory
`
`controller of Qureshi to place the DRAM memory of Schaefer into the low
`
`power self-refresh mode so that existing data may be retained, while other
`
`signals may be ignored, and the amount of power consumed from the
`
`computer system is reduced.” Id. at 14 (citing Ex. 1002 ¶¶ 48–53).
`
`Patent Owner responds that the combination of Schaefer and Qureshi
`
`fails to teach the control device recited in claim element 1[e] and the
`
`memory access enable control device recited in claim element 1[f]. Prelim.
`
`Resp. 6. Specifically, Patent Owner states that “Qureshi dynamically enters
`
`the self refresh on an external demand. That is, Qureshi requires human
`
`intervention to initiate the self refresh mode” and therefore does not teach a
`
`“memory access enable control device coupled to said control device and to
`
`said control lines for determining when said memory system is not being
`
`accessed and for initiating a low power mode.” Id. at 6–7 (quoting
`
`Ex. 1004, 2:54–57, 6:42–45).
`
`Patent Owner’s argument is not persuasive at this stage of the
`
`proceeding because Petitioner is not relying solely upon Qureshi, but rather
`
`is relying upon the combined teachings of Schaefer and Qureshi for meeting
`
`the disputed limitations. Petitioner contends that a POSITA would
`
`understand that Schaefer’s command controller 28 (i.e., memory access
`
`enable control device) is coupled to the memory controller (i.e., control
`
`device) of Qureshi to receive commands from the memory controller and for
`
`determining access. See, e.g., Id. at 43 (stating that “the command controller
`
`of Schaefer is coupled to the memory controller of Qureshi to receive
`
`12
`
`
`
`IPR2017-01994
`Patent 6,243,315 B1
`
`
`commands from the memory controller and for determining access”); Ex.
`
`1002 ¶¶ 62–63; see also Pet. at 29 (stating Schaefer’s command controller
`
`(i.e., memory access enable device) decodes commands from the Qureshi
`
`memory controller (i.e., control device) so as to determine which memory
`
`bank should be addressed, “including decoding Qureshi’s signal that places
`
`Schaefer’s SDRAM into power down or self-refresh mode, where all access
`
`signals are ignored (‘memory system is not being accessed and for initiating
`
`a low power mode’”)). Petitioner further asserts that a POSITA would
`
`understand that Qureshi’s memory controller (i.e., “control device of claim
`
`element 1[e]”) is configured to place the Schaefer SDRAM into a “don’t
`
`care” state, thereby electrically isolating the address/control lines and
`
`placing it in a low power self-refresh mode, prior to performing its tests.
`
`See, e.g., Pet. at 41 (stating the “configuration of Qureshi’s memory
`
`controller with Schaefer’s SDRAM discloses limitation 1.e.”).
`
`Patent Owner also argues that the combination of Schaefer and
`
`Qureshi do not teach all of the limitations of claim 1 because “Qureshi does
`
`not disable the CKE when it drives Schaefer into self refresh.” Prelim.
`
`Resp. 7; see also id. at 8 (stating “the combination of Qureshi and Schaefer
`
`keeps a control line (CKE) active and connected to the SDRAM even in the
`
`self refresh mode in contrast to the ’315 Patent claims”).
`
`This argument is not persuasive because we do not understand claim 1
`
`to require electrically isolating memory devices from all address and control
`
`lines. Indeed, such a reading would be inconsistent with the preferred
`
`embodiments, which do not appear to isolate the memory devices from all
`
`address and control lines. For example, the ’315 patent states that the
`
`control device shown in Figure 1 electrically isolates control bus 22 and
`
`13
`
`
`
`IPR2017-01994
`Patent 6,243,315 B1
`
`
`address bus 17 from the memory devices, but does not state that the memory
`
`devices are electrically isolated from the RAS and WE control lines, 26, 28.
`
`Ex. 1001, Fig. 4, 5:60–67; see also id. at 9:24–26, (stating that control center
`
`115 of Figure 4 electrically isolates memory devices 5 from control lines
`
`122 and address lines 117, but not stating that the memory devices are
`
`isolated from RAS and WE Control Lines).
`
`On the present record, we are persuaded Petitioner has shown
`
`sufficiently the combination of Schaefer and Qureshi teaches or suggests the
`
`limitations of claims 1 and 5 and has provided articulated reasoning with
`
`rational underpinning for combining the references. Accordingly, the
`
`information presented shows a reasonable likelihood that Petitioner would
`
`prevail in showing that claims 1 and 5 would have been obvious over the
`
`combination of Schaefer and Qureshi.
`
`F. Asserted Obviousness of Claims 10
`and 16 over Schaefer, Qureshi, and
`Mazur
`
` Petitioner contends that claims 10 and 16 would have been obvious
`
`over the combined teachings of Schaefer, Qureshi, and Mazur. Pet. 3, 17–
`
`21, 31–39, 44–50. For example, in addition to referencing several elements
`
`already identified for claim 1, Petitioner explains that Mazur discloses
`
`memory devices that retain information when voltage is applied above a
`
`predetermined threshold. Id. at 31–32 (citing Ex. 1006, 5:11–15, 5:36–39,
`
`3:9–16); Ex. 1002 ¶ 75. Petitioner explains also that Mazur teaches a first
`
`power source (i.e., the computer’s power supply that provides at least 4.8V
`
`for the memory devices), that is monitored so that when the voltage supplied
`
`from that source drops below the predetermined threshold, “the control
`
`14
`
`
`
`IPR2017-01994
`Patent 6,243,315 B1
`
`
`device selectively electrically isolates the memory devices from the
`
`respective address and control lines.” Id. at 32–35 (citing Ex. 1005, 3:9–16,
`
`4:17–32, 5:11–15, 5:36–39, Fig. 1). According to Petitioner, Mazur
`
`discloses a second electrical power source (i.e. a rechargeable battery 18) for
`
`supplying a second voltage to the memory device, as well as a power
`
`switchover circuit for switching from the computer power supply to the
`
`rechargeable battery when the computer power supply falls below the
`
`threshold, thus isolating the volatile memory from errant signals and
`
`preventing corruption. Id. at 35–36, 47–49 (citing Ex. 1006, 5:11–15, 4:2–
`
`6, 4:17–32, 3:9–16, 5:36–39, Fig. 1).
`
`Patent Owner argues that Petitioner has failed to provide a technical
`
`argument for combining Mazur with the combination of Schaefer and
`
`Qureshi. Prelim. Resp. 4–5. This argument is not persuasive at this stage of
`
`the proceeding. Petitioner has provided evidence, supported by declaration
`
`testimony, that a person of ordinary skill in the art would have reason to
`
`combine the teachings of Schaefer, Qureshi, and Mazur in order to, inter
`
`alia, enable retention of SDRAM data during testing phase, without concern
`
`as to power losses. Pet. 20–21 (citing Ex. 1002 ¶¶ 69–70); id. at 20 (stating
`
`that a POSITA “would recognize that [Qureshi’s] low power mode may be
`
`supported by a battery backup instead of the primary power source, thereby
`
`enabling failure of the primary power source without the need for resetting
`
`any components”); see also id. at 21 (stating the “combination of familiar
`
`elements according to known methods is likely to be obvious when it does
`
`no more than yield predictable results”).
`
`On the present record, we are persuaded Petitioner has shown
`
`sufficiently the combination of Schaefer, Qureshi, and Mazur teaches or
`
`15
`
`
`
`IPR2017-01994
`Patent 6,243,315 B1
`
`
`suggests the limitations of claims 10 and 16 and has provided articulated
`
`reasoning with rational underpinning for combining the references.
`
`Accordingly, the information presented shows a reasonable likelihood that
`
`Petitioner would prevail in showing that claims 10 and 16 would have been
`
`obvious over the combination of Schaefer, Qureshi, and Mazur.
`
`III. CONCLUSION
`
`For the foregoing reasons, we determine Petitioner has demonstrated
`
`there is a reasonable likelihood it would prevail in establishing the
`
`unpatentability of claims 1, 5, 10, and 16 of the ’315 patent.
`
`At this stage of the proceeding, the Board has not made a final
`
`determination as to the patentability of any challenged claim or of any
`
`underlying factual and legal issues, including claim construction.
`
`IV. ORDER
`
`Accordingly, it is:
`
` ORDERED that, pursuant to 35 U.S.C. § 314(a), an inter partes
`
`review is hereby instituted for the following grounds of unpatentability:
`
`Claims 1 and 5 as unpatentable under 35 U.S.C. § 103(a) over
`
`Schaefer and Qureshi;
`
`Claims 10 and 16 as unpatentable under 35 U.S.C. § 103(a) over
`
`Schaefer, Qureshi, and Mazur.
`
`FURTHER ORDERED that pursuant to 35 U.S.C. § 314(c) and
`
`37 C.F.R. § 42.4, inter partes review of the ’315 patent shall commence on
`
`the entry date of this Order, and notice is hereby given of the institution of a
`
`trial; and
`
`16
`
`
`
`IPR2017-01994
`Patent 6,243,315 B1
`
`
` FURTHER ORDERED that no ground other than that specifically
`
`provided above is authorized.
`
`17
`
`
`
`IPR2017-01994
`Patent 6,243,315 B1
`
`
`For PETITIONER:
`
`Barry K. Shelton
`bshelton@sheltoncolburn.com
`
`
`
`For PATENT OWNER:
`
`David Fink
`Fink & Johnson
`texascowboy6@gmail.com
`
`Felix Readus
`federallitigationlaw@gmail.com
`
`
`
`18
`
`
Accessing this document will incur an additional charge of $.
After purchase, you can access this document again without charge.
Accept $ Charge
Still Working On It
This document is taking longer than usual to download. This can happen if we need to contact the court directly to obtain the document and their servers are running slowly.
Give it another minute or two to complete, and then try the refresh button.
A few More Minutes ... Still Working
It can take up to 5 minutes for us to download a document if the court servers are running slowly.
Thank you for your continued patience.
This document could not be displayed.
We could not find this document within its docket. Please go back to the docket page and check the link. If that does not work, go back to the docket and refresh it to pull the newest information.
Your account does not support viewing this document.
You need a Paid Account to view this document. Click here to change your account type.
Your account does not support viewing this document.
Set your membership
status to view this document.
With a Docket Alarm membership, you'll
get a whole lot more, including:
- Up-to-date information for this case.
- Email alerts whenever there is an update.
- Full text search for other cases.
- Get email alerts whenever a new case matches your search.
One Moment Please
The filing “” is large (MB) and is being downloaded.
Please refresh this page in a few minutes to see if the filing has been downloaded. The filing will also be emailed to you when the download completes.
Your document is on its way!
If you do not receive the document in five minutes, contact support at support@docketalarm.com.
Sealed Document
We are unable to display this document, it may be under a court ordered seal.
If you have proper credentials to access the file, you may proceed directly to the court's system using your government issued username and password.
Access Government Site
