`
`ADVANCE
`MT48LC4M4R1(S)
`4 MEG x 4SDRAM
`
`SYNCHRONOUS
`DRAM
`
`FEATURES
`* Fully synchronous;all signals (excluding clock enable)
`registered to positive edge of system clock
`* Meetsall JEDEC functional specifications
`* Dualinternal banks: dual 2 Meg x 4 architecture
`Programmable burst-lengths:2, 4, 8 cycles or full-page
`burst
`
`Programmable burst-sequence: sequentialor interleave
`Burst termination
`Multiple burst READ, single WRITE capability
`Hidden precharge capability with optional automatic
`precharge command
`Programmable READlatency: 1, 2 or 3 clocks
`Industry-standard x8 pinouts, timing, functions and
`packages
`¢ Refresh modes: AUTO and SELF
`¢ Standard and extended AUTO REFRESHrates
`* High-performance CMOSsilicon-gate process
`* Lead-over-chip assembly architecture
`* Single +3.3V £0.3V power supply
`° Low power, 3mW standby; 200mW active, typical
`¢ LVTTL-compatible
`e CKE-controlled power-down and suspend operations
`© Moderegister programming
`¢ JEDEC-standard commandset (pulsed RAS)
`OPTIONS
`MARKING
`* Timing
`(<100 MHz)
`10ns access
`( <83 MHz)
`12ns access
`13.3ns access ( <75 MHz)
`¢ Auto Refresh
`
`-10
`-12
`-13
`
`(15.64s/row)
`4,096-cycle in64ms
`4,096-cycle in 128ms (31.25us/row)
`¢ SELF REFRESH
`Notallowed
`Allowed
`
`none
`S
`
`none
`5
`
`* Plastic Packages
`TG
`44-pin TSOP (400 mil)—forward
`¢ Part Number Example: MT48LC4M4R1TG-10 S
`
`GENERAL DESCRIPTION
`The MT48LC4M4R1(S) is a randomly accessed, solid-
`state memorycontaining 16,777,216 bits organized in a x4
`configuration. It is structured as a dual 2 Meg x 4 DRAM
`
`MT48LC4M4R1(S)
`REV. 4/94
`
`
`
`WVYdSNONOYHONAS
`
`PIN ASSIGNMENT(Top View)
`
`44-Pin TSOP
`FORWARD
`(DD-7)
`
`4 MEG x 4SDRAM
`Pulsed RAS, Dual Bank,
`BURST Mode, 3.3V, SELF REFRESH
`
`
`
`
`MT48C4M4R1TG
`
`with a synchronousinterface. Each byte is uniquely ad-
`
`dressed through a bank-select bit and 20 addressbits. The
`bank select and address are enteredfirst by RAS registering
`
`(row active command) 12 bits (A0-A10, BA) and then
`CASregistering 11 bits (AQ-A9, BA). At CASregistration
`(READ or WRITE command), address bit A10 defines auto-
`
`prechargestate (active HIGH). Bankselection is controlled
`by BA during both RAS and CASregistration.
`The MT48LC4M4R1is designed to operate in a synchro-
`nous, 3.3V memory system. All input and output signals,
`with the exception of clock enable (CKE) during POWER-
`DOWNand SELF REFRESH modes, are synchronized to
`the positive-going edge of the system clock (CLK).
`The synchronous DRAMhasseveral programmable fea-
`tures to allow maximum performance ineachuser’s system.
`Additionally, bank switching between the two internal
`memory banks in conjunction with the programmable
`BURST modeprovides very high-speed performance.
`The synchronous DRAM allows both AUTO REFRESH
`(during normal operation) and SELF REFRESH (for low-
`power, data-retention operation).
`
`Micron Semiconductor,Inc., reservesthe right to change products or specifications without notice.
`HP Exhibit 10087 Paget"
`
`HP Exhibit 1008 - Page 1
`
`

`

`4 MEG x 4SDRAM
`
`ADVANCE
`
`MT48LC4M4R1(S)
`
`MICRON
`
`rental
`
`FUNCTIONAL BLOCK DIAGRAM
`
`
`
`WVddSNONOYHONASZ
`
`CKE ©
`CLK ©
`
`WE o
`
`CAS 0
`
`BA o
`
`AIO o
`AQ
`
`AB tes
`Ar
`:
`AG
`A5 oe
`Ag ©
`A3 0
`A2
`o
`Al
`o
`A0 o
`
`
`BUFFER
`
`
`DATA-OUT
`
`BUFFER
`CONTROLLOGIC
`
`
`
`
`COMMAND
`DECODE RAS 9
`
`ROWDECODER
`
`- 1|ToT||bees
`ES =
`
`
`ADDRESSBUFFER
`
`BURSTCOUNTER
`
`ADDRESSLATCH
`
`COLUMN-
`COLUMN-
`
`
`DQM
`
`pat
`paz
`Das
`pa4
`
`ROW-
`BUFFERS
`ADDRESS
`
`BANK 0
`
`MEMORY
`
`
`REFRESH
`OSCILLATOR
`and TIMER
`
`[-1024--|
`COLUMN
`DECODER
`
`--1024---
`
`ROW-
`ADDRESS
`
`NO. 1 CLOCK
`GENERATOR
`
`LATCH
`
`
`J
`
`
`NO. 2 CLOCK
`
`GENERATOR
`
`ROW.
`
`ADDRESS
`BUFFERS
`
`&
`z 8
`28
`w
`
`BANK 4
`MEMORY
`
`+o Vec
`
`«——~o Vss
`
`MT48LC4M4R1{S)
`REV. 4/94
`
`
`Micron Semiconductor, Inc., reservestheright to change products or specifications without notice.
`
`2-2 tp perp 1008 Pageeon
`
`HP Exhibit 1008 - Page 2
`
`