US005793776A
`[11] Patent Number:
`(45) Date of Patent:
`
`5,793,776
`Aug. 11, 1998
`
`5,535,331
`5,546,568
`5,566,117
`5,568,437
`5,570,381
`5,608,736
`5,614,838
`5,623,503
`
`
`
`..sssseeneee 395/183.21
`7/1996 Swobodaet al.
`8/1996 Bland et al.........
`sae 395/550
`10/1996 Okamura etal. ...
`vee 365/222
`10/1996 Jamal
`...essceo
`. 365/201
`
`10/1996 Schofield .csesssesseesseesseessseenee 371/61
`
`a 37122.3
`3/1997 Bradford et al.
`
`
`vase 32765
`3/1997 Jaber et al.
`.....
`scerssssssssseeecsersnee 371/22.3
`4/1997 Rutkowski
`
`OTHER PUBLICATIONS
`
`Texas Instruments, Boundary—Scan Architecture and IEEE
`Std. 1149.1 (from Chapter 3 of TI’s IEEE 1149.1 Testability
`Primer. SSYA002B) (Nov. 1996).
`IEEE Computer Society, “IEEE Standard Test Access Port
`and Boundary~Scan Architecture”, Published by the Insti-
`tute of Electrical and Electronics Engineers, Inc. (1990),
`including 1149.1a (Oct. 21, 1993) and 1149.1b (Mar. 1,
`1995).
`Maunder and Tulloss. “The Test Access Port and Bound-
`ary~Scan Architecture”, Published by the IEEE Computer
`Society Press, Los Alamitos, California (1990).
`
`Primary Examiner—Robert W. Beausoliel, Jr.
`Assistant Examiner—Nadeem Iqbal
`Attorney, Agent, or Firm—Skjerven, Morrill, MacPherson,
`Franklin & Friel, LLP; David T. Millers
`
`(57]
`
`ABSTRACT
`
`United States Patent
`Qureshiet al.
`
`p19
`
`[54]
`
`[75]
`
`[73]
`
`STRUCTURE AND METHOD FOR SDRAM
`DYNAMIC SELF REFRESH ENTRY AND
`EXIT USING JTAG
`
`Inventors: Amjad Qureshi, San Jose; Sanghyeon
`Baeg, Cupertino, both of Calif.
`
`Assignee: Samsung Electronics Co., Ltd., Seoul.
`Rep. of Korea
`
`[21]
`
`Appl. No.: 733,817
`
`[22]
`
`Filed:
`
`Oct. 18, 1996
`
`[51]
`[52}
`[58}
`
`(56]
`
`Frnt. CUS icceeccccssssscsssssssssecsesssecsssanssessesnsenes GO1R 31/28
`WLS. Ch.
`cesesscssccsnecssesonserteesenconsone 371/22.1; 395/183.18
`Field of Searcle 0...ccscccssssssssssessees 371/22.1, 21.1,
`371/22.31, 22.32, 22.5, 42; 365/201, 222.
`189.01, 233; 395/881, 285, 183.06, 183.18;
`324/765
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`
`
`
`
`2/1989 Mizukami 2.0...csscceressecsseseeee 365/222
`4,807,196
`8/1989 Daniels et al.
`wee 37/25
`4,860,290
`7/1993 Chiles ...0...
`. 373/22.3
`5,228,045
`5/1994 Simpson
`«.........cscsecscseseeserseese 371/22.3
`5,313,470
`5/1994 Peek et ab...
`esssscserssceseseees 395/425
`5,317,712
`ITAGtest logic and a memory controller place an SDRAM
`6/1994 TIwakiri et ab. on.
`esssesssseees 365/222
`5,321,661
`in a self refresh mode prior to beginning JTAGtesting. The
`7/1994 Swoboda et al.
`.
`364/578
`5,329,471
`memory controller can complete a current memory access
`6/1995 Rahman et al.
`.0........cssccceeene 371/22.3
`5,428,623
`
`5,432,747=7/1995 Fuller et al. ws cessscecscsesenes 365/203
`
`and otherwise prepare for the JTAGtest. During the JTAG
`5,434,804
`7/1995 Bock et al. occ sccsssecesecesneees 364/579
`test, self refresh mode operation of the SDRAM retains data
`5,450,364
`9/1995 Stephens, Jr. et al... 365/222
`without the need for a clock signal or refresh signals which
`5,479,652
`12/1995 Dreyeret al.
`..........
`. 395/183.06
`are suspended for the JTAG test. Accordingly, after the
`5,488,688
`1/1996 Gonzales et al.
`..
`« 395/183.1
`JTAGtest, circuit operation can continue withoutreinitial-
`
`5,497,378 oo...eesessseseeees 371/22,33/1996 Amini et ab.
`
`izing data in the SDRAM.
`5,510,704
`4/1996 Parker et al.
`..
`324/158.1
`5,519,715
`5/1996 Haoet al.
`......
` 371/22.3
`16 Claims, 6 Drawing Sheets
`5,524,114—6/1996 Peng ..crccesccoscasserersvassoerenescrsee 371/22.1
`
`
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`HP Exhibit 1004 - Page 1
`
`HP Exhibit 1004 - Page 1
`
`

`

`US. Patent
`
`Aug. 11, 1998
`
`Sheet 1 of 6
`
`5,793,776
`
`i
`
`II
`
`|
`MEMORY
`14>
`|,
`|CONTROLLER|
`|
`
`08 We 1160|STATE !
`MACHINE
`
`|
`jtag_clk_ |
`stop_req
`
`111
`
`{ I I Il
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`113
`
`mcu_idle
`
`
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`
`REGISTER bypass
`
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`jtag_clk_
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`stop_req
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`
`11¢~|
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`SDRAM
`
`HP Exhibit 1004 - Page 2
`
`HP Exhibit 1004 - Page 2
`
`

`

`U.S. Patent
`
`Aug.11, 1998
`
`Sheet 2 of 6
`
`5,793,776
`
`201
`
`jtag_clk_stop_req
`
`211
`
`jtag_sdram_
`
`no jtag_cik_stop_req
`
`
`WAIT
`mcu_idie=0
`
`NORM
`(100ns)
`
`
`C
`mecu_idle=1
`
`no
`
`205
`
`
`
`FIG. 2
`
`207
`
`EXE
`
`mem_add_ud
`mem_add_cnt
`mem_add_reset
`mem_add_set
`
`reg_file_test_en
`
`mem wel
`mem_we2
`mem_cex
`
`REQUIRED
`
`Data Path
`
`FIG. 7
`
`HP Exhibit 1004 - Page 3
`
`HP Exhibit 1004 - Page 3
`
`

`

`U.S. Patent
`
`Aug. 11, 1998
`
`Sheet 3 of 6
`
`5,793,776
`
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`HP Exhibit 1004 - Page 4
`
`HP Exhibit 1004 - Page 4
`
`

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`Aug.11, 1998
`
`Sheet 4 of 6
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`5,793,776
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`HP Exhibit 1004 - Page 5
`
`HP Exhibit 1004 - Page 5
`
`
`

`

`U.S. Patent
`
`Aug. 11, 1998
`
`Sheet 5 of 6
`
`5,793,776
`
`ASSERTINGSIGNALjtag_clk_stop_req
`HIGH TO MEMORY CONTROLLER UNIT
`FROM JTAG LOGIC
`
`501
`
`
`
`
`
`
`
`ASSERTING SIGNAL mc_idle
`
`HIGH TO JTAG LOGIC FROM MEMORY
`CONTROLLER UNIT AFTER MEMORY
`
`CONTROLLER UNIT HAS FINISHED
`CURRENT MEMORY ACCESS
`
`
`
`
`
`ENTERING OF SDRAMsINTO
`
`SELF-REFRESH MODE BY MEMORY
`
`
`CONTROLLER UNIT IF SIGNALS
`
`jtag_clk_stop_req HIGH AND mcu_idle
`HIGH ARE BOTH ASSERTED
`
`
`
`
`
`ASSERTING SIGNALsys_clk_bypass
`HIGH FROM JTAG LOGIC TO SYSTEM
`CLOCK GENERATOR BLOCK TO
`
`BYPASS SYSTEM CLOCK
`
`MAINTAINING SDRAMsIN SELF-
`REFRESH MODE DURING JTAG
`TESTING
`
`ASSERTING SIGNALjtag_sdram_norm
`HIGH TO MEMORY CONTROLLER UNIT
`FROM JTAG LOGIC AFTER JTAG
`
`TESTING IS COMPLETE
`
`
`
`EXITING OF SDRAMs OUT OF
`
`
`SELF-REFRESH MODE BY MEMORY
`CONTROLLER UNIT IF SIGNAL
`
`
`jtag_sdram_norm HIGH IS RECEIVED
`
`
`BY MEMORY CONTROLLER UNIT
`
`FIG. 5
`
`504
`
`507
`
`510
`
`543
`
`516
`
`519
`
`HP Exhibit 1004 - Page 6
`
`HP Exhibit 1004 - Page 6
`
`

`

`U.S. Patent
`
`Aug. 11, 1998
`
`Sheet 6 of 6
`
`5,793,776
`
`$si3ud
`
` LT—_——uajse}wereyepaNpVvyksuesarwelaLLTyTPwoei{II|t1II6J9sppewaw
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`HP Exhibit 1004 - Page 7
`
`HP Exhibit 1004 - Page 7
`
`
`

`

`2
`SDRAM disables the system clock and ali input buffers
`except CKE (clock enable).
`A JTAG Logic is used in accordance with this invention
`to asynchronously communicate with a Memory Controller
`Unit to allow the stopping of system clocks while preserving
`the contents of SDRAM using the self refresh mode. The
`Memory Controller Unit does not permit the system clocks
`to be stopped by the JTAG Logic for testing until
`the
`Memory Controller Unit has finished the current memory
`access operation. Prior to the stopping of the system clocks,
`the Memory Controller Unit places the SDRAM into self
`refresh mode to preserve the memory contents.
`In accordance with one embodimentofthis invention, the
`JTAGLogic includes a JTAG Controller that is connected to
`a set of control registers that provide an interface to the
`Memory Controller Unit. The control registers are necessary
`for the communication of signals between the JTAG Con-
`troller and the Memory Controller Unit because the two
`Controllers operate at different clock frequencies (for
`example, the JTAG Controller operates at 10 MHz and the
`Memory Controller Unit operates at 80 MHz).
`In one embodiment in accordance with this invention.
`when the JTAG Controller wants to stop the system clock to
`allow testing to commence, a signal jtag_clk_stop_req
`high is asserted and communicated via a Memory Control
`Register to a Self-Refresh State Machine which is part of the
`Memory Controller Unit. The Self-Refresh State Machine
`A recent developmentin integrated circuit testing is the
`asserts the signal jtag_clk__stop_request high to a Memory
`use of the JTAG (Joint Test Action Group)test port for in situ
`testing of integrated circuit chips mounted on a board. This
`Controller State Machine which finishes the current memory
`access operation before asserting a signal mcu_idle high
`standard has been adopted by the Institute of Electrical and
`back to the Self-Refresh State Machine. On assertion of the
`Electronics Engineers and is now defined as IEEE Standard
`signal mcu_idle high by the Memory Controller State
`1149.1, IEEE Standard Test Access Port and Boundary-Scan
`Machine and the presence of signal jtag_clk_stop_req
`Architecture, whichis incorporated herein by reference. The
`high, the Self-Refresh State Machine places the SDRAM
`TEEE standard 1149.1 is explained in “The Test Access Port
`into self refresh mode. The Self-Refresh State Machine also
`and Boundary-Scan Architecture” (IEEE Computer Society
`asserts the signal mcu_idle high to an Observation Control
`Press, 1990) which is also incorporated herein by reference.
`Register which is continually scanned by the JTAG Con-
`In the JTAG scheme,a four (or optional five) signal Test
`troller. If the JTAG Controller detects the signal mcu_idle
`Access Port (TAP) is added to each chip or grouping of chips
`high andthe signal jtag_clk__stop,, req high, a signal sys,,
`on a board. The TAP includes four inputs: a test clock
`clk__bypass high is asserted by the JTAG Controller. The
`(TCK), a test mode select (TMS),atest data in (TDI), and
`signal sys_clkbypass high is asserted to a System Clock
`an optional test reset (TRSTN). In addition, there is one
`Generator Block via the Memory Control Register and
`output, a test data output (TDO). TDI and TDOare daisy-
`causes the system clock to be bypassed.
`chained from chip to chip, whereas TCK and TMSare
`broadcast.
`Once the system clock has been bypassed, testing can
`begin andthe contents of the SDRAM are preserved through
`the use of the SDRAM self refresh mode. Whentesting is
`complete,
`the JATAG controller asserts a signal jtag__
`sdram__norm high to the Self-Refresh State Machine via the
`Memory Control Register which causes the SDRAM to be
`taken out of self refresh mode. The JTAG Controller also
`removes the bypass of the system clock by asserting the
`signal sys_clk_bypass low via the Memory Control Reg-
`ister.
`The ability to dynamically enter and exit SDRAM self
`refresh before andafter testing, respectively, using the JTAG
`Logic saves debugging time. Memory and control logic do
`not need to be initialized after testing has taken place.
`
`This application relates to copending applicationsSer. No.
`08/733,132. filed on the same day, entitled “ADAPTABLE
`SCAN CHAINS FOR DEBUGGING AND MANUFAC-
`TURING TEST PURPOSES”, by Baeg, and Ser. No.
`09/733,908, filed on the same day, entitled “CLOCK GEN-
`ERATION FOR TESTING OF INTEGRATED
`CIRCUITS”. by Baeg and Yu, both owned by the assignee
`of this application and incorporated herein by reference.
`
`COPYRIGHT NOTICE
`
`A portion of the disclosure of this patent document
`contains material which is subject to copyright protection.
`The copyright owner has no objection to facsimile repro-
`duction by anyone of the patent document or the patent
`disclosure, as it appears in the Patent and Trademark Office
`patent file or records, but otherwise reserves all copyright
`rights whatsoever.
`
`BACKGROUNDOF INVENTION
`
`The TCKinputis independentof the system clocks for the
`chip so that test operations can be synchronized between
`different chips. The operation of the test logic is controlled
`by the sequence of signals applied at the TMS input. The
`TDI and TDOareserial data input and output, respectively
`while TRSTN inputis used to intitialize a chip or circuit to
`a knownstate. JTAG testing may be used to test suitably
`configured integrated circuits to verify operability. However,
`conventional JTAG testing may requireinitializing memory
`and control logic after each JTAG test procedure since the
`storage cells of SDRAM needto be refreshed periodically
`(for example, every 64 ms) or the stored informationis lost.
`This meansall pre-existing memory data is lost and opera-
`tion cannot be resumed at the point just prior to JTAG
`testing.
`
`5,793,776
`
`1
`STRUCTURE AND METHOD FOR SDRAM
`DYNAMIC SELF REFRESH ENTRY AND
`EXIT USING JTAG
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`45
`
`30
`
`55
`
`SUMMARYOF INVENTION
`
`In accordance with this invention, memory such as
`SDRAMsare put into self refresh mode while JTAG testing
`is performed. Self refresh is a refresh mode available in
`some memory and is preferred for data retention and low
`poweroperation. For an SDRAM inself refresh mode, the
`
`65
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 shows JTAG logic interfaced to a memory con-
`troller unit in accordance with this invention.
`FIG. 2 showsa state diagram of a Self-Refresh State
`Machine in accordance with an embodimentof this inven-
`tion.
`FIG. 3 shows a register cell
`embodiment of this invention.
`
`in accordance with an
`
`HP Exhibit 1004 - Page 8
`
`HP Exhibit 1004 - Page 8
`
`

`

`5,793,776
`
`3
`FIG. 4 showsa set ofregister cells configured as a register
`in accordance with an embodimentof this invention.
`
`FIG. 5 shows a method for SDRAM dynamicself refresh
`entry and exit using JTAG in accordance with this invention.
`FIGS. 6 and 7 illustrate test schemes according to the
`present invention.
`
`DETAILED DESCRIPTION OF INVENTION
`
`Self refresh mode is implemented in some volatile memo-
`ries such as SDRAMs.Putting such memoriesin self refresh
`mode allows the stopping of all clocks,
`including the
`SDRAM clock without loss of the stored information. An
`SDRAM. part NO. KM41651120Aavailable from Samsung
`Electronics, Ltd. is an example of a memory havinga self
`refresh mode. Using the SDRAM self refresh mode during
`STAG testing allows dynamic stopping of clocks, proceed-
`ing with JTAG testing. and resuming operations with
`memory contents preserved.
`In accordance with this invention as shown in FIG. 1,
`JTAG Logic 140 implemements extensions of the JTAG
`standard. Two special shift registers, a Mode Control Reg-
`ister (MCR) 120 and an Observation Control Register
`(OCR) 125 are controlled by standard JTAG Controller 110.
`Shift registers MCR 120 and OCR 125 are used between a
`JTAG Controller 110 and the non-test circuitry because
`JTAG Controller 110 operates at a lower clock speed than
`the non-test circuitry. For example, in one embodiment,
`JTAG Controller 110 runs at a 10 MHz clock while the
`non-test circuitry operates at 80 MHz. Synchronization
`problems between JTAG Controller 110 and the non-test
`circuitry are avoided through the use of the two shift
`registers, MCR 126 and OCR 125.
`In one embodiment, Mode Control Register 120 holds 40
`instruction values while Observation Control Register 125
`holds 70 status values (Further details concerning one
`embodiment of JTAG Logic 140 are presented in Appendix
`A-B, incorporated by reference and available in the file,in
`particular Appendix B includes Verilog code for the test
`circuitry). Instructions are serially shifted into MCR 120
`from JTAG Controller 110 to control the internal logic of an
`integrated circuit. For example.
`in one embodiment the
`circuit
`is a multimedia signal processor system. JTAG
`Controller 110 serially shifts values out of OCR 125 to
`observe the status of the internal logic of the circuit. Shift
`registers MCR 126 and OCR 125 are special shift registers
`consisting of a plurality of register cells where data can be
`serially shifted through each register cell without destroying
`the existing contents of that register cell. The register cell
`used in an exemplary embodiment
`is a standard ASIC
`register cell described in Samsung ASIC Standard Cell
`Library Data Book SEC STD60 which is incorporated
`herein by reference.
`FIG. 3 shows a schematic of a register cell 300 which can
`transmit an input signal dinp with or without storing the
`value of signal dinp in flipflop 310. In register cell 300, input
`signal dinp is input through multiplexer 305 to flipflop 310
`through an invertor 320 and multiplexer 330 as an output
`signal dout.
`Multiplexer 305 selects either a signal tdi on or signal
`dinp depending on whether a signal shift is high or low
`respectively. The use of flipflop 310 and latch 325 allows
`data to be shifted into flipflop 310 while latch 325 preserves
`an outputsignal inst. Multiplexer 330 selects whether output
`signal dout is from latch 325 or input signal dinp.
`If the signal tdi is selected by multiplexer 305, data (tdi)
`maybe shifted through register cell 300 by shifting data into
`
`4
`flipflop 310 while a signal update on lead 385 coupled to
`latch 325 remains high. Latch 325 retains the previously
`latched data on terminal Q of latch 325. An output signal tdo
`from flipflop 310 is input into an identical adjoining register
`cell 430 (see FIG. 4) as the signal tdi at a clock edge if the
`clock signal tck is enabled by AND gate 315 andsignal enb.
`Clock signal tck and the signal enb input to AND gate 315
`which is coupled to the clock terminal of flipfiop 310.
`To change output signal inst from register cell 300, signal
`update is asserted low which causes latch 325 to latch the
`output signal from flipflop 31so that new value inst is now
`provided by register cell 300. Signal inst is the content of
`register cell 300 which is output to, for example, Self-
`Refresh State Machine 112.
`FIG. 4 shows how register cell 300 (shown in detail in
`FIG. 3) is coupled together with other register cells in one
`embodimentof a register such as MCR 120 or OCR 125.
`Four register cells of a register are shown in FIG. 4, and the
`interconnect scheme can be repeated to produce a register of
`the desired size. The signals mode, tck. update, shift, enb,
`and setn are on leads 405, 410, 415, 420, 435, and 440,
`respectively, and couple to register cells 300, 430, 450, and
`470 in parallel.
`Data input signals dinp from JTAG Logic 140 couple to
`register cells 300, 430, 450. and 470 on separate input leads
`380, 445, 446, and 447, respectively. The data outputsignals
`dout from register cells 300, 430, 450, and 470 couple on
`separate leads 330, 461, 462, and 463. respectively, to JTAG
`logic 140.
`Thesignals inst from register cells 300, 430, 450, and 470
`on leads 389, 488, 489, and 490, respectively, are coupled to
`desired locations in JTAG Logic 140 or other parts of the
`circuitry. For example, in one embodiment. tworegister cells
`of MCR 126 provide thesignals inst, jtag_clk__stop_req on
`lead 111 andjtag__sdram_norm, on lead 115 to Self-Refresh
`State Machine 112. Similarly, a register cell in OCR 125
`provides the signals inst and mcu_idie, to JTAG Controller
`110.
`
`Dataserially shifted through register cells 300, 430, 450,
`and 470 is labeled as signal tdi when going into one of
`register cells 300, 430, 450, and 476 and labledas signal tdo
`when coming out of one of register cells 300, 430, 450, and
`470.
`
`Whenentering JTAG test mode, JTAG Logic 140 asserts
`a clock stop request signal (jtag_clk__stop_req on lead 111)
`high to Memory Control Unit 160 of FIG. 1. Signal jtag_
`clk__stop_req high on lead 111 passes to Self-Refresh State
`Machine 112 which the asserts signal jtag_clk_stop_req
`high on lead 111 coupled to Memory Controller State
`Machine 114. Self-Refresh State Machine 112 does not put
`SDRAMs116 into self refresh mode until Memory Con-
`troller State Machine 114 is in an IDLE state and Memory
`Controller State Machine 114asserts a signal mc_idle high
`on lead 113. The state signal mcu_idle from Memory
`Controller State Machine 114is input into shift register OCR
`125 andshifted out to be observed by JTAG Controller 110.
`Once Memory Controller State Machine 114 has finished the
`current memory access operation and signal jtag_clk_
`stop_req is asserted high, all remaining memory access
`requests are disregarded by Memory Controller State
`Machine 114.
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`Onassertion of the signal mcu__idle high with a pending
`clock-stop request, Self-Refresh State Machine 112initiates
`a self refresh command to SDRAMs116. Oncea self refresh
`command has been asserted on SDRAMs 116, the signal
`mc_idle high is asserted by Self-Refresh State Machine 112
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`HP Exhibit 1004 - Page 9
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`HP Exhibit 1004 - Page 9
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`5,793,776
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`Each block represents a step in the method. Block 501is the
`on lead 113 to OCR 125. A few clock cycles after assertion
`step of asserting signal jtag_clk_stop_req high by JTAG
`of the signal mc_idle high on lead 113, System Clock
`Logic 140 to Memory Controller Unit 160. Block 504 is the
`Generator Block 150 to the logic and SDRAMs116 will be
`bypassed for JTAGtesting. To bypass system clock 105, the
`step of asserting signal mc_idle high by Memory Controller
`signal sys_clk_bypass high is shifted into a particular
`Unit 160 to JTAG Logic 140 once Memory Controller Unit
`register cell of MCR 120. Lead 119 is coupled to synchro-
`160 has completed the current memory access operation.
`nous multiplexer 118 and the assertion of signal sys_clk__
`Block 507 is the step of Memory Controller Unit 160 placing
`bypass high on lead 119 disables output from system clock
`SDRAMs116 into self refresh mode if the signals jtag_
`105. Before switching to input “1” on assertion of the signal
`clk__stop_req and mcu_idle are both asserted. Block 510 is
`sys_clk_bypass high on lead 119 synchronous multiplexer
`the step of asserting a signal sys_clk_bypass high from
`118 waits for a rising clock edge to ensure maintenance of
`ITAG Logic 140 to system clock generator 150 to bypass
`proper synchronization.
`system clock 105. Block 513 is the step of maintaining
`During testing, SDRAMs 116 are maintained in self
`SDRAMs116 in self refresh mode during JTAG testing.
`refresh mode to retain stored data. Once JTAGtesting is
`Block 516 is the step of asserting a signal jtag_sdram_
`complete, JTAG Controller 116 asserts the signal jtag_
`norm high to Memory Controller Unit 160 from JTAG Logic
`sdram_norm high on lead 115 which causes Self-Refresh
`140after JTAGtesting has been completed. Block 519 is the
`State Machine 112 to take SDRAMs116 outof self refresh
`step of Memory Controller Unit 160 taking SDRAMs116
`mode and deasserts signal sys_clkbypass. Once SDRAMs
`out of self refresh mode if signal jtag__sdram__norm highis
`116 are out of self refresh mode, and all the system clocks
`received by Memory Controller Unit 160.
`are active. Memory Controller State Machine 114 resumes
`Restarting logic and SDRAMS116at the point of shut-
`processing memory access requests that were pending prior
`down allows dynamic stopping of all clocks, proceeding
`to the start of JTAG testing.
`with JTAGtesting, and resuming operation. Hence, memory
`FIG. 2 shows a state diagram for an embodiment of
`and control logic need not be initialized each time JTAG
`Self-Refresh State Machine 112. Initially, Self-Refresh State
`testing is performed and less memory initializations are
`25
`Machine 112 is in state IDLE 261 if the signal jtag_clk_
`required saving time during the debugging procedure.
`stop_req high is not asserted.If the signal jtag_clk_stop_
`The various embodimentsof the structure and method of
`req high is asserted, Self-Refresh State Machine 112 enters
`this invention that are described above are illustrative only
`state JTAG_CLK_STOP__REQ 203, asserts signal jtag_
`of the principles of this invention and are not intended to
`clk_stop_req to Memory Controller State Machine 114,
`limit the scope of the invention to the particular embodi-
`and waits until signal mcu_idle high is asserted, indicating
`ments described. Many additional and alternative embodi-
`that Memory Controller State Machine 114 has completed
`ments are in the scope of this invention as defined by the
`the current memory access. When the signal mcu__idle is
`following claims.
`asserted, Self-Refresh State Machine 112 enters state
`We claim:
`MCU_IDLE 205 whichasserts the signal mcu__idle high on
`1. A circuit test method comprising:
`lead 113 to OCR 125. JTAG Controller 110 constantly shifts
`asserting a first signal to a memory controller unit from a
`the contents of OCR 125 to determine the state of the
`test logic circuit to indicate a start of the circuit test;
`internal logic and initiates testing once the signal mcu_idle
`asserting a second signal from said memory controller
`high on lead 113 has been shifted in from OCR 125.
`unit
`to said test
`logic circuit
`to indicate that said
`Self-Refresh State Machine 112 enters state ASSERT
`memory controller unit has finished the current
`SELF REFRESH MODE207 and in an exemplary embodi-
`memory access;
`ment where SDRAMs 116 are 16M SDRAMsavailable
`placing of a dynamic memory coupled to said memory
`from Samsung (part nos. KM44S4020A, KM48S2020A,or
`controller unit into a self refresh mode in response to
`KM416S1120A, see Samsung Data Book “16M Synchro-
`both said first signal and said second signal being
`nous DRAM”, March 1996 which is incorporated herein by
`asserted; and
`reference), Self-Refresh State Machine 112 asserts low on
`testing a circuit while said dynamic memory is in said self
`pins CS (chip select), RAS (row address strobe), CAS
`tefresh mode, said self-refresh mode being used to
`(column address strobe) and CKE (clock enable) with high
`preserve pretest contents of said dynamic memory
`on WE (write enable) to put SDRAM 116into self refresh.
`during said testing.
`Oncethe self refresh mode is entered, SDRAM 116 ignores
`2. The method of claim 1. wherein testing disables a clock
`all inputs other than a CKE (clock enable) pin while in self
`refresh state.
`signal used by said dynamic memory when in an operating
`mode.
`Self-Refresh State Machine 112 is in state WAIT TO
`3. The method of claim 1 wherein testing stops a refresh
`REFRESH 209 until the signal jtag_sdram_norm from
`signal to said dynamic memory.
`MCR 120 is high. On receipt of the signal jtag_sdram_
`4. The method of claim 1, further comprising asserting a
`norm high on lead 115, Self-Refresh State Machine 112 exits
`third signal from said test logic circuit to a system clock
`self refresh mode and enters state WAIT NORM 211.In the
`generator block, said third signal causing a bypass of said
`exemplary embodiment, exit from self refresh mode is
`system clock generator block.
`accomplished by removing the bypass of system clock 105
`5. The method of claim 4, further comprising:
`by asserting the signal sys_clockbypass low on lead 119
`asserting a fourth signal to said memory controller unit
`coupled to synchronous multiplexer 118 and then asserting
`from said test logic circuit to indicate that said circuit
`high on the CKE inputs of SDRAMs116. In state WAIT
`test is complete; and
`NORM 211, a NOP (no operation signal) is asserted for a
`minimum of 100 ns on SDRAMs 116to allow SDRAMs 116
`taking of said dynamic memory outof self refresh mode
`by said memory controller unit if said fourth signal is
`to reach idle state. After assertion of signal NOP for 100 ns,
`asserted.
`Self-Refresh State Machine 112 returns to state IDLE 201.
`6. A circuit comprising:
`FIG. 5 shows a method for SDRAM dynamic self refresh
`a memory controller;
`entry and exit using JTAG in accordance with this invention.
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`7
`a test logic coupled to said memory controller wherein
`priorto a circuit test, said test logic assertsa first signal
`that indicates to said memory controller that a system
`clock bypass is being requested and said memory
`controller asserts a second signal to said test logic when
`a current memory access operation is complete; and
`a dynamic memory capable of operating in self refresh
`mode coupled to said memory controller, wherein said
`memory controller places said dynamic memory into
`said self refresh mode in response to said first signal
`and said second signal being asserted, said self refresh
`mode being used to preserve pretest contents of said
`dynamic memory during said circuit test.
`7. The circuit of claim 6, further comprising a system
`clock generator block coupled to said test logic circuit,
`wherein said test logic circuit asserts a third signal prior to
`said circuit test to bypass said system clock generator block.
`8. The circuit of claim 6, wherein said dynamic memory
`is an SDRAM.
`9. The circuit of claim 6. wherein said test logic com-
`prises:
`a test controller; and
`a set of shift registers coupled to both said memory
`controller and said test controller to allow for commu-
`nication between said test controller and said memory
`controller.
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`10. The circuit of claim 9, wherein said test controlleris
`a JTAG Controller.
`11. The circuit of claim 9, wherein said set of shift
`registers comprise:
`a Mode Control Register for holding instruction values;
`and
`
`an Observation Control Register for holding status values.
`12. The circuit of claim 11, wherein said Mode Control
`Register comprises a plurality of register cells through
`which data can be serially shifted without destroying the
`existing contents of each of said plurality of register cells.
`13. The circuit of claim 11, wherein said Observation
`Control Register comprises a plurality of register cells
`through which data can be serially shifted without destroy-
`ing the existing contents of each of said plurality of register
`cells.
`
`14. The circuit of claim 6 wherein said circuit comprises
`an integrated circuit.
`15. The circuit of claim 14 wherein said integrated circuit
`is a multimedia signal processor system.
`16. The method of claim 1 wherein said circuit is a logic
`circuit.
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`HP Exhibit 1004 - Page 11
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`HP Exhibit 1004 - Page 11
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