JOURNAL OF APPLIED PHYSICS
`
`VOLUME 90, NUMBER 5
`
`1 SEPTEMBER 2001
`
`APPLIED PHYSICS REVIEWS
`Ultrathin „Ë4 nm… SiO2 and Si–O–N gate dielectric layers for silicon
`microelectronics: Understanding the processing, structure, and physical
`and electrical limits
`M. L. Greena)
`Agere Systems, Murray Hill, New Jersey 07974
`E. P. Gusev
`IBM Thomas J. Watson Research Center, Yorktown Heights, New York 10598
`R. Degraeve
`IMEC, Leuven 3001, Belgium
`E. L. Garfunkel
`Rutgers University, Piscataway, New Jersey 08854
`共Received 1 March 2001; accepted for publication 21 May 2001兲
`The outstanding properties of SiO2 , which include high resistivity, excellent dielectric strength, a
`large band gap, a high melting point, and a native, low defect density interface with Si, are in large
`part responsible for enabling the microelectronics revolution. The Si/SiO2 interface, which forms
`the heart of the modern metal–oxide–semiconductor field effect transistor, the building block of the
`integrated circuit, is arguably the worlds most economically and technologically important materials
`interface. This article summarizes recent progress and current scientific understanding of ultrathin
`共⬍4 nm兲 SiO2 and Si–O–N 共silicon oxynitride兲 gate dielectrics on Si based devices. We will
`emphasize an understanding of the limits of these gate dielectrics, i.e., how their continuously
`shrinking thickness, dictated by integrated circuit device scaling, results in physical and electrical
`property changes that impose limits on their usefulness. We observe, in conclusion, that although Si
`microelectronic devices will be manufactured with SiO2 and Si–O–N for the foreseeable future,
`continued scaling of integrated circuit devices, essentially the continued adherence to Moore’s law,
`will necessitate the introduction of an alternate gate dielectric once the SiO2 gate dielectric thickness
`approaches ⬃1.2 nm. It is hoped that this article will prove useful to members of the silicon
`microelectronics community, newcomers to the gate dielectrics field, practitioners in allied fields,
`and graduate students. Parts of this article have been adapted from earlier articles by the authors 关L.
`Feldman, E. P. Gusev, and E. Garfunkel, in Fundamental Aspects of Ultrathin Dielectrics on
`Si-based Devices, edited by E. Garfunkel, E. P. Gusev, and A. Y. Vul’ 共Kluwer, Dordrecht, 1998兲, p.
`1 关Ref. 1兴; E. P. Gusev, H. C. Lu, E. Garfunkel, T. Gustafsson, and M. Green, IBM J. Res. Dev. 43,
`265 共1999兲 关Ref. 2兴; R. Degraeve, B. Kaczer, and G. Groeseneken, Microelectron. Reliab. 39, 1445
`共1999兲 关Ref. 3兴. © 2001 American Institute of Physics.
`关DOI: 10.1063/1.1385803兴
`
`TABLE OF CONTENTS
`
`I. INTRODUCTION AND OVERVIEW. . . . . . . . . . . 2058
`A. SiO2 enabled the microelectronics revolution... 2058
`B. Fundamental limits of SiO2 : Is the end in
`sight?. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2060
`II. PHYSICAL CHARACTERIZATION METHODS
`FOR ULTRATHIN DIELECTRICS. . . . . . . . . . . . . 2062
`A. Optical methods. . . . . . . . . . . . . . . . . . . . . . . . . . 2062
`B. X-ray based methods. . . . . . . . . . . . . . . . . . . . . . 2065
`C. Ion beam analysis. . . . . . . . . . . . . . . . . . . . . . . . . 2067
`D. Electron microscopy. . . . . . . . . . . . . . . . . . . . . . . 2072
`
`a兲Electronic mail:mlg@agere.com
`
`E. Scanning probe microscopy. . . . . . . . . . . . . . . . . 2073
`III. ELECTRICAL CHARACTERIZATION
`METHODS AND PROPERTIES. . . . . . . . . . . . . . 2074
`A. Characterization methods. . . . . . . . . . . . . . . . . . . 2075
`1. C – V measurements. . . . . . . . . . . . . . . . . . . . 2075
`2. Gate tunnel current. . . . . . . . . . . . . . . . . . . . . 2076
`3. Charge pumping. . . . . . . . . . . . . . . . . . . . . . . 2077
`B. Oxide degradation during electrical stress. . . . . 2078
`1. Interface trap creation. . . . . . . . . . . . . . . . . . 2078
`2. Oxide charge trapping. . . . . . . . . . . . . . . . . . 2078
`3. Hole fluence. . . . . . . . . . . . . . . . . . . . . . . . . . 2078
`4. Neutral electron trap generation. . . . . . . . . . 2079
`5. Stress-induced leakage current. . . . . . . . . . . . 2080
`6. Discussion of trap generation mechanisms.. 2081
`
`0021-8979/2001/90(5)/2057/65/$18.00
`2057
`© 2001 American Institute of Physics
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`

`2058
`
`J. Appl. Phys., Vol. 90, No. 5, 1 September 2001
`
`Appl. Phys. Rev.: Green etal.
`
`C. Oxide breakdown. . . . . . . . . . . . . . . . . . . . . . . . . 2082
`1. Breakdown modeling. . . . . . . . . . . . . . . . . . . 2082
`2. Soft breakdown. . . . . . . . . . . . . . . . . . . . . . . . 2083
`3. Breakdown acceleration models. . . . . . . . . . 2084
`4. Temperature dependence of breakdown. . . . 2085
`5. Oxide reliability predictions. . . . . . . . . . . . . . 2086
`IV. FABRICATION TECHNIQUES FOR
`ULTRATHIN SILICON OXIDE AND
`OXYNITRIDES. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2086
`A. Surface preparation. . . . . . . . . . . . . . . . . . . . . . . . 2086
`B. Fabrication of ultrathin oxide and oxynitrides.. 2086
`1. Thermal oxidation and oxynitridation. . . . . . 2086
`2. Chemical deposition. . . . . . . . . . . . . . . . . . . . 2088
`3. Physical deposition. . . . . . . . . . . . . . . . . . . . . 2090
`C. Postoxidation processing and annealing. . . . . . . 2090
`D. Hydrogen/deuterium processing. . . . . . . . . . . . . . 2091
`V. THE Si/SiO2 SYSTEM. . . . . . . . . . . . . . . . . . . . . . . 2093
`A. The initial stages of oxygen interaction with
`silicon surfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . 2093
`1. The passive oxidation regime. . . . . . . . . . . . 2094
`2. The active oxidation regime. . . . . . . . . . . . . 2098
`3. The transition regime. . . . . . . . . . . . . . . . . . . 2099
`B. Growth mechanisms of ultrathin oxides,
`beyond the Deal–Grove model. . . . . . . . . . . . . . 2100
`VI. THE Si/SiOxNy SYSTEM. . . . . . . . . . . . . . . . . . . . 2104
`A. Oxynitride properties. . . . . . . . . . . . . . . . . . . . . . 2104
`1. Thermodynamics of the Si–O–N system. . . 2104
`2. Physical properties. . . . . . . . . . . . . . . . . . . . . 2105
`3. Diffusion barrier properties of oxynitride
`layers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2105
`B. Oxynitridation processes. . . . . . . . . . . . . . . . . . . 2106
`1. NO processing. . . . . . . . . . . . . . . . . . . . . . . . 2106
`2. N2O processing. . . . . . . . . . . . . . . . . . . . . . . . 2107
`a. Gas phase N2O decomposition at high
`temperatures.. . . . . . . . . . . . . . . . . . . . . . . 2107
`b. N incorporation and removal during
`N2O oxynitridation.. . . . . . . . . . . . . . . . . . 2108
`3. Nitridation in NH3. . . . . . . . . . . . . . . . . . . . . 2109
`4. Nitridation in N2. . . . . . . . . . . . . . . . . . . . . . 2109
`VII. THE POST-SiO2 ERA: ALTERNATE GATE
`DIELECTRICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2109
`A. Si3N4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2110
`B. Alternate 共higher兲 dielectric constant materials.. 2110
`
`TABLE I. Selected properties of SiO2 gate dielectric layers.
`
`Native to silicon 共SiO2 is the only stable oxide phase on Si兲
`Low interfacial (Si/SiO2) defect density 共⬃1010 eV⫺1 cm⫺2, after
`H2 passivation兲
`Melting point⫽1713 °C
`Energy gap⫽9 eV
`Resistivity ⬃1015 ⍀ cm
`Dielectric strength ⬃1⫻107 V/cm
`Dielectric constant⫽3.9
`
`I. INTRODUCTION AND OVERVIEW
`A. SiO2 enabled the microelectronics revolution
`Nature has endowed the silicon microelectronics indus-
`try with a wonderful material, SiO2 , as is shown in Table I.
`SiO2 is native to Si, and with it forms a low defect density
`interface. It also has high resistivity, excellent dielectric
`strength, a large band gap, and a high melting point. These
`properties of SiO2 are in large part responsible for enabling
`the microelectronics revolution. Indeed, other semiconduc-
`tors such as Ge or GaAs were not selected as the semicon-
`ducting material of choice, mainly due to their lack of a
`stable native oxide and a low defect density interface. The
`metal–oxide–semiconductor field effect
`transistor 共MOS-
`FET兲, Fig. 1, is the building block of the integrated circuit.
`The Si/SiO2 interface, which forms the heart of the MOS-
`FET gate structure, is arguably the worlds most economically
`and technologically important materials interface. The ease
`of fabrication of SiO2 gate dielectrics and the well passivated
`Si/SiO2 interface that results have made this possible. SiO2
`has been and continues to be the gate dielectric par excel-
`lence for the MOSFET. Figure 2 is a transmission electron
`photomicrograph of an actual submicron MOSFET, showing
`the SiO2 gate dielectric as well as the Si/SiO2 interface.
`In spite of its many attributes, however, SiO2 suffers
`from a relatively low dielectric constant 共␬⫽dielectric con-
`stant, or permittivity, relative to air⫽3.9兲. Since high gate
`dielectric capacitance is necessary to produce the required
`drive currents for submicron devices,1,4 and further since ca-
`pacitance is inversely proportional to gate dielectric thick-
`ness, the SiO2 layers have of necessity been scaled to ever
`thinner dimensions, as is shown in Fig. 3. This gives rise to
`a number of problems,
`including impurity penetration
`through the SiO2 , enhanced scattering of carriers in the
`
`FIG. 1. Schematic illustration of a
`submicron 共channel
`length兲 CMOS-
`FET 共complementary metal–oxide–
`semiconductor field effect transistor兲
`共courtesy of C. P. Chang, Agere Sys-
`tems兲.
`
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`

`J. Appl. Phys., Vol. 90, No. 5, 1 September 2001
`
`Appl. Phys. Rev.: Green etal.
`
`2059
`
`FIG. 2. Cross-section transmission electron photomicrographs of a 35 nm
`共channel length兲 transistor, and a detailed view of its 1.0 nm SiO2 gate
`dielectric and Si/SiO2 interface 关from Timp et al. 共Ref. 15兲兴.
`
`channel, possible reliability degradation, high gate leakage
`current, and the need to grow ultrathin and uniform SiO2
`layers.
`This article summarizes recent progress and current sci-
`entific understanding of ultrathin 共⬍4 nm兲 SiO2 and Si–
`O–N gate dielectrics on silicon based devices. 共Si–O–N will
`refer to oxynitride dielectrics for which N/共N⫹O兲⭐0.5, and
`most often much less than that.兲 We will emphasize an un-
`derstanding of the limits of these gate dielectrics, i.e., how
`their continuously shrinking thickness, dictated by integrated
`circuit device scaling, results in physical and electrical prop-
`erty changes that impose limits on their usefulness. We will
`also discuss the near-future need for alternate gate dielectric
`materials such as Si3N4 and other metal oxides and nitrides,
`known as ‘‘high ␬’’ materials.
`In a continuous drive to increase integrated circuit per-
`formance through shrinkage of the circuit elements, the di-
`mensions of MOSFETs and other devices have been scaled
`since the advent of integrated circuits about 40 years ago,
`according to a trend known as Moore’s law.5–8 Moore’s law
`describes the exponential growth of chip complexity due to
`decreasing minimum feature size, accompanied by concur-
`rent improvements in circuit speed, memory capacity, and
`cost per bit. SiO2 gate dielectrics have decreased in thickness
`
`from hundreds of nanometers 共nm兲 40 years ago to less than
`2 nm today, to maintain the high drive current and gate ca-
`pacitance required of scaled MOSFETs. Further, as can be
`seen in Fig. 3, SiO2 thickness continues to shrink. Many
`ultrasmall transistors have been reported, with SiO2 layers as
`thin as 0.8 nm.9–15 The International Technology Roadmap
`for Semiconductors,16 excerpted in Table II, shows that SiO2
`gate dielectrics of 1 nm or less will be required within 10
`years. 关It will become obvious while reading this article that
`SiO2 layers thinner than ⬃1.2 nm may not have the insulat-
`ing properties required of a gate dielectric. Therefore alter-
`nate gate dielectric materials, having ‘‘equivalent oxide
`thickness’’ less than 1.2 nm 共for example兲, may be used.
`Equivalent oxide thickness, tox共eq), is the thickness of the
`SiO2 layer 共␬⫽3.9兲 having the same capacitance as a given
`tdiel (␬⫽␬diel).
`thickness of an alternate dielectric layer,
`Equivalent oxide thickness is given by the relationship:
`tox共eq)⫽tdiel共3.9/␬diel).兴 At these thicknesses, the Si/SiO2 in-
`terface becomes a more critical, as well as limiting, part of
`the gate dielectric. A 1 nm SiO2 layer is mostly interface,
`with little if any bulk character. It contains about five layers
`of Si atoms, at least two of which reside at the interface.17
`Given its prominence, much of this article will focus on the
`physical and electrical properties of the Si/SiO2 interface.
`Due to its commercial relevance, the Si/SiO2 system has
`received an enormous amount of scientific attention. It is
`daunting to count the number of scientific papers: using an
`INSPEC Database we found 36 708 references 共since 1969兲
`devoted to this system. 关We intersected the set ‘‘silicon’’ with
`the set ‘‘共SiO or SiO2 or SiOx兲’’ and then subtracted the set
`‘‘quartz.’’兴 Only 2% of these references are cited in this ar-
`ticle. Several excellent books18–23 and review papers on di-
`electric selection,24 atomic scale interactions between Si and
`O,25–27 oxidation of Si,28–30 SiO2 structure,31 interface struc-
`defects,32–34
`reliability,35
`metrology,36
`ture
`and
`Si–O–N,2,37,38
`and
`general
`growth,
`structure
`and
`properties39,40 have been published. However, some basic
`scientific issues at the forefront of the field remain unre-
`solved. Among these issues are an understanding of the exact
`diffusion mechanisms and incorporation reactions of oxidiz-
`ing and nitriding species in SiO2 , an atomistic understanding
`of the initial stages of oxidation, the role of postoxidation
`processing on physical and electrical properties, the bonding
`structure at and near the Si/SiO2 interface, the relationship
`between local bonding/chemistry and electrical defects, and
`the failure mechanisms in ultrathin dielectrics. All of these
`topics will be addressed in this article.
`It is amusing and instructive to learn that not only is
`SiO2 enabling to microelectronics, but also to some forms of
`life itself. Many forms of animal and plant life have cell
`membranes and exoskeletons composed of pure, crystalline
`共opaline兲 SiO2 .41 This should not be too surprising, since Si
`and O are the two most abundant elements in the earth’s
`crust. In particular, one celled animals called diatoms fashion
`their cell membrane via self-assembly 共molecule by mol-
`ecule兲,
`from SiO2
`dissolved
`at
`ambient
`in H2O,
`temperature.42 They exist in thousands of symmetric mor-
`FIG. 3. Decrease in gate SiO2 共or equivalent oxide兲 thickness with device
`phologies. Figure 4 is a scanning electron microscopy image
`scaling 共technology generation兲. Actual or expected year of implementation
`of the SiO2 exoskeleton of a diatom, on which one can ob-
`of each technology generation is indicated 关adapted from ITRS 共Ref. 16兲兴.
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`

`

`2060
`
`J. Appl. Phys., Vol. 90, No. 5, 1 September 2001
`
`Appl. Phys. Rev.: Green etal.
`
`TABLE II. MOSFET technology timetable, adapted from the International Technology Roadmap for Semicon-
`ductors 共ITRS兲 共Ref. 16兲.
`
`First year of
`production
`
`DRAM generation
`Minimum feature
`size, nm
`Equivalent oxide
`thickness, nm
`
`1999
`
`1G
`180
`
`2001
`
`1G
`160
`
`2002
`
`4G
`130
`
`2005
`
`16G
`100
`
`2008
`
`64G
`70
`
`2011
`
`256G
`50
`
`2014
`
`1T
`35
`
`1.9–2.5
`
`1.5–1.9
`
`1.5–1.9
`
`1.0–1.5
`
`0.8–1.2
`
`0.6–0.8
`
`0.5–0.6
`
`serve SiO2 features as small as 100 nm. It is humbling to
`discover that diatoms evolved with such ‘‘scaled dimen-
`sions’’ 400 million years ago, and suggests that in the future,
`SiO2 , as well as other electronic materials structures, might
`be self-assembled by biomimetic processes. In fact, such
`structures have already been achieved.43,44
`
`B. Fundamental limits of SiO2 : Is the end in sight?
`The use of ultrathin SiO2 gate dielectrics gives rise to a
`number of problems, including high gate leakage current,
`reduced drive current, reliability degradation, B penetration,
`and the need to grow ultrathin and uniform SiO2 layers. We
`may ask when any of these effects will fundamentally limit
`the usefulness of SiO2 as a gate dielectric.45
`Due to the large band gap of SiO2 , ⬃9 eV, and the low
`density of traps and defects in the bulk of the material, the
`carrier current passing through the dielectric layer is nor-
`mally very low. For ultrathin films this is no longer the case.
`When the physical thickness between the gate electrode and
`doped Si substrate becomes thinner than ⬃3 nm, direct tun-
`neling through the dielectric barrier dominates leakage
`current.11,40,46–48 According
`to
`fundamental
`quantum-
`mechanical laws, the tunneling current increases exponen-
`tially with decreasing oxide thickness. Gate leakage currents
`measured on 35 nm transistors fabricated using advanced
`wafer preparation, cleaning, and oxidation procedures14 are
`shown in Fig. 5. The leakage current is seen to increase by
`one order of magnitude for each 0.2 nm thickness decrease.
`
`Assuming a maximum allowable gate current density of 1
`A/cm2 for desktop computer applications, and 10⫺3 A/cm2
`for portable applications, minimum acceptable SiO2 thick-
`nesses 共physical兲 would be approximately 1.3 and 1.9 nm,
`respectively.
`Recent electron energy loss spectroscopy 共EELS兲 experi-
`ments on ultrathin Si/SiO2 interfaces, in a scanning transmis-
`sion electron microscope 共STEM兲, support these findings.17
`Oxygen profiles across the interface were obtained and are
`shown in Fig. 6 for SiO2 films 1.0 and 1.8 nm thick. The
`profiles consist of bulk-like regions and interfacial regions,
`and the interfacial regions are thought to be due to interfacial
`states. Based on this analysis, it has been calculated that the
`minimum oxide thickness, before leakage current becomes
`overwhelming, is 1.2 nm. This comes from the fact that a
`satisfactory SiO2 tunnel barrier is formed when it is equal in
`thickness to six times the decay length of the interfacial
`states, about 6⫻0.12 nm⬵0.7 nm, plus a 0.5 nm contribution
`from interfacial roughness.
`Reduced drive 共drain兲 current has been reported in small
`transistors with ultrathin gate dielectrics.10 Figure 7 shows
`that drain current increases with decreasing SiO2 thickness,
`but
`then falls off; gate leakage current continuously in-
`creases, as expected, with decreasing SiO2 thickness. Thus
`for SiO2 layers thinner than about 1.3 nm there is no advan-
`
`FIG. 5. Gate leakage current measured at 1.5 V as a function of oxide
`thickness 共measured by TEM兲 for 35 nm NMOSFETs. Leakage current in-
`creases one order of magnitude for every 0.2 nm decrease in SiO2 thickness.
`Horizontal lines indicate 1 A/cm2 acceptable leakage current for desktop
`FIG. 4. Scanning electron microscope image of a diatom exoskeleton, com-
`applications, and 1 mA/cm2 acceptable leakage for portable applications
`posed of opaline SiO2 共courtesy of J. Aizenberg, Bell Laboratories/Lucent
`关data of G. Timp, from Green et al. 共Ref. 45兲兴.
`Technologies兲.
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`J. Appl. Phys., Vol. 90, No. 5, 1 September 2001
`
`Appl. Phys. Rev.: Green etal.
`
`2061
`
`FIG. 8. Predicted maximum allowable operating voltage as a function of
`oxide thickness 共Ref. 16兲 共solid line兲, modeled so that requirements of
`power dissipation and circuit speed for successive technology generations
`are met. The Lucent data, at either 25 or 100 °C, estimates the safe operating
`voltages 共for 10 year lifetime reliability兲 for sub-2.5 nm oxides, based on
`measured results and extrapolation principles 共Ref. 62兲. The Lucent data
`clearly show that the 10 year reliability of sub-2.5 nm oxides meets the
`ITRS specifications for SiO2 layers as thin as 1.4 nm.
`
`FIG. 6. Oxygen bonding profiles measured by STEM-EELS. The Si sub-
`strate is on the left and the gate polycrystalline Si is on the right. 共a兲 1.0 nm
`共ellipsometric兲 oxide, annealed at 1050 °C/10 s. The bulk-like O signal 共y
`axis, arbitrary scale兲 yields a FWHM of 0.85 nm, whereas the total O signal
`yields a FWHM of 1.3 nm. The overlap of the two interfacial regions has
`been correlated with the observation of a very high gate leakage current,
`102 A/cm2. 共b兲 a thicker 共1.8 nm ellipsometric兲 oxide, also annealed. The
`interfacial regions no longer overlap and the gate leakage current
`is
`10⫺5 A/cm2 关from Muller et al. 共Ref. 17兲兴.
`
`drive current is not fully understood. One possibility is an
`additional
`scattering
`component
`from the
`upper
`共SiO2/polycrystalline Si gate兲 interface. Some experimental
`evidence exists for this case49 but the observed effect is not
`enough to explain the data in Fig. 7. Another cause could be
`a universal mobility curve effect, i.e., lowered mobility due
`to enhanced scattering because of extreme carrier confine-
`ment in the inversion layer of the ultrathin oxide. The issue
`of long-range electrostatic interactions between charges in
`very heavily doped gate, source, and drain regions, and elec-
`trons traveling in the channel, was recently theoretically
`studied50 using both semiclassical
`two-dimensional self-
`consistent Monte Carlo–Poisson simulations and a quantum
`mechanical model based on electron scattering from gate–
`oxide interface phonons. It was shown that excitation and
`absorption of plasma modes in the gate region may result in
`a net momentum loss of carriers in the channel, thus decreas-
`ing their velocity, and leading to reduced drain current.
`Reliability 共lifetime to breakdown兲 of ultrathin SiO2 is a
`major concern for oxide scaling into the sub-2 nm range and
`currently a contentious issue.35,40,51–62 Electrons traveling
`through the SiO2 layer may create defects such as electron
`traps and interface states63–65 that in turn, upon accumulation
`to some critical density, degrade the insulating properties of
`the oxide. The accumulated charge the film can withstand
`before its breakdown (Qbd) decreases with oxide thickness.54
`Recently, it was predicted that oxide films thinner than about
`2.2 nm would not have the reliability required by the indus-
`try roadmap.54 Data from another research group,62 shown in
`Fig. 8, indicates that acceptable reliability will be achievable
`for SiO2 thicknesses as low as 1.4 nm. At about 1.0 nm
`thickness, the statistical probability of a percolation path may
`reduce reliability to an unacceptable level.66 One should
`mention that all reliability data is model dependent. Unlike
`directly measured parameters such as the gate leakage and
`drive currents, reliability studies always involve extrapola-
`FIG. 7. Drive current vs leakage current for two ultrasmall 共gate lengths of
`70 and 140 nm兲 NMOSFETs. In both cases it can be seen that gate current
`tions from relatively high 共⬃2.5–4 V兲 stress voltages to real
`increases, as is expected, with decreasing SiO2 thickness. However, drain
`device operating voltages 共⬃1.0–1.2 V兲. The extrapolations
`current first increases and then falls off with decreasing oxide thickness.
`are based on different, although most often percolation type,
`Decreasing the oxide thickness past the fall-off thickness confers no further
`models with several parameters extracted from the high
`advantage on the device 关from Timp et al. 共Ref. 10兲兴.
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`tage in performance 共drive current兲 for incurring the burden
`of an ever-increasing gate leakage current. This would sug-
`gest that SiO2 layers thinner than 1.3 nm no longer deliver
`any performance advantage. The cause of the decreased
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`J. Appl. Phys., Vol. 90, No. 5, 1 September 2001
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`Appl. Phys. Rev.: Green etal.
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`stress voltage experiments. Finally, the real impact of oxide
`breakdown on circuit performance, which ultimately is the
`critical issue, has yet to be understood.
`Thus the fundamental limits imposed on SiO2 are exces-
`sively high gate leakage current, reduced drive current, and
`reliability. The first two of these properties impose a limit of
`⬃1.3 to 1.4 nm as the thinnest SiO2 acceptable. Although
`potential improvements in interfacial roughness may push
`the leakage limit to ⬃1.0 nm, reliability may then be the
`limiting factor. Complementary metal–oxide–semiconductor
`共CMOS兲 applications of SiO2 or Si–O–N gate dielectrics are
`limited neither by the ability to grow the ultrathin films in a
`manufacturing environment 共see Sec. IV兲, nor to suppress
`the diffusion of B through them 共see Sec. VI兲. Therefore,
`according to Table II, SiO2 will have to be replaced in as
`little as 5 years if gate capacitance is to increase according to
`projected scaling. Technology generations that require ⬍1.0
`nm equivalent SiO2 thickness will have to rely on alternate,
`high-␬gate dielectrics 共see Sec. VII兲. This transition will not
`be simple to implement, as SiO2 is the major reason that
`silicon technology has been so successfully integrated thus
`far. One can say that SiO2 has only one disadvantage, low ␬,
`and most alternate gate dielectrics currently have only one
`advantage, high ␬.
`In this introductory section we have systematically ex-
`amined the repercussions of decreasing SiO2 gate dielectric
`thickness on several physical and electrical parameters. Al-
`though the end of SiO2 scaling may be in sight, it will be
`manufactured in integrated circuits for at least the next de-
`cade. This article is not intended to be an obituary for SiO2 ,
`however, since its useful life will undoubtedly be extended
`by innovations in device design, e.g., dual gate dielectric
`thickness devices67,68 or vertical MOSFETs.69
`
`FIG. 9. Principles of an ellipsometric measurement.
`
`beam reflected from a sample surface, as is illustrated in Fig.
`9. The measured parameters are the ellipsometric angles ⌿
`and ⌬, defined from the ratio
`R 储 /R⬜⫽tan共⌿ 兲exp共i⌬ 兲
`共1兲
`of the Fresnel reflection coefficients R 储 and R⬜ for the light
`polarized parallel and perpendicular to the plane of inci-
`dence. The reflection coefficients are determined by the op-
`tical properties and composition of the substrate and overlay-
`ers, their thicknesses, and morphology. The parameters ⌿
`and ⌬ can be measured either at a given wavelength of light,
`i.e., single wavelength ellipsometry 共most often 633 nm兲, or
`as a function of photon energy, i.e., spectroscopic ellipsom-
`etry. The single wavelength configuration is often used for
`fast, nondestructive, on-line monitoring of film thickness,
`provided that the refractive index of the film is known. The
`spectroscopic mode allows determination of the refractive
`index 共␩兲 as well as the thickness. For SiO2 films on Si, good
`agreement has been demonstrated, Fig. 10, between the el-
`lipsometric oxide thickness and thickness values determined
`by transmission electron microscopy 共TEM兲 and x-ray pho-
`toelectron spectroscopy 共XPS兲, for films as thin as ⬃2 nm.108
`Since the very first publications on Si oxidation, ellipsometry
`
`II. PHYSICAL CHARACTERIZATION METHODS FOR
`ULTRATHIN DIELECTRICS
`In this section we will briefly introduce the various ana-
`lytical techniques useful for studying the physical properties,
`such as thickness, composition, density, crystallinity, bond-
`ing, and surface and interface morphology, of ultrathin gate
`dielectrics. We will overview only the basic principles of the
`techniques, the information they yield, and their strengths
`and limitations. The techniques are grouped into the follow-
`ing categories: optical, x-ray, ion beam, electron beam, and
`scanning probe microscopy. Each technique will be repre-
`sented by important dielectric results. Our choice of tech-
`niques is not exhaustive, but primarily reflects our perception
`of the impact of the various techniques on the understanding
`of the field.
`A. Optical methods
`The most commonly used optical techniques are single
`wavelength and spectroscopic ellipsometry,29,70–85 reflec-
`tance difference spectroscopy 共RDS兲,86–88 second harmonic
`generation 共SHG兲,89–97 and Fourier transform infrared spec-
`FIG. 10. Oxide thickness measured by x-ray photoemission spectroscopy,
`troscopy 共FTIR兲.82,98–107
`compared to measurements on the same films by ellipsometry, transmission
`Ellipsometry is based on the measurement and subse-
`electron microscopy, and capacitance–voltage techniques 关from Lu et al.
`quent modeling of changes in the polarization state of a light
`共Ref. 108兲兴.
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`

`J. Appl. Phys., Vol. 90, No. 5, 1 September 2001
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`Appl. Phys. Rev.: Green etal.
`
`2063
`
`FIG. 11. Si共100兲 oxidation kinetics at different temperatures, as measured
`by high temperature ellipsometry 关from Massoud et al. 共Ref. 73兲兴.
`
`FIG. 13. Schematic illustrations of various polarized light methods for thin
`film characterization 关adapted from Drevillon et al. 共Ref. 88兲兴.
`
`has been the tool of choice to measure film thickness.
`Knowledge of the thickness is critical in modeling oxidation
`kinetics and determining growth mechanisms.29 An example
`of its application is shown in Fig. 11.
`The ellipsometric parameters, ⌿ and ⌬, can be detected
`with very high accuracy, making ellipsometry one of the
`most sensitive thickness measurement techniques. However,
`the interpretation of the measurements is very model depen-
`dent, especially in the ultrathin regime where ␩may become,
`as is the case for SiO2 , a function of thickness.78,109,110 For
`more
`complex gate dielectrics
`such as Si–O–N or
`SiO2 /Si3N4 multilayer stacks, the analysis is further compli-
`cated by the fact that ␩changes with the composition of the
`film.111,112 For example, at a wavelength of 630 nm, ␩varies
`linearly with the amount of N in the film, Fig. 12, from a
`value of 1.46 for SiO2 to a value of approximately 2.0 for
`stoichiometric Si3N4 .111
`Sensitivity to the Si/SiO2 interface of ultrathin films is
`relatively low using conventional ellipsometric configura-
`tions. Interfacial sensitivity can be enhanced via an immer-
`sion ellipsometry technique, in which the Si/SiO2 sample is
`placed in a liquid having an ␩close to that of SiO2 , thereby
`
`thickness of the oxide
`effectively increasing the optical
`overlayer.75,113 Sensitivity to surfaces and interfaces may
`also be significantly enhanced using RDS. While in conven-
`tional ellipsometry the measurements are performed under
`oblique incidence, in RDS the primary photon beam is nor-
`mal to the surface, as is illustrated in Fig. 13. The analysis is
`based on the determination of the reflectance differences of
`the light polarized along principle axes of the crystal surface.
`The anisotropic properties of surfaces and interfaces can
`therefore be determined. RDS has been applied to the study
`of Si oxidation as well as the wet cleaning of Si.86,87 Details
`of the RDS technique and its application to semiconductor
`surfaces and interfaces have recently been reviewed.88
`Another important method for the selective optical prob-
`ing of surfaces and interfaces is SHG.89–97 In general, the
`polarization amplitude, P, of a photon beam of optical fre-
`quency ␻, interacting with a solid sample, can be expressed
`in terms of an expansion over the amplitude of the electro-
`magnetic field 共E兲, as
`P⬃␣共␻兲E共␻兲⫹␤共␻,2␻兲E2共␻兲⫹¯ .
`共2兲
`The first term of the polynomial expansion represents the
`linear optical response, which is the basis of the ellipsomet-
`ric and RDS techniques described above. In centrosymmetric
`solids such as Si, the second, nonlinear coefficient ␤is non-
`zero only at interfaces, where crystal symmetry is broken.
`The electrical dipoles present at such interfaces give rise to
`the surface/interface selectivity of SHG. Recently, SHG gen-
`eration methods have been used to investigate the structure
`of Si/SiO2 and Si/Si3N4 interfaces, Fig. 14, as well as the
`initial stages of Si oxidation in N2O and O2 .89–92,95,96
`FTIR is a powerful method to examine chemical 共sto-
`ichiometry, bonding and impurities兲, and structural 共stress,
`transitional
`layer兲
`aspects
`of
`ultrathin
`dielectric
`films.82,98–106,114,115 The technique, based on the absorption
`FIG. 12. Refractive index of Si–O–N layers as a function of composition
`of light in the infrared region of the spectrum, is sensitive to
`关adapted from data in Brown et al. 共Ref. 111兲兴.
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