119)
`United States Patent
`4,951,100
`[11] Patent Number:
`Parrillo
`
`[45] Date of Patent: Aug. 21, 1990
`
`[54]
`
`HOT ELECTRON COLLECTOR FOR A LDD
`TRANSISTOR
`
`[75]
`
`Inventor:
`
`Louis C. Parrillo, Austin, Tex.
`
`[73]
`
`Assignee:
`
`Motorola, Inc., Schaumburg,II.
`
`[21]
`
`Appl. No.:
`
`374,703
`
`[22]
`
`(51)
`[52]
`
`[58]
`
`[56]
`
`Filed:
`
`Jul. 3, 1989
`
`Int. C15 oeescsetstsssesscersesenseessenenens HOIL 29/78
`WLS. C1. ceeesscessecesesssesseeceeeneees 357/233; 357/23.12;
`357/53; 357/59
`Field of Search................... 357/23.3, 23.5, 23.12,
`357/53, 23.4, 59 E, 59 G, 59 J; 437/44, 35
`
`References Cited
`U.S. PATENT DOCUMENTS
`6/1988
`9/1988
`2/1989
`6/1989
`
`Mizutani et al. oo. 357/23.3
`Horiuchi etal....
`.- 357/23.3
`
`
`Matsui.............
`«- 357/23.5
`Chiu et al.
`....scseecssesssceceeseees 437/34
`
`4,754,320
`4,769,686
`4,808,544
`4,843,023
`
`FOREIGN PATENT DOCUMENTS
`
`59-231864 12/1984 Japan .....cescessssssseecssseeseeees 357/23.3
`62-217665
`9/1987 Japan...
`« 357/23.3
`
`63-296278 12/1988 Japan ...
`.» 357/233
`
`Primary Examiner—William D. Larkins
`Assistant Examiner—Donaid L. Monin
`Attorney, Agent, or Firm—James L. Clingan, Jr.
`
`ABSTRACT
`[7]
`A lightly-doped drain (LDD) structure has conductive
`shield overlying the lightly-doped drain and source
`portions to collect and/or remove hot carriers which
`can otherwise cause instabilities such as gain degrada-
`tion and threshold voltage shifts in short-channel MOS
`devices. The hot carriers eventually deteriorate the
`performance of the transistor to the point where the
`transistor provides insufficient performance. Thus, the
`lifetime of a transistor is affected by the degradation
`caused by the formation of hot carriers. The lifetime is
`increased by collecting the hot carriers in the conduc-
`tive material over the lightly-doped source and drain.
`
`14 Claims, 4 Drawing Sheets
`
`
`
`TSMC 1313
`TSMC1313
`
`

`

`
`
`US. Patent—Aug. 21, 1990 Sheet 1 of 4 4,951,100
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`
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`
`
`FTG.1
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`

`

`US. Patent
`
`oS
`
`Sheet 2 of 4
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`4,951,100
`
`Aug. 21, 1990
`
`19 22
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`

`

`US. Patent
`
`Sheet 3 of 4
`
`4,951,100
`
`Aus. 21, 1990
`a 59
`
`66 62 69
`
`
`
`

`

`US. Patent
`
`Sheet 4 of 4
`
`Aug. 21, 1990
`
`4,951,100
`
`

`

`1
`
`4,951,100
`
`HOT ELECTRON COLLECTOR FOR A LDD
`TRANSISTOR
`
`FIELD OF THE INVENTION
`
`The invention relates MOS transistor device struc-
`tures, and more particularly, to device structures of
`MOStransistors which have a lightly-doped drain
`(LDD).
`BACKGROUND OF THE INVENTION
`
`Lightly-doped drain (LDD)transistors have a lightly
`doped portion at both ends of the channel with heavily-
`doped portions spaced from the channel
`to form
`contacts. In the use of LDD transistors there has been
`discovered a problem created by hot carriers that result
`from high electric fields. Although attenuated in LDD
`transistors, hot carriers still cause a particular problem
`for the lightly-doped sources and drains of the LDD
`structure. Hot electrons get into the oxide above the
`lightly-doped regions and tend to deplete the mobile
`carriers from the surface of these lightly-doped regions.
`This causes an increase in the source and/ordrain resis-
`tance which results in degradation in the gain of the
`transistor. This degradation is less if there are more
`mobile carriers which can be obtained by increasing the
`doping level ofthe lightly-doped source and drain. The
`increased doping level, however, also increases the
`internal electric field and the number of generated hot
`carriers, which thus increases the tendency of the hot
`carriers to drive the mobile carriers away from the
`surface of the lightly-doped regions. There has been
`determined an implant dosage of about 5 x 1013 of phos-
`phorusfor N channel transistors which has been found
`to be the optimum dosage for minimizing this problem.
`The problem, however, still exists even at that dosage.
`Additionally, the preferred dosage for other character-
`istics, such as gate-aided and avalanche breakdown,is
`less than that. Thus, the hot electrons and holes gener-
`ated by internal electric fields reduce the useful lifetime
`ofthe transistor.
`One solution was disclosed in an article, “A New
`LDDTransistor With Inverse T-Gate Structure,” Tial-
`Yuan Huang et al, IEEE Electron Device Letters, Vol.
`EDL-8, No. 4, Apr. 1987. In that case the structure
`involved a T-shaped polysilicon gate which had a thick
`portion over the channel and a thin portion which was
`implanted through bythefirst implant to form thelight-
`ly-doped portion of the drain. Sidewall spacers were
`formed on the thick portion of the polysilicon gate for
`the mask for the second, heavy implant. This, however,
`resulted in close proximity of the gate to the heavily
`doped portion of the source/drain. There was then
`present excessive capacitance between the gate and the
`heavily doped source/drain regions. Such excessive
`capacitance is deleterious to circuit performance.
`SUMMARYOF THE INVENTION
`
`20
`
`25
`
`40
`
`45
`
`50
`
`Accordingly, it is an object of the present invention
`to provide an improved MOStransistor structure.
`It is another object of the present invention to pro-
`vide a MOStransistor with an improved LDDstruc-
`ture.
`
`In carrying out these and other objects of the inven-
`tion, there is provided, in one form, a transistor formed
`in an active region of a substrate, having a first insulator
`layer, a gate, a secondinsulatorlayer, a lightly-doped
`source region, a lightly-doped drain region, a channel
`
`65
`
`2
`region, a first heavily-doped region, a second heavily-
`doped region, a first conductive strip, and a second
`conductive strip. The first insulator layer is on the ac-
`tive region. The gate overlies the first insulator layer at
`an intermediate portion of the active region and leaves
`a first portion and a second portion ofthe active region
`uncovered by the gate. The gate has a first side and a
`secondside. The first and second sides are aligned with
`the first and second portions, respectively, of the active
`region. The second insulator layer coats the first and
`second sides of the gate. The lightly-doped source re-
`gion is in the first portion of the active region and
`aligned substantially with thefirst side of the gate. The
`lightly-doped drain region is in the second portion of
`the active region aligned substantially with the second
`side of the gate. The channel region is in the active
`region, under the gate, and between the lightly-doped
`source region and the lightly-doped drain region. The
`first heavily-doped region is in the first portion of the
`active region, offset from thefirst side of the gate, and
`adjoining the lightly-doped source region. The second
`heavily-doped region is in the second portion of the
`active region,
`is offset from the second side of the
`polysilicon gate, and adjoins the lightly-doped drain
`region. The first conductive strip adjoins the insulator
`coating on thefirst side of the gate and is overat least
`a portion of the lightly-doped source. The second con-
`ductive strip adjoins the insulator coating on the second
`side of the gate and is over at least a portion of the
`lightly-doped source.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG.1 is a cross-section of a portion of an integrated
`circuit at a stage in processing according to the prior
`art;
`FIG.2 is a cross-section of the portion of the inte-
`grated circuit of FIG. 1 at a subsequentstage in process-
`ing according to a preferred embodimentofthe inven-
`tion;
`FIG. 3 is a cross-section of the portion of the inte-
`grated circuit of FIG. 1 at a stage in processing subse-
`quent to that shown in FIG. 2 according to the pre-
`ferred embodiment of the invention;
`FIG.4 is a cross-section of the portion of the inte-
`grated circuit of FIG. 1 at a stage in processing subse-
`quent to that shown in FIG. 3 according to the pre-
`ferred embodimentof the invention;
`FIG. 5 is a cross-section of the portion of the inte-
`grated circuit of FIG.1 at a stage in processing subse-
`quent to that shown in FIG.4 according to an optional
`embodiment of the invention;
`FIG.6 is a cross-section of an alternative to that of
`FIG.2 at a subsequent stage in processing to that shown
`in FIG. 1 according to an alternative preferred embodi-
`ment of the invention;
`FIG.7 is a cross-section of the portion of the inte-
`grated circuit of FIG. 6 at a stage in processing subse-
`quent to that shownin FIG.6 according to the alterna-
`tive preferred embodimentof the invention;
`FIG. 8 is a cross-section of the portion of the inte-
`grated circuit of FIG. 8 at a stage in processing subse-
`quent to that shownin FIG.8 according to the alterna-
`tive preferred embodimentof the invention;
`FIG. 9 is a cross-section of the portion of the inte-
`grated circuit of FIG. 8 at a stage in processing subse-
`quent to that shown in FIG. 8 accordingto the alterna-
`tive embodimentof the invention;
`
`

`

`4,951,100
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`
`3
`FIG.10 is a simplied layout of a transistor according
`to either embodimentof the invention; and
`FIG.11 is a simplied layout of the transistor of FIG.
`10 at a stage in processing subsequent to that shown in
`FIG.10.
`
`4
`spacer 27 and a portion 37 of polysilicon under sidewall
`spacer 37. Portion 36 also extends along left side 21 of
`polysilicon gate 16. Similarly, portion 37 extends along
`right side 23 of gate 16. A transistor 38 is formed of
`source and drain regions 33 and 34, respectively, and
`gate 16. Portions 36 and 37 are in close proximity to the
`left and right bottom corners, respectively, of gate 16 of
`transistor 38 where the highest electric field strength
`Shownin FIG.1 is a cross-section of a portion 10 of
`occurs during normal operation of transistor 38. This
`an integrated circuit formed in a P— substrate 11 at a
`highest field strength location is at or near the location
`stage in processing according to the prior art compris-
`where hot electrons are most generated. Thus, portions
`ing a field oxide region 12, a field oxide region 13, an
`36 and 37 located over portions 33 and 34 are in position
`active region 14 therebetween, an oxide layer 15 over
`to collect these hot electrons instead of having them
`active region 14, a polysilicon gate 16, a source region
`become trapped in oxide 15 at the interface of channel
`17 which is lightly-doped to N—, a drain region 18
`24 or in thicker oxide 28 which lies above portion 37.
`Portions 36 and 37 can be considered shields. The col-
`which is lightly doped to N—, and a reoxidation layer
`19 coating polysilicon gate 16. The structure of portion
`lection of these electrons prevents them from adversely
`10 shownin FIG.1 is formed in conventional fashion by
`affecting the mobile carriers in drain region 34. The
`electrons that do remain in thin oxide 15 between shield
`forming field oxide regions 12 and 13, growing oxide
`layer 15 in active region 14, forming a polysilicon layer
`portion 37 and N— portion 34 are imaged on shield
`over oxide layer 15 which is etched to form gate 16,
`portion 37. Shield portion 37 thus has a positive charge
`implanting source and drain regions 17 and 18 to N—,
`accumulation near the electrons trapped in thin oxide
`and reoxidizing gate 16 to form reoxidation layer 19.
`15. Thus, the tendency of these trapped electrons to
`Polysilicon gate 16 has a left side 21, a top side 22, and
`deplete N— portion 34 is reduced by the positive
`a right side 23 which are coated by reoxidation layer 19.
`charge that is imaged onto shield portion 37. The pres-
`. Polysilicon gate 16 is formed intermediate active region
`ence of shield portions 36 and 37 for the transistor
`14 so that source region 17 and drain region 18 are
`formed as portion 10 increases lifetime of the transistor
`uncovered by gate 16. A channel region 24 is in sub-
`and allowsfor the reduction in the doping level of drain
`strate 11, under gate 16, and between source region 17
`region 34.
`and drain region 18. Portion 10 shown in FIG. 1 could
`Portion 36 and region 31 can be connected together,
`be a portion of a well in a CMOSprocess.
`and portion 37 and region 32 can be connected together
`Shownin FIG. 2 is portion 10 witharelatively thin
`so as to avoid accumulating electrons in shield portions
`layer of polysilicon 26 deposited thereover. Polysilicon
`36 and 37, respectively. One example is portion 10, as
`is used in one embodimentof the invention, but another
`shownin FIG.5, after an oxide etch and formation of
`conductive material could also be used. Polysilicon is
`salicide on the silicon exposed by the oxide etch. The
`oxide etch either does not removeall of the oxide from
`actually a semiconductor, but in most applicationsit is
`conductive in nature. As used herein, conductive mate-
`top 22 of gate 16 or is masked from etching the oxide on
`rial includes polysilicon. Polysilicon layer 26 is confor-
`top 22 of gate 16. The oxide on top 22 of gate 16, which
`mal in nature so that left side 21, top side 22, and right
`is shown as oxide 19 in FIG. 4, can be made to be
`side 23 ofpolysilicon gate 16 are coated by polysilicon
`thicker than oxide 15 which overlies regions 31 and 32.
`layer 26 as well as source region 17 and drain region 18.
`One known way of making this oxide thickeris to form
`After polysilicon layer 26 has been deposited, sidewall
`a layer of oxide over the polysilicon before it is etched
`spacers 27 and 28 are formed as shownin FIG.3. Side-
`to form the polysilicon gate. This layer of oxide would
`wall spacers 27 and 28 are adjacent to sides 21 and 23,
`be selectively etched with the same mask whichis used
`respectively, of polysilicon gate 16. After formation of 45
`to etch the polysilicon to form the gate. This would
`sidewall spacers 27 and 28, an N+ implant is performed
`increase the complexity of the etch of the gate butthis
`to form heavily-doped region 31 in source region 17 and
`is a known technique. Thus, if oxide 19 is sufficiently
`heavily-doped region 18 in drain region 18. Such spacer
`thick, there will still be oxide left on top 22 of gate 16
`material may be a deposited oxide for example. This
`after the oxide etch which removes the portions of
`leaves a lightly-doped region 33 in source region 17 and
`oxide 15 which overlie regions 31 and 32 is performed.
`This oxide etch does removeall of the oxide from the
`a lightly-doped region 34 in drain region 18. Sidewall
`spacer 21 is located over region 33 and acts as a mask
`tops of heavily-doped regions 31 and 32. There is then
`during the N+ implant so that region 33 is not doped
`formed on the exposed siliconasalicide portion 41 over
`during the N-++ implant. Gate 16 acts as a mask during
`heavily-doped region 31 and a salicide portion 42
`the N+ implant so that channel 24 is not doped by the
`formed over heavily-doped region 32. Salicide portions
`N-+ implant. Sidewall spacer 28 is located over region
`41 and 42 makeelectrical contact with polysilicon por-
`34 and acts as a mask during the N+ implant so that
`tions 36 and 37. This contact can be quite resistive and
`region 34 is not doped during the N+ implant. Thus,
`still provide the desired function of providing a path for
`portions 33 and 34 are substantially aligned with left and
`electrons and/orholes to escape polysilicon portions 36
`right sides 21 and 23, respectively, and adjoin N+ re-
`and 37 out the source and drain, respectively, so as to
`gions 31 and 32, respectively. The N+ implant as
`avoid accumulating electrons and/orholes in the shield
`shownis the same depth as that of the N— implant but
`portions.
`either implant could be deeper than the other.
`Another method for obtaining shields for the same
`After the N+ implant, an etch of polysilicon layer 26
`purpose as shield portions 36 and 37 is to perform a
`is performed using sidewall spacers 27 and 28 and
`heavy, shallow silicon implant on the oxide which is
`polysilicon gate 16 as a mask. Shownin FIG.4 is por-
`over the source and drain. The implant ofsilicon is
`tion 10 after this etch of polysilicon layer 26. After this
`sufficiently shallow and heavy that a silicon layer is
`etch there is a portion 36 of polysilicon under sidewall
`formed near the surface of the implanted oxide. Such a
`
`10
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`4,951,100
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`6
`layer can act as a “seed”for the selective growth of a
`implanted portion 64, and polysilicon portion 67 which
`film layer such as polysilicon. The selective deposition
`are between sidewall spacer 71 and field oxide 52. Also
`of polysilicon is then performed so that polysilicon is
`removed are implant region 62, polysilicon portion 69,
`deposited on the oxide which is over the source and
`and the portion of reoxidation layer 59 which is on top
`drain. The structure of portion 10 shown in FIG. 1
`side 62 of gate 56. After this etch there remains a por-
`would be a convenient starting point. Shown in FIG.6
`tion 81 of selectively-deposited polysilicon portion 67
`is a portion 50 of an integrated circuit at a stage in pro-
`which underlies sidewall spacer 71. Similarly, there also
`cessing after that which forms a structure like that of
`remains a portion 82 of selectively-deposited polysili-
`FIG. 1. Portion 50 is formed in a P— substrate 51 and
`con portion 68. Portions 81 and 82 act as shields as
`comprises a field oxide region 52, a field oxide region
`described for shield portions 36 and 37 in FIGS. 4 and
`53, an active region 54 therebetween, an oxide layer 55
`5. Salicide regions 77, 78, and 79 are then formed on
`over active region 54, a polysilicon gate 56, a source
`exposedsilicon surfaces above regions 73 and 74 and on
`region 57 whichis lightly-doped to N—, a drain region
`top side 62 of gate 56, respectively. Salicide region 77 is
`58 which is lightly doped to N—, and a reoxidation
`formedto a sufficient thickness to contact shield portion
`81 which thus establishes an electrical contact between
`layer 59 coating polysilicon gate 56. The structure of
`portion 50 shown in FIG.6 is formed by formingfield
`shield portion 81 and region 73. Similarly, salicide re-
`oxide regions 52 and 53, growing oxide layer 55 in
`gion 78 is formed to a sufficient thickness to contact
`active region 54, forming a polysilicon layer over oxide
`shield portion 82 and thus establish an electrical contact
`layer 55 which is etched to form gate 56, implanting
`between region 78 and shield portion 82.
`Portion 50 in FIG.9 thusalso has the shields for the
`source and drain regions 57 and 58 to N—, and reoxidiz-
`ing gate 56 to form reoxidation layer 59. Polysilicon
`desirable collection of hot carriers. The transistor of
`gate hasaleft side 61, a top side 62, and a right side 63
`FIG.9 also offers a performance advantage overthat of
`which are coated by reoxidation layer 59. Polysilicon
`FIG. 5. In FIG.5, the shield portions have a vertical
`gate 56 is formed intermediate active region 54 so that
`portion adjacent to the gate. This vertical portion in-
`source region 57 and drain region 58 are uncovered by
`creases the capacitance betweenthe gate andthe shield.
`the formation of gate 56. A channel region 64 is in sub-
`Because each shield portion is connected to a source or
`strate 51, under gate 56, and between source region 57
`drain, the gate-to-shield capacitance addsto the gate-to-
`and drain region 58. Portion 50 shownin FIG.6 could
`drain capacitance and the gate-to-source capacitance.
`be a portion of a well in a CMOSprocess.In addition to
`Shield portions 81 and 82 adjoin insulator layer 59 so
`the conventional features heretofore described for por-
`there is some gate-to-shield capacitance also. Shield
`tion 50, oxide layer 55 is heavily and shallowly im-
`portions 81 and 82, however, do not have the vertical
`planted with silicon to form an implanted region 64 in a
`portion which is present with shield portions 36 and 37
`top portion of oxide layer which overlies region 57 and
`so there is much less gate-to-shield capacitance for the
`transistor of FIG. 9. The transistor of FIG. 9 thus has
`an implanted region 65 in a top portion of oxide layer 55
`which overlies region 58. Incidental to implanting por-
`less gate-to-drain capacitance and less gate-to-source
`tions of oxide layer 55, a top portion of reoxidation
`capacitance.
`Shown in FIG. 10 is a transistor 90 which can be
`layer 59 also has formed therein an implanted region 66.
`The implant is sufficiently low energy and thus suffi-
`madefrom either process described above comprising a
`ciently shallow for there to besilicon near top surfaces
`polysilicon strip 91 for a gate, a drain 92, a source 93,
`of regions 64 and 65. Oxide layer 55 can be madeto the
`and a shield 94. Shield 94 surrounds polysilicon strip 91
`thickness necessary to ensure that the low energy im-
`including end portions 96 and 97 of polysilicon strip 91.
`plant does not penetrate significantly to the source and
`This is a problem becauseit is contemplated that a por-
`drain regions 57 and 58.
`tion of shield 94 which is adjacent to drain 92 will
`After forming regions 64 and 65, which havesilicon
`contact drain 92 and a portion of shield 94 which is
`near the top surfaces thereof, a selective polysilicon
`adjacent to source 93 will contact source 93. This will
`deposition step is performed. The result of this step is
`then have the effect of shorting the source and drain
`shownin FIG. 7. Shown in FIG.7 are polysilicon por-
`together. This is overcome by a mask and subsequent
`tions 67, 68, and 69 which result from the selective
`etch. After a masking layer has been applied and pat-
`polysilicon deposition step. Portion 67 overlies im-
`terned, an aperture 98 is opened to expose end portion
`planted region 64. Portion 68 overlies implanted region
`96 and an aperture 99 is opened to expose end portion 97
`65, and portion 69 overlies implanted portion 66. After
`as shown in FIG. 11. An etch is then performed which
`formation of portions 67-69 by selective deposition,
`removes the portions of shield 94 which are adjacent to
`sidewall spacers 71 and 72 are formed as shownin FIG.
`end portions 96 and 97. The result, shown in FIG.11,
`8. Sidewall spacer 71 is adjacentto left side 61 of gate 56
`avoids the problem of shorting the source and drain via
`and overlies a portion of region 57. Sidewall spacer 72
`the shield. Although the etch is shown as being per-
`is adjacent to right side 63 of gate 56 and overlies a
`formed after the conductive layer which forms the
`portion of region 58. Sidewall spacers 71 and 72 act as
`shield has been etched, this etch can be performed at
`masks for an N+ implant. This N+ implantresults in
`another convenient point after the shield layer has been
`the formation of N+ regions 73 and 74 within regions
`deposited but before it is etched to form the shields.
`57 and 58, respectively. N— regions 75 and 76, which
`While the invention has been described in specific
`are under sidewall spacers 71 and 72, respectively, re-
`embodiments, it will be apparent to those skilled in the
`mnain in regions 57 and 58, respectively. A polysilicon
`art that the disclosed invention may be modified in
`and oxide etch is then performed using sidewall spacers
`numerous ways and may assume many embodiments
`other than those specifically set out and described
`71 and 72 as masks. The etch of polysilicon and oxide
`removes the portions of oxide 55, implanted region 65,
`above. For example, the invention is applicable to P
`and polysilicon portion 68 which are between field
`channel transistors. Implants of impurities to form N-
`oxide 53 and sidewall spacer 72. Similarly, the etch of
`type regions could be substituted with impurities to
`polysilicon and oxide removes the portions of oxide 55,
`form P-type regions. Also the sequence of steps could
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`7
`be changed. One such example is that the implant to
`form regions 73 and 74 shown in FIG. 8 could occur
`after the removal of portions of deposited polysilicon
`portions 67 and 68. Another example is that the shield
`portions may beelectrical contacted with somesignal
`or reference other than sources and drainsof the respec-
`tive transistors. Accordingly, it is intended by the ap-
`pended claims to cover all modifications of the inven-
`tion which fall within the true spirit and scope of the
`invention.
`I claim:
`1. A transistor formed in an active region of a sub-
`strate, comprising:
`a first insulator layer on the active region;
`a gate overlying thefirst insulator layer at an interme-
`diate portion of the active region leaving a first
`portion and a second portion of the active region
`uncovered bythe gate, said gate having a first side
`and a second side, said first and second sides
`aligned with said first and second portions, respec-
`tively, of the active region;
`a second insulator layer coating the first and second
`sides of the gate;
`a lightly-doped source region in the first portion of
`the active region and aligned substantially with the
`first side of the polysilicon gate;
`a lightly-doped drain region in the second portion of
`the active region aligned substantially with the
`second side of the polysilicon gate;
`a channel region in the active region, underthe gate,
`and between the lightly-doped source region and
`the lightly-doped drain region;
`a first heavily-doped region in thefirst portion of the
`active region, offset from the first side of the
`polysilicon gate, and adjoining the lightly-doped
`source region;
`a second heavily-doped region in the second portion .
`of the active region, offset from the secondside of
`the polysilicon gate, and adjoining the lightly-
`doped drain region;
`a first conductive strip adjoining the second insulator
`layer on the first side of the gate, over at least a
`portion of the lightly-doped source region, and
`separated from the lightly-doped source region by
`the first insulator layer; and
`a second conductivestrip adjoining the secondinsula-
`tor layer on the second side of the gate, over at
`least a portion of the lightly-doped drain region,
`and separated from the lightly-doped drain region;
`a first conductive layer over the source region and in
`contact with the first conductive strip and the
`source region; and
`a second conductive layer over the drain region and
`in contact with the first conductive strip and the
`drain region.
`2. The transistor of claim 1 wherein thefirst insulator
`layeris further characterized as being oxide with silicon
`impregnated portions on the surface thereof and in
`contact with the first conductive layer and the second
`conductivelayer.
`3. The transistor of claim 1 wherein the first and
`second conductive strips are polysilicon.
`4. The transistor of claim 1 wherein the first conduc-
`tive strip is characterized has having a vertical portion
`adjoining the second insulator layer and a horizontal
`portion adjoining the first insulator layer.
`5. The transistor of claim 1 wherein the gate has a
`thickness measured along thefirst side thereof and the
`
`10
`
`— 3
`
`25
`
`40
`
`45
`
`60
`
`65
`
`4,951,100
`
`8
`first conductive strip has a horizontal dimension along
`the first insulator layer and a vertical dimension along
`the first side of the gate, said vertical dimension being
`substantially less than the thickness of the gate and
`substantially less than the horizontal dimension.
`6. The transistor of claim 1 wherein the first conduc-
`tive strip is characterized as being a layer parallel with
`the surface of the substrate and of uniform thickness.
`7. A transistor formed in an active region of a sub-
`strate, comprising:
`a first insulator layer on a portionofthe active region;
`a gate overlyingthefirst insulator layer at an interme-
`diate portion of the active region leaving a first
`portion and a second portion of the active region
`uncovered bythe gate, said gate havinga first side
`and a second side, said first and second sides
`aligned with said first and second portions, respec-
`tively, of the active region;
`a second insulator layer coating the first and second
`sides of the gate;
`a lightly-doped source region in the first portion of
`the active region and aligned substantially with the
`first side of the polysilicon gate;
`a lightly-doped drain region in the second portion of
`the active region aligned substantially with the
`second side of the polysilicon gate;
`a channel region in the active region, underthe gate,
`and between the lightly-doped source region and
`the lightly-doped drain region;
`a first heavily-doped region in the first portion of the
`active region, offset from the first side of the
`polysilicon gate, and adjoining the lightly-doped
`source region;
`a second heavily-doped region in the second portion
`of the active region, offset from the second side of
`the polysilicon gate, and adjoining the lightly-
`doped drain region;
`a first conductive strip adjoining the insulator coating
`on the first side of the gate and overat least a por-
`tion of the lightly-doped source;
`a first insulating portion under the first conductive
`strip;
`a second conductive strip adjoining the insulator
`coating on the second side of the gate and overat
`least a portion of the lightly-doped source;
`a secondinsulating portion under the second conduc-
`tive strip;
`an electrical contact between the first conductive
`strip and the first heavily-doped region; and
`an electrical contact between the second conductive
`strip and the second heavily-doped region.
`8. The transistor of claim 7 wherein the first conduc-
`tive strip is formed by thestepsof:
`implanting silicon onto the first insulating portion;
`and
`performing selective deposition of polysilicon to
`form the first conductive strip.
`9. The transistor of claim 7 wherein the first and
`second conductive strips are formed by thestepsof:
`depositing polysilicon over at least the first and sec-
`ond lightly-doped regions,
`the first and second
`heavily-doped regions, and the gate;
`forminga first sidewall spacer ona first portion of the
`polysilicon, said first sidewall spacer overlying the
`first
`lightly-doped region and leaving the first
`heavily-doped region uncovered bythe first side-
`wail spacer, and located besidethefirst side of the
`
`

`

`9
`gate and separated therefrom by the secondinsulat-
`ing layer;
`forming a second sidewall spacer on a second portion
`of the polysilicon, said second sidewall spacer
`overlying the second lightly-doped region and
`leaving the second heavily-doped region uncov-
`ered by thefirst sidewall spacer, and located beside
`the first side of the gate and separated therefrom by
`the second insulating layer; and
`etching the polysilicon over the gate and the first and
`second heavily-doped regions using the first and
`second sidewall spacers as masks.
`10. The transistor of claim 7 wherein thefirst insula-
`tor layer is further characterized as being oxide with
`silicon impregnated portions on the surface thereof and
`in contact with the first conductive layer and the sec-
`ond conductive layer.
`
`10
`11. The transistor of claim 7 wherein the first and
`second conductivestrips are polysilicon.
`12. Thetransistor of claim 7 wherein the first conduc-
`tive strip is characterized has having a vertical portion
`adjoining the second insulator layer and a horizontal
`portion adjoining the first insulator layer.
`13. The transistor of claim 7 wherein the gate has a
`thickness measured along thefirst side thereof and the
`first conductive strip has a horizontal dimension along
`the first insulator layer and a vertical dimension along
`the first side of the gate, said vertical dimension being
`substantially less than the thickness of the gate and
`substantially less than the horizontal dimension.
`14, Thetransistor of claim 7 wherein the first conduc-
`tive strip is characterized as being a conductive layer
`parallel with the surface of the substrate and of uniform
`thickness.
`*
`*
`*
`*
`*
`
`4,951,100
`
`10
`
`20
`
`25
`
`30
`
`35
`
`45
`
`350
`
`35
`
`65
`
`