Docket No.: 079195-0566
`
`PATENT
`
`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`In re Application of
`Masafumi TSUTSUJ,etal.
`Application No.: 12/170,191
`
`Customer Number: 53080
`:
`Confirmation Number: 1644
`:
`| Group Art Unit: 2814
`
`Filed: July 09, 2008
`
`Examiner: Howard Weiss
`
`For:
`
`SEMICONDUCTOR DEVICE INCLUDING MISFET HAVING INTERNAL STRESS
`FILM (as amended)
`
`AMENDMENT
`
`Mail Stop Amendment
`Commissionerfor Patents
`P.O, Box 1450
`Alexandria, VA 22313-1450
`
`Sir:
`
`In responseto the Office Action dated May 10, 2010, wherein a three-month shortened
`
`statutory period for responseis set to expire on August 10, 2010, Applicants respectfully request
`
`reconsideration ofthe above-identified application in view of the following amendments and
`
`remarks.
`
`WDC99 1903276-1.079195.0566
`
`TSMC 1303
`TSMC1303
`
`
`
`PATENT
`
`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`In re Application of
`Masafumi TSUTSUJ,etal.
`Application No.: 12/170,191
`
`Customer Number: 53080
`:
`Confirmation Number: 1644
`:
`| Group Art Unit: 2814
`
`Filed: July 09, 2008
`
`Examiner: Howard Weiss
`
`For:
`
`SEMICONDUCTOR DEVICE INCLUDING MISFET HAVING INTERNAL STRESS
`FILM (as amended)
`
`AMENDMENT
`
`Mail Stop Amendment
`Commissionerfor Patents
`P.O, Box 1450
`Alexandria, VA 22313-1450
`
`Sir:
`
`In responseto the Office Action dated May 10, 2010, wherein a three-month shortened
`
`statutory period for responseis set to expire on August 10, 2010, Applicants respectfully request
`
`reconsideration ofthe above-identified application in view of the following amendments and
`
`remarks.
`
`WDC99 1903276-1.079195.0566
`
`TSMC 1303
`TSMC1303
`
`
`
`Application No.: 12/170,191
`
`This listing ofclaims will replace all prior versions andlistings ofclaims in the application
`
`IN THE CLAIMS:
`
`Listing of Claims
`
`1-14.
`
`(Cancelled)
`
`15.|(Currently Amended) A semiconductor device, comprising a MISFET, wherein
`
`the MISFETincludes:
`
`an active region made of a semiconductorsubstrate;
`
`a gate insulating film formed onthe active region;
`
`a gate electrode formed onthe gate insulating film;
`
`source/drain regions formedin regionsof the active region located onboth sides of the
`
`gate electrode; and
`
`a silicon nitride film formed over from side surfaces of the gate electrode to upper
`
`surfaces of the source/drain regions, wherein:
`
`the silicon nitride film is not formed on an uppersurface of the gate electrode, and
`
`
`
`the gate electrode protrudes upward from a surface level of parts ofthe silicon nitride
`
`film located at both side surfaces of the gate electrode.
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`WDC99 1903276-1.079195.0566
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`Application No.: 12/170,191
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`16.
`
`(Previously presented) The semiconductor device of claim 15, wherein
`
`the silicon nitride film is for generating a stress in a substantially parallel direction to the
`
`gate length direction in a channel regionlocated in the active region under the gate electrode.
`
`17.
`
`(Previously presented) The semiconductor device of claim 16, wherein
`
`the substantially parallel direction of the stress includes a directiontilted by an angle of
`
`less than 10 degree from a direction in which carriers move.
`
`18.
`
`(Previously presented) The semiconductor device of claim 15, wherein
`
`the silicon nitridefilm is directly in contact with the source/drain regions,
`
`19.
`
`(Previously presented) The semiconductor device of claim 15, wherein
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`the silicon nitride film is formed above the source/drain regions with a thin film
`
`interposed therebetween.
`
`20.
`
`(Currently amended) The semiconductor device of claim 15, wherein
`
`the source/drain regions include lightly doped impurity regions formedin regions of the
`
`active region located on both sides of the gate electrode, heavily doped impurity regions formed
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`in regionsofthe active region respectively extending outwardly from the lightly doped impurity
`
`regions to be in contact with the lightly doped impurity regions and having a higher impurity
`
`concentration than that ofthe lightly doped impurity regions, andasilicide layer.
`
`21.
`
`(Currently amended) The semiconductor device of claim 15, further comprising:
`
`WDC99 1903276-1.079195.0566
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`Application No.: 12/170,191
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`a sidewall formed on the side surface of the gate electrode, wherein
`
`the silicon nitride film is formed overthe side surfaces of the gate electrode with the
`
`sidewall interposed betweenthesilicon nitride film and the side surface of the gate electrode.
`
`22.
`
`(Previously presented) The semiconductordevice of claim 15, wherein
`
`a principal surface of the semiconductor substrate is substantially a {100} plane, and
`
`the gate length direction ofthe gate electrode is substantially a <011> direction.
`
`a,
`
`(Previously presented) The semiconductor device of claim 15, further
`
`comprising:
`
`an interlevel insulating film formed onthesilicon nitride film; and
`
`a contact plug provided so as to pass throughtheinterlevel insulating film andthesilicon
`
`nitride film and to be connected to the source/drain regions.
`
`24.
`
`(Currently amended) The semiconductor device of claim 15, wherein:
`
`the active region is divided by an isolation region formed in the semiconductor substrate,
`
`and
`
`the silicon nitride film is formed to extend overthe isolation region as well as the
`
`source/drain regions.
`
`a5,
`
`(Previously presented) The semiconductor device of claim 15, wherein
`
`the gate insulating film is a silicon oxide film.
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`WDC99 1903276-1.079195.0566
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`Application No.: 12/170,191
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`26.
`
`(Previously presented) The semiconductor device of claim 15, wherein
`
`the gate insulatingfilm is a silicon oxynitride film.
`
`27.
`
`(Previously presented) The semiconductor device of claim 15, wherein
`
`the gate electrode hasa polysilicon film.
`
`28.
`
`(Previously presented) The semiconductor device of claim 15, wherein
`
`the gate electrode has a metalfilm.
`
`29.
`
`(Previously presented) The semiconductor device of claim 15, wherein
`
`the silicon nitride film is provided so as to coverat least part of at least one of the
`
`source/drain regions.
`
`30.
`
`(Previously presented) The semiconductor device of claim 15, wherein
`
`the silicon nitride film covers at least respective parts of the source/drain regions.
`
`31.
`
`(Previously presented) The semiconductor device of claim 15, wherein
`
`the silicon nitride film covers at least respective parts of both side surfaces of the gate
`
`electrode.
`
`32.
`
`(Previously presented) The semiconductor device of claim 15, wherein
`
`the MISFETis an nMISFET and
`
`the source/drain regions are n-type source/drain regions.
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`WDC99 1903276-1.079195.0566
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`Application No.: 12/170,191
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`33.
`
`(Previously presented) The semiconductor device of claim 32, wherein
`
`the silicon nitride film is for generating a tensile stress in a substantially parallel direction
`
`to the gate length direction in a channelregion locatedin the active region underthe gate
`
`electrode.
`
`34.
`
`(Previously presented) The semiconductor device of claim 32, wherein
`
`the n-type source/drain regions include an n-type lightly doped impurity region, an n-type
`
`heavily doped impurity region andasilicide layer.
`
`35.
`
`|
`
`(Previously presented) The semiconductor device of claim 15, whereinthe silicon
`
`nitride film directly contacts with the side surfaces of the gate electrode.
`
`36.
`
`(Previously presented) The semiconductor device of claim 24, wherein a lower
`
`surface of the isolation region is located in the semiconductor substrate and is in direct contact
`
`with the semiconductor substrate.
`
`oo:
`
`(New) The semiconductor device of claim 15, wherein
`
`an uppersurfaceofthe gate electrode is higher than an uppersurfaceofthe parts of the
`
`silicon nitride film located at both side surfaces of the gate electrode.
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`WDC99 1903276-1.079195,0566
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`Application No.: 12/170,191
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`38.
`
`(New) The semiconductor device of claim 15, wherein
`
`the gate insulating film is formed only under a lower surface of the gate electrode.
`
`39.|(New) The semiconductor device of claim 15, further comprising:
`
`a sidewall formed onthe side surface of the gate electrode;
`
`an interlevel insulating film formed onthe silicon nitride film;
`
`an isolation region formed in the semiconductorsubstrate to divide the active region; and
`
`a contactplug providedsoas to pass through theinterlevel insulating film and the silicon
`
`nitride film and to be connected to the source/drain regions, wherein
`
`the silicon nitride film is formed overthe side surfaces of the gate electrode with the
`
`sidewall interposed betweenthesilicon nitride film andthe side surface of the gate electrode and
`
`to extend overthe isolation region as well as the source/drain regions.
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`WDC99 1903276-1.079195.0566
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`Application No.: 12/170,191
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`Status of Claims
`
`REMARKS
`
`Claims 15-39 are pending, of which claim 15 is independent.
`
`Claims 15, 20, 21 and 24 have been amendedtocorrectinformalities in the claim
`
`language and to moreclearly define the claimed subject matter. Claims 37-39 have been added.
`
`Support for the amendmentand the newclaimsis foundat, for example, FIGS. 1 and 4A. Care
`
`has been taken to avoid introducing new matter.
`
`Rejection under 35 U.S.C. § 103
`
`Claims 15-21, 23-34 and 36 were rejected under 35 U.S.C. § 103(a) as being
`
`unpatentable over Xianget al. (US 6,437,404) and Matsudaetal. (US 6,870,230). Claims 22
`
`and 35 were rejected under 35 U.S.C. § 103(a) as being unpatentable over Xianget al. and
`
`Matsudaetal., and further in view of Tatsuta (US 5,023,676). These rejections are traversed for
`
`at least the following reasons.
`
`Applicants respectfully submit that, at a minimum,noneofthe cited references discloses
`
`or suggeststhat “the gate electrode protrudes upwardfrom a surface level ofparts ofthe silicon
`
`nitridefilm located at both side surfaces ofthe gate electrode,” as recited by amended claim 15.
`
`In the present subject matter, as shown in, for example, FIGS. 1 and 4A,the gate electrode 6a, 6b
`
`protrudes upward from a surfacelevel of parts ofthe silicon nitride film 8a, 8b located at both
`
`side surfaces of the gate electrode 6a, 6b. In other words, a height of the gate electrode from the
`
`surface of the substrate is higher than a height ofthesilicon nitride film disposed at the sides of
`
`the gate electrode.
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`WDC99 1903276-1.079195.0566
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`Application No.: 12/170,191
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`In contrast, as shown in FIG. 1 of Xiang,it is clear that the upper surface ofthe gate
`
`electrode 56 is at the samelevel as that of an upper end surface ofthe etch stop layer 80, 82 (i.e.,
`
`the allegedsilicon nitride film) located at both side surfaces ofthe gate electrode 56. As such, in
`
`Xiang, the gate electrode 56 does not protrude from a surfacelevel ofthe parts ofthe silicon
`
`nitride film 80, 82 located at the both side surfaces of the gate electrode 56.
`
`In Matsuda, as shown in FIG, 9A,it is also clear that the upper surface of the gate
`
`electrode 6a is at the samelevelas that of an upper end surface of the parts of the protective
`
`insulating film 9a(i.e., the alleged silicon nitride film) located at both side surfaces ofthe gate
`
`electrode 6a. As such,it is clear that Matsudaalso fails to disclose or suggest that the gate
`
`electrode protrudes upward from a surface level ofparts ofthe silicon nitride film located at both
`
`side surfaces of the gate electrode.
`
`Accordingly,it is clear that the combination of Xiang and Matsudastill fails to disclose
`
`the above identified features of amended claim 15. Further, it is also clear that the remaining
`
`cited reference does not cure the deficiencies of Xiang and Matsuda, and it would not have been
`
`obviousto add these features to any combination ofthe cited references. Thus, Applicants
`
`submit that claim 15 and all claims dependentthereon are patentable over the cited references.
`
`New claims
`
`Since new claims 37-39 depend upon claim 15, claims 37-39 are patentable for at least
`
`the same reasonsas claim 15.
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`WDC99 1903276-1,079195.0566
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`Application No.: 12/170,191
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`CONCLUSION
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`Having fully respondedto all matters raised in the Office Action, Applicants submit that
`
`all claims are in condition for allowance, an indication for which is respectfully solicited. If
`
`there are any outstanding issues that might be resolved by an interview or an Examiner’s
`
`amendment, the Examineris requested to call Applicants’ attorney at the telephone number
`
`shown below.
`
`To the extent necessary,a petition for an extension of time under 37 C.F.R. § 1.136 is
`
`hereby made. Please charge any shortage in fees due in connection with thefiling of this paper,
`
`including extension of time fees, to Deposit Account 500417 and please credit any excess fees to
`
`such deposit account.
`
`Respectfully submitted,
`
`McDERMOTT WILL & EMERY LLP
`
`Takashi Saito
`Limited Recognition No. L0123
`
`Please recognize our Customer No. 53080
`as our correspondenceaddress.
`
`600 13"Street, N.W.
`Washington, DC 20005-3096
`Phone: 202.756.8000 TS:MaM
`Facsimile: 202.756.8087
`Date: August 6, 2010
`
`WDC99 1903276-1.079195.0566
`
`-10-
`
`
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