`a2) Patent Application Publication (0) Pub. No.: US 2004/0164359 Al
`
` Iwataetal. (43) Pub. Date: Aug.26, 2004
`
`
`US 20040164359A1
`
`(54) SEMICONDUCTOR STORAGE DEVICE,ITS
`MANUFACTURING METHOD AND
`OPERATING METHOD, AND PORTABLE
`ELECTRONIC APPARATUS
`
`Publication Classification
`
`Int. C17 cecceseseees HOIL 21/8238; HO1L 29/76
`(51)
`(52) US. Che ce ececcessscsstessensenteeneeenes 257/379; 438/200
`
`(76)
`
`Inventors: Hiroshi Iwata, Nara (JP); Akihide
`Shibata, Nara (JP)
`
`(57)
`
`ABSTRACT
`
`Correspondence Address:
`BIRCH STEWART KOLASCH & BIRCH
`PO BOX747
`FALLS CHURCH, VA 22040-0747 (US)
`
`.
`(21) Appl. No.:
`(22) PCT Filed:
`
`10/480,893
`Nov. 18, 2002
`
`(86) PCT No::
`
`PCT/JP02/12028
`
`(30)
`
`Foreign Application Priority Data
`
`Nov. 21, 2001
`
`(IP) ..eeeceessesssssecssneeeersees 2001-356549
`
`invention provides a semiconductor storage
`The present
`device having: a first conductivity type region formed in a
`semiconductor layer; a second conductivity type region
`formed in the semiconductor layer in contact with the first
`conductivity type region; a memory functional element
`disposed on the semiconductor layer across the boundary of
`the first and second conductivity type regions; and an
`electrode provided in contact with the memory functional
`element and on the first conductivity type region via an
`insulation film, and a portable electronic apparatus compris-
`ing the semiconductor storage device. The present invention
`can fully cope with scale-down and high-integration by
`constituting a selectable memory cell substantially of one
`device.
`
`609a 607 606 605 610
`
`
`609b
`
`
`—LOS Sys
`PEOLTEIID}LEEKA AEA, LkLA
`
`612
`RaEE
`
`SA
`610
`
`
`AS
`
`
`Key
`
`
`
`Soa
`608
`y
`
`Ks
`
`
`
`KS
`
`AI
`603
`
`
`
`re72
`PLLLLLLLLLL
`LeLLPLLLLL
`
`
`
`
`KLkL]
`
`Ao
`
`e
`EB
`post
`
`
`
`Yy
`Vs
`
`IP Bridge Exhibit 2218
`IP Bridge Exhibit 2218
`TSMC v. Godo Kaisha IP Bridge 1
`TSMCv. Godo Kaisha IP Bridge 1
`IPR2017-01843
`IPR2017-01843
`
`
`
`Patent Application Publication Aug. 26, 2004 Sheet 1 of 36
`
`US 2004/0164359 Al
`
`FIG.1 (a)
`
`609a
`
`607 606 605 610
`
`609b
`622
`
`FIG. 1(b)
`
`
`
`Patent Application Publication Aug. 26, 2004 Sheet 2 of 36
`
`US 2004/0164359 Al
`
`FIG. 2
`
`
`
`
`
`Patent Application Publication Aug. 26, 2004 Sheet 3 of 36
`
`US 2004/0164359 Al
`
`FIG. 3
`
`805
`
`807
`
`805
`
`4
`
` SS
`
`
`
`
`
`Patent Application Publication Aug. 26, 2004 Sheet 4 of 36
`
`US 2004/0164359 Al
`
`FIG. 4
`
`
`STINTKS
`
`
`
`
`
`902 901
`
`902
`
`900
`
`
`
`Patent Application Publication Aug. 26, 2004 Sheet 5 of 36
`
`US 2004/0164359 Al
`
`FIG. 5(a)
`
`Tx:
`ae
`
`
`
`
`
`FIG. 5(b)
`
`.
`
`3
`
`FIG. 5(c)
`
`3
`
`
`
`Patent Application Publication Aug. 26, 2004 Sheet 6 of 36
`
`US 2004/0164359 Al
`
`FIG. 6(a)
`
`CGL
`
`
`
`STr.
`
`MTr.
`
`FIG. 6(b)
`
`EFFECT OF VARIABLE RESISTANCE
`
`
`
`Patent Application Publication Aug. 26, 2004 Sheet 7 of 36
`
`US 2004/0164359 Al
`
`FIG. 7(a)
`
`FIG. 7(d)
`
`FIG. 7(e)
`
`FIG. 7(b)
`
`
`
`
`Patent Application Publication Aug. 26, 2004 Sheet 8 of 36
`
`US 2004/0164359 Al
`
`FIG. 8
`
`
`
`
`
`Patent Application Publication Aug. 26, 2004 Sheet 9 of 36
`
`US 2004/0164359 Al
`
`FIG. 9 (a)
`
`+2(V]
`| +20V]
`
`FIG. 9(b)
`
`
`
`Patent Application Publication Aug. 26, 2004 Sheet 10 of 36
`
`US 2004/0164359 Al
`
`FIG. 10
`
`+1[V]
`
`
`
`Patent Application Publication Aug. 26,2004 Sheet 11 of 36
`
`US 2004/0164359 Al
`
`FIG. 11
`
`-4LV]
`
`
`
`Patent Application Publication Aug. 26, 2004 Sheet 12 of 36
`
`US 2004/0164359 Al
`
`FIG. 12
`
`
`
`
`
`Patent Application Publication Aug. 26, 2004 Sheet 13 of 36
`
`US 2004/0164359 Al
`
`FIG. 13
`
`
`
`
`
`Patent Application Publication Aug. 26, 2004 Sheet 14 of 36
`
`US 2004/0164359 Al
`
`FIG. 14
`
`
`
`
`
`Patent Application Publication Aug. 26, 2004 Sheet 15 of 36
`
`US 2004/0164359 Al
`
`FIG. 15
`
`
`
`
`
`Patent Application Publication Aug. 26, 2004 Sheet 16 of 36
`
`US 2004/0164359 Al
`
`FIG. 16 (a)
`
`FIG. 16(b)
`
`7
`17
`FIG. 16(c)
`
`
`
`Patent Application Publication Aug. 26, 2004 Sheet 17 of 36
`
`US 2004/0164359 Al
`
`FIG. 1%
`
` a—
`
`
`
`
`
`Patent Application Publication Aug. 26, 2004 Sheet 18 of 36
`
`US 2004/0164359 Al
`
`FIG. 18 (a)
`
`14.617
`
`LZ
`
`51
`
`a1
`
`FIG. 18(b)
`
`
`
`
`FIG. 18(c)
`
`
`
`Patent Application Publication Aug. 26, 2004 Sheet 19 of 36
`
`US 2004/0164359 Al
`
`FIG. 19
`
`
`
`
`
`Patent Application Publication Aug. 26, 2004 Sheet 20 of 36
`
`US 2004/0164359 Al
`
`FIG. 20
`
`
`
`
`
`Patent Application Publication Aug. 26, 2004 Sheet 21 of 36
`
`US 2004/0164359 Al
`
`FIG. 21 (a)
`
`FIG. 21(c) . 30°
`
`31
`
`HW
`
`31
`
`
`
`Patent Application Publication Aug. 26, 2004 Sheet 22 of 36
`
`US 2004/0164359 Al
`
`FIG. 22 (d)
`FIG. 22(e)
`
`40 At
`
`31
`
`17
`
`31
`
`
`
`Patent Application Publication Aug. 26, 2004
`
`Sheet 23 of 36
`
`US 2004/0164359 Al
`
`FIG. 23(a)
`
`1910
`
`Ta|
`flttsmsLLLLAsESS
`~KAKA
`—MD™jO[D—iwsMM,
`SOK
`CDS6K{[LFS
`
`nnPRSPIMALAALELD
`
`AERISeevob.ecdeececee
`ezzeeiorseekc
`Saar4RS|ed&
`
`MHRENVdtf)SNodrerloeaSkee awy
`
`
`NextarbooedSYCLA
`ekedLLLALLLALALA
`ViLe(LAL)YSFLLa
`pLLehLLALLL.RS
`
`oSKKCECEELS
`a
`
`
`
`1907.
`
`1903
`
`‘1904
`
`FIG. 23(b)
`
`1906
`
`1903
`
`BSSiASSy)
`
`1901
`
`1902
`
`1905
`
`
`
`
`
`
`
`
`Patent Application Publication Aug. 26, 2004 Sheet 24 of 36
`
`US 2004/0164359 Al
`
`FIG. 24
`
`
`
`
`
`Patent Application Publication Aug. 26, 2004 Sheet 25 of 36
`
`US 2004/0164359 Al
`
`FIG. 25
`
`7114Ws 1062
`
`142 181
`
`147 113°
`
`111
`
`
`
`Patent Application Publication Aug. 26, 2004 Sheet 26 of 36
`
`US 2004/0164359 Al
`
`FIG. 26
`
`117a 1142
`
`
`
`Patent Application Publication Aug. 26, 2004 Sheet 27 of 36
`
`US 2004/0164359 Al
`
`FIG. 27
`
` W2=100nm —
`
`:
`
`:
`
`120
`
`140
`
`10°
`20
`
`40
`
`:
`60
`
`100
`80
`W 1[nm]
`
`
`
`Patent Application Publication Aug. 26, 2004 Sheet 28 of 36
`
`US 2004/0164359 Al
`
`FIG. 28
`
`
`
`
`
`Patent Application Publication Aug. 26, 2004 Sheet 29 of 36
`
`US 2004/0164359 Al
`
`FIG. 29
`
`117 114!
`
`
`
`Patent Application Publication Aug. 26, 2004 Sheet 30 of 36
`
`US 2004/0164359 Al
`
`FIG. 30
`
`
`
`
`
`Patent Application Publication Aug. 26, 2004 Sheet 31 of 36
`
`US 2004/0164359 Al
`
`FIG. 31
`
`
`
`
`
`Patent Application Publication Aug. 26, 2004 Sheet 32 of 36
`
`US 2004/0164359 Al
`
`FIG. 32
`
`
`
`
`
`Patent Application Publication Aug. 26, 2004 Sheet 33 of 36
`
`US 2004/0164359 Al
`
`FIG. 33
`
`
`
`
`
`Patent Application Publication Aug. 26, 2004 Sheet 34 of 36
`
`US 2004/0164359 Al
`
`FIG. 34
`
`
`
`
`
`Patent Application Publication Aug. 26, 2004 Sheet 35 of 36
`
`US 2004/0164359 Al
`
`FIG. 35
`
`215
`
`21/ 212
`
`213
`
`214
`
`216
`
`211
`
`
`
`970
`
`916
`
`919
`
`Patent Application Publication Aug. 26, 2004 Sheet 36 of 36
`
`US 2004/0164359 Al
`
`FIG. 36 (a)
`
`920
`
`
`FIG. 36(b)
`
`
`
`US 2004/0164359 Al
`
`Aug. 26, 2004
`
`SEMICONDUCTOR STORAGE DEVICE, ITS
`MANUFACTURING METHOD AND OPERATING
`METHOD, AND PORTABLE ELECTRONIC
`APPARATUS
`
`TECHNICAL FIELD
`
`[0001] The present invention relates to a semiconductor
`storage device,
`its manufacturing method and operating
`method, and a portable electronic apparatus. More particu-
`larly, the present invention relates to a semiconductorstor-
`age device which is a device having the function of con-
`verting a change in a charge amountinto a current amount,
`its manufacturing method and operating method, and a
`portable electronic apparatus using such a semiconductor
`storage device.
`
`BACKGROUND ART
`
`[0002] Conventionally, as a nonvolatile memory using a
`resistance value of a variable resistor as storage information,
`rewriting the storage information by changing the resistance
`value, and reading out the storage information by detecting
`the resistance value, there is an MRAM (Magnetic Random
`Access Memory) (M. Durlam et al., Nonvolatile Ram Based
`on Magnetic Tunnel Junction Elements, International Solid-
`State Circuits Conference Digest of Technical Papers, pp.
`130-131, February 2000).
`
`[0003] FIG. 36(a) is a schematic sectional view of one
`memorycell constituting such an MRAM and FIG.36(d)is
`an equivalent circuit diagram.
`
`[0004] The memorycell is constituted in such a manner
`that a variable resistor 911 and a selection transistor 912 are
`connected to each other via a metal wire 917 and a contact
`plug 918. In addition, a bit line 914 is connected to one end
`of the variable resistor 911.
`
`[0005] The variable resistor 911 is constituted by MTJ
`(Magnetic Tunnel Junction) and is sandwiched by a rewrite
`word line 913 extended in a direction orthogonal to the bit
`line 914 andthe bit line at the crossing pointof the lines.
`
`Theselection transistor 912 is constituted by a pair
`[0006]
`of diffusion regions 920 formed on a semiconductor sub-
`strate 919 and a gate electrode. One of the diffusion regions
`920 is connected to the variable resistor 911 via the metal
`wire 917 and the contact plug 918, and the other diffusion
`region is connected to a source line 915. The gate electrode
`constitutes a selection word line 916.
`
`[0007] A rewriting operation of the MRAM is performed
`in such a mannerthat a composite magnetic field generated
`by current flowing in the bit line 914 and the rewrite word
`line 913 changesthe resistance value of the variable resistor
`911. On the other hand, a reading operation is performed in
`such a mannerthat the selection transistor 912 is turned on
`and a current value flowing in the variable resistor 911,that
`is,
`the resistance value of the variable resistor 911 is
`detected.
`
`[0008] As described above, a memorycell of the MRAM
`is constituted by two devices: the variable resistor 911 which
`is a device having three terminals; and the selection tran-
`sistor 912 which is a device having three terminals. Conse-
`quently, it is limited and difficult to realize further scale-
`down and increase in capacity of a memory.
`
`DISCLOSURE OF THE INVENTION
`
`[0009] An object of the present invention is to provide a
`semiconductor storage device capable of fully coping with
`scale-downand high-integration by constituting a selectable
`memory cell substantially of one device, its manufacturing
`method and operating method, and a portable electronic
`apparatus having such a semiconductor storage device.
`
`[0010] According to the present invention, there is pro-
`vided a semiconductor storage device comprising: a first
`conductivity type region formed in a semiconductorlayer; a
`second conductivity type region formed in contact with the
`first conductivity type region in the semiconductorlayer; a
`memory functional clement disposed on the semiconductor
`layer across the boundary of the first and second conduc-
`tivity type regions; and an electrode provided in contact with
`the memory functional element and onthe first conductivity
`type region via an insulation film.
`
`{0011] There is also provided a semiconductor storage
`device comprising: a first conductivity type region formedin
`a semiconductorlayer; two second conductivity type regions
`formed on both sidesofthe first conductivity type region in
`the semiconductor layer; two memory functional elements
`each disposed on the semiconductor layer across the bound-
`aries of the first and second conductivity type regions; and
`electrodes provided in contact with each of the memory
`functional elements and onthefirst conductivity type region
`via an insulation film.
`
`{0012] Further, there is provided a semiconductor storage
`device comprising: a channel region formed in a, semicon-
`ductor layer; variable resistance regions provided on both
`sides of the channel region; two diffusion regions provided
`on both sides of the channel region via the variable resis-
`tance regions; a gate electrode provided on the channel
`region via a gate insulation film; and two memoryfunctional
`elements disposed on both sides of the gate electrode each
`across the variable resistance regions and a part of the
`diffusion regions.
`
`[0013] There is also provided a semiconductor storage
`device comprising: a gate electrode formed on a semicon-
`ductor layer via a gate insulation film; a channel region
`provided under the gate electrode; diffusion regions dis-
`posed on both sides of the channel region and having a
`conductivity type different from the conductivity type of the
`channel region; and memoryfunctional elements for holding
`charges, formed on both sides of the gate electrode so as to
`overlap with the diffusion regions.
`
`{0014] Further, there is provided a semiconductor storage
`device comprising at least one memorycell including: a
`semiconductor layer disposed on a semiconductorsubstrate,
`a well region provided in the semiconductor substrate, or an
`insulator; a single gate electrode formed on the semicon-
`ductor substrate or the semiconductor layer via a gate
`insulation film; a channel region disposed under the gate
`electrode; two diffusion regions formed on bothsides of the
`channel
`region; and two memory functional elements
`formed on both sides of the gate electrode so as to overlap
`with the diffusion regions.
`
`[0015] There is also provided a semiconductor storage
`device comprising at least one memorycell including: a
`semiconductor layer disposed on a semiconductor substrate,
`a well region provided in the semiconductor substrate, or an
`
`
`
`US 2004/0164359 Al
`
`Aug. 26, 2004
`
`insulator; a gate insulation film formed on the semiconduc-
`tor layer which is disposed on the semiconductor substrate,
`the well region provided in the semiconductor substrate, or
`the insulator; a single gate electrode formed on the gate
`insulation film; a channel region disposed immediately
`below the gate electrode; two diffusion regions disposed on
`both sides of the channel region; and sidewall insulation
`films formed on both sides of the gate electrode so as to
`overlap with the diffusion regions, wherein the sidewall
`insulation films have the function of holding charges.
`
`[0016] Further, there is provided a semiconductor storage
`device comprising: a semiconductor substrate; a first con-
`ductivity type well region formed in the semiconductor
`substrate; a gate insulation film formed on the well region;
`a plurality of word lines formed on the gate insulation film;
`a plurality of second conductivity type diffusion regions
`formed on both sides of each of the word lines; charge
`holding films having the function of accumulating or trap-
`ping charges, formed on both sides of the plurality of word
`lines on the word lines, the well region, and the diffusion
`regions directly or via an insulation film on at least a part of
`the diffusion region or so as to extend from a part of the well
`region to a part of the diffusion region; and a plurality of bit
`lines connected to the diffusion regions and extending in a
`direction which crosses the word lines.
`
`[0017] There is also provided a semiconductor storage
`device comprising: a gate electrode formed on a semicon-
`ductor layer via a gate insulation film; memory functional
`elements formed on both sides of the gate electrode and
`having the function of holding charges;
`two diffusion
`regions each disposed on the side opposite to the gate
`electrode of the memory functional elements; and a channel
`region disposed under
`the gate electrode, wherein the
`memory functional element
`includes a film having the
`function of holding charges, and at least a part of the film
`having the function of holding charges is formed so as to
`overlap with a part of the diffusion region.
`
`[0018] Further, there is provided a semiconductor storage
`device comprising: a first conductivity type semiconductor
`layer; a gate insulation film formed onthe first conductivity
`type semiconductor layer; a gate electrode formed on the
`gate insulation film; memory functional elements formed on
`both sides of the gate electrode and having the function of
`holding charges; and two second conductivity type diffusion
`regions each disposed on the side opposite to the gate
`electrode of the memory functional elements, wherein the
`memory functional element
`includes a film having the
`function of holding charges,at least a part ofthe film having
`the function of holding charges overlaps with at least a part
`of the diffusion region, and the first conductivity type
`semiconductor layer has a first conductivity type high-
`concentration region having a concentration higher than that
`of a portion in the vicinity of the surface of the first
`conductivity type semiconductor layer under the gate elec-
`trode, under the memory functional element and in the
`vicinity of the diffusion region.
`
`[0019] There is also provided a semiconductor storage
`device comprising: a gate insulation film; a gate electrode
`formed on the gate insulation film; memory functional
`elements formed on both sides of the gate electrode and
`having the function of holding charges;
`two diffusion
`regions each disposed on the side opposite to the gate
`
`electrode of the memoryfunctional elements; and a channel
`region disposed under the gate electrode, wherein when a
`length of the gate electrode in a channel length direction is
`A, a channel length between the diffusion regions is B, and
`a distance from an end of one of the memory functional
`elements to an end of the other memory functional element
`is C, a relation of A<B<C is satisfied.
`
`[0020] Further, there is provided a semiconductor storage
`device comprising: a gate insulation film; a gate electrode
`formed on the gate insulation film; memory functional
`elements formed on both sides of the gate electrode and
`having the function of holding charges; two N-type diffusion
`regions each disposed on the side opposite to the gate
`electrode of the memory functional element; and a channel
`region disposed underthe gate electrode, wherein magnitude
`of a voltage applied to one of the diffusion regions and
`magnitude of a voltage applied to the other diffusion region
`are reversed betweenthe time of changing a storage state by
`injecting electrons into the memory functional element and
`the time of reading out the storage state of the memory
`functional element.
`
`[0021] There is also provided a semiconductor storage
`device comprising: a gate insulation film; a gate electrode
`formed on the gate insulation film; memory functional
`elements formed on both sides of the gate electrode and
`having the function of holding charges; two P-type diffusion
`regions each disposed on the side opposite to the gate
`electrode of the memory functional element; and a channel
`region disposed underthe gate electrode, wherein magnitude
`of a voltage applied to one of the source and drain regions
`and magnitude of a voltage applied to the other region are
`reversed between the time of changing a storage state by
`injecting holes into the memory functional element and the
`time of reading out the storage state of the memory func-
`tional element.
`
`[0022] Further, there is provided a manufacturing method
`of a semiconductor storage device, comprising the steps of:
`forming a gate insulation film and a gate electrode on a
`semiconductor substrate; depositing an insulation film hav-
`ing the function of accumulating or trapping charges on the
`whole surface of the obtained substrate; and forming a
`sidewall insulation film on a sidewall of the gate electrode
`by selectively etching the insulation film.
`[0023] According to another aspect, there is provided an
`operating method of a semiconductor storage device com-
`prising: a single gate electrode formed on a P-type semi-
`conductor layer disposed on a P-type semiconductor sub-
`strate, a P-type well region formed in the semiconductor
`substrate, or an insulator; a channel region disposed under
`the single gate electrode; two N-type source/drain regions
`positioned on both sides of the channel region; and a
`memory functional element existing in the vicinity of the
`source/drain regions, wherein one of the source/drain
`regionsis set to a reference voltage, the gate electrode is set
`to a voltage lower than the reference voltage, the semicon-
`ductor layer formed on the semiconductorsubstrate, the well
`region formed in the semiconductor substrate, or the insu-
`lator is set to a voltage higher than the reference voltage, and
`the other source/drain region is set to a voltage higher than
`the semiconductor layer formed on the semiconductor sub-
`strate, the well region formed in the semiconductor sub-
`strate, or the insulator,
`thereby injecting holes into the
`memory functional element.
`
`
`
`US 2004/0164359 Al
`
`Aug. 26, 2004
`
`[0024] Further, there is provided an operating method of a
`semiconductor storage device comprising: a single gate
`electrode formed on an N-type semiconductor layer dis-
`posed on an N-type semiconductorsubstrate, an N-type well
`region formed in the semiconductor substrate, or an insula-
`tor; a channel region under the single gate electrode; two
`P-type source/drain regions positioned on both sides of the
`channel region; and a memory functional element existing in
`the vicinity of the source/drain regions, wherein one of the
`source/drain regions is set to a reference voltage, the gate
`electrode is set
`to a voltage higher than the reference
`voltage, the semiconductor layer disposed on the semicon-
`ductor substrate, the well region formed in the semiconduc-
`tor substrate, or the insulator is set to a voltage lower than
`the reference voltage, and the other source/drain regionis set
`to a voltage lower than the semiconductor layer disposed on
`the semiconductor substrate, the well region formed in the
`semiconductor substrate, or the insulator, thereby injecting
`electrons into the memory functional element.
`
`[0025] There is also provided a portable electronic appa-
`ratus comprising the semiconductor storage device.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG.1 is a schematic sectional view and an equiva-
`[0026]
`lent circuit of a main part of a semiconductor storage device
`(Embodiment 1) of the present invention.
`
`FIG.2 is a schematic sectional view of a main part
`[0027]
`showing a modification of the semiconductor storage device
`(Embodiment 1) of the present invention.
`
`FIG.3 is a schematic sectional view of a main part
`[0028]
`of a semiconductor storage device (Embodiment 2) of the
`present invention.
`
`[0029] FIG. 4 is a schematic sectional view of a main part
`of a semiconductor storage device (Embodiment 3) of the
`present invention.
`
`FIG.5 is a schematic sectional view of a main part
`[0030]
`for describing the flow of a manufacturing method of a
`semiconductor storage device (Embodiment 4) of
`the
`present invention.
`
`[0031] FIG. 6 is a circuit diagram for describing the
`function of a charge holding film of the semiconductor
`storage device (Embodiment 4) of the present invention.
`
`FIG.7 is a schematic sectional view of a main part
`[0032]
`showing a semiconductor storage device (Embodiment 5) of
`the present invention.
`
`FIG.8 is a schematic sectional view of a main part
`[0033]
`showing a semiconductor storage device (Embodiment 6) of
`the present invention.
`
`FIG.9 is a schematic sectional view of a main part
`[0034]
`for describing a writing operation of the semiconductor
`storage device (Embodiment 6) of the present invention.
`
`[0037] FIG. 12 is a schematic sectional view of a main
`part showing a semiconductor storage device (Embodiment
`7) of the present invention.
`
`[0038] FIG. 13 is a schematic sectional view of a main
`part showing a semiconductor storage device (Embodiment
`8) of the present invention.
`
`[0039] FIG. 14 is a schematic sectional view of a main
`part showing a semiconductor storage device (Embodiment
`9) of the present invention.
`
`[0040] FIG. 15 is a schematic sectional view of a main
`part showing a semiconductor storage device (Embodiment
`10) of the present invention.
`
`[0041] FIG. 16 is a schematic sectional view of a main
`part for describing the flow of a manufacturing method of
`the semiconductor storage device (Embodiment 10) of the
`present invention.
`
`[0042] FIG. 17 is a schematic sectional view of a main
`part showing a semiconductor storage device (Embodiment
`11) of the present invention.
`
`[0043] FIG. 18 is a schematic sectional view of a main
`part for describing the flow of a manufacturing method of
`the semiconductor storage device (Embodiment 11) of the
`present invention.
`
`[0044] FIG. 19 is a schematic sectional view of a main
`part showing a semiconductor storage device (Embodiment
`12) of the present invention.
`
`[0045] FIG. 20 is a schematic sectional view of a main
`part showing a semiconductor storage device (Embodiment
`13) of the present invention.
`
`[0046] FIG.21 and FIG.22 are schematic sectional views
`of a main part for describing the flow of a manufacturing
`method of the semiconductor storage device (Embodiment
`13) of the present invention.
`
`[0047] FIG. 23 is a schematic sectional view of a main
`part of a semiconductor storage device (Embodiment 14) of
`the present invention.
`
`[0048] FIG.24 is a schematic sectional view of a main
`part of a semiconductor storage device (Embodiment 15) of
`the present invention.
`
`[0049] FIGS. 25 and 26 are enlarged schematic sectional
`views of the main part of FIG. 24.
`
`[0050] FIG.27 is a graph showing electric characteristics
`of the semiconductor storage device (Embodiment 15)ofthe
`present invention.
`
`{0051] FIG. 28 is a schematic sectional view of a main
`part of a modification of the semiconductor storage device
`(Embodiment 15) of the present invention.
`
`[0052] FIG. 29 is a schematic sectional view of a main
`part of a semiconductor storage device (Embodiment 16) of
`the present invention.
`
`[0035] FIG. 10 is a schematic sectional view of a main
`part for describing a reading operation of the semiconductor
`storage device (Embodiment 6) of the present invention.
`
`[0053] FIG. 30 is a schematic sectional view of a main
`part of a semiconductor storage device (Embodiment 17) of
`the present invention.
`
`[0036] FIG. 11 is a schematic sectional view of a main
`part for describing an erasing operation of the semiconduc-
`tor storage device (Embodiment 6) of the present invention.
`
`[0054] FIG. 31 is a schematic sectional view of a main
`part of a semiconductor storage device (Embodiment18) of
`the present invention.
`
`
`
`US 2004/0164359 Al
`
`Aug. 26, 2004
`
`[0055] FIG. 32 is a schematic sectional view of a main
`part of a semiconductor storage device (Embodiment19) of
`the present invention.
`
`[0056] FIG. 33 is a schematic sectional view of a main
`part of a semiconductor storage device (Embodiment20) of
`the present invention.
`
`[0057] FIG. 34 is a schematic sectional view of a main
`part of a semiconductor storage device (Embodiment21) of
`the present invention.
`
`FIG.35 is a schematic sectional view of a portable
`[0058]
`electronic apparatus in which the semiconductor storage
`device of the present invention is assembled.
`
`[0059] FIG. 36 is a schematic sectional view of a main
`part showing a conventional semiconductor storage device.
`
`BEST MODE FOR CARRYING OUT THE
`INVENTION
`
`[0060] Hereinafter, description will be given of a semi-
`conductor storage device, its manufacturing method and a
`portable electronic apparatus of the present invention with
`reference to the drawingsin detail. In the following descrip-
`tion, conductivity types may be reversed and the constituent
`features described in each of embodiments maybe applied
`to other embodiments.
`
`Embodiment 1
`
`[0061] Asemiconductor storage device of Embodiment 1
`is substantially constituted by a single three-terminal device
`having a variable resistor.
`
`[0062] FIG. 1(a) is a schematic sectional view of a
`memorycell of a storage device formed on a glass panel of
`a liquid crystal TFT display device, as an example of the
`semiconductor storage device of the present invention. The
`storage device is used for adjusting an image. FIG. 1(b) is
`an equivalent circuit diagram of the memorycell.
`
`[0063] As shown in FIG. 1(a), the memory cell has: a
`P-type diffusion region 603 formed in a semiconductorlayer
`602 on a glass panel 601; an N-type diffusion region 604
`formed in contact with the P-type diffusion region 603 in the
`semiconductor layer 602; a memory functional element 605
`disposed on the semiconductor layer 602 across the bound-
`ary of the P-type diffusion region 603 and the N-type
`diffusion region 604; and a single electrode 607, whichis in
`contact with the memory functional element 605, formed on
`the P-type diffusion region 603 via an insulation film 606 so
`as to be insulated from the P-type diffusion region 603.
`Further, a refractory metal silicide film 608 is formed on the
`surface of the P-type diffusion region 603. A wire 609q is
`connected to the refractory metal silicide film 608. The
`refractory metal silicide film 608 is also formed on the
`surface of the N-type diffusion region 604. A wire 6095 is
`connectedto the refractory metalsilicide film 608. The wires
`609a and 6095 are connected to the refractory metalsilicide
`608 via contact plugs 612 filling contact holes opened in an
`interlayer insulation film 610.
`
`[0064] As shown in FIG.1(), a portion in the vicinity of
`the surface of the P-type diffusion region 603 and under the
`electrode 607 has a switch function. A portionin the vicinity
`of the surface of the P-type diffusion region 603 and under
`the memory functional element 605 serves as a variable
`
`resistor A. The electrode 607 has the function of an input
`terminal for changing over the switch. The switch and the
`variable resistor A are formed underthe electrode 607 and
`the memory functional element 605 formed adjacent to the
`electrode 607 (formed on the sidewall of the electrode 607).
`That is, the switch and the variable resistor A are formed so
`as to be adjacent to each other in a position defined by the
`boundary between the electrode 607 and the memory func-
`tional element 605, and are substantially integral. Therefore,
`the switch, the variable resistor and the electrode 607 are
`constituted by one device 631.
`[0065]
`In the case of constituting a memorycell array by
`arranging a plurality of memory cells,
`it
`is sufficient
`to
`connect the electrode 607 to a word line 622 and to connect
`one end of the device 631 to a bit line 623.
`
`[0066] The memorycell can be read/rewritten by applying
`predetermined voltages to the P-type diffusion region 603,
`the N-type diffusion region 604, and the electrode 607
`functioning as a selection word line.
`[0067] For example, by setting the voltage of the P-type
`diffusion region 603 as a reference potential, a voltage in the
`positive direction with respect to the reference potential is
`applied to the N-type diffusion region 604. At this time, by
`setting the electrode 607 in a non-selection state (for
`example, a state where the reference voltage is applied), the
`portion under the electrode 607 remains in the P-type.
`Consequently, the PN junction between the P-type diffusion
`region 603 and the N-type diffusion region 604 is reverse-
`biased and only a PN reverse-direction current
`flows
`between the wires 609a and 609b. The current value can be
`almost ignored. On the other hand, when the electrode 607
`is set to a selection state (for example, a voltage in the
`positive direction with respect to the reference voltage is
`applied), the portion under the electrode 607 is inverted to
`the N-type, so that a current accordingto the resistance value
`of the variable resistor A flows. Therefore, by detecting the
`current, memory information can be read out.
`[0068] The resistance value of the variable resistor A can
`be changed, that is, rewritten according to an amount of
`charges accumulated in the memory functional element 605.
`In order to accumulate charges in the memory functional
`element 605, by setting the P-type diffusion region 603 to a
`reference voltage and applying a reverse bias voltage which
`is very large as compared with that used at the time of
`reading (for example, three times or more as large as the
`potential difference at the time of reading) to the N-type
`diffusion region 604, an interband tunnel current is used.
`Specifically, electrons are accumulated in the memory func-
`tional element 605 when a positive voltage with respect to
`the reference voltage is applied to the electrode 607, and
`holes are accumulated in the memory functional element
`605 when a negative voltage is applied to the electrode 607.
`Bysetting the P-type diffusion region 603 to a reference
`voltage, applying a
`relatively large reverse bias
`(for
`example, about twice or three times as large as that at the
`time of reading) to the N-type diffusion region 604, and
`simultaneously applying a positive voltage to the electrode
`607, charges may be accumulated in the memory functional
`element 605 by channelhotelectrons. Alternatively, charges
`may be accumulated in the memory functional element 605
`by both of them.
`[0069]
`In the case where the N-type diffusion region 604
`and the P-type diffusion region 603 have reverse conduc-
`
`
`
`US 2004/0164359 Al
`
`Aug. 26, 2004
`
`tivity types, by reversing all of the signs of the above applied
`voltages, rewriting operation can be performed similarly.
`
`the memory cell of this
`[0070] As described above,
`embodimentis constituted by substantially one device, and
`the device has only three terminals. It is therefore possible
`to realize scale-down and high-integration of the semicon-
`ductor storage device.
`
`[0071] The memory functional element 605 includes, at
`least, a region for holding charges or a film having the
`function of accumulating and holding charg