O
`Umted States Patent
`
`[19]
`
`USOOS792695A
`
`[11] Patent Number:
`
`5,792,695
`
`
`Ono et al.
`[45] Date of Patent:
`Aug. 11, 1998
`
`[54] MANUFACTURING METHOD OF A
`SEMICONDUCTOR EPROM DEVICE
`
`Primary Examiner—Joni Chang
`Attorney Agent, or Firm—Loch & Loeb LLP
`
`[75]
`
`Inventors: Masahiro Ono. Sawa-gun; Masaji
`Sakamura. Tatebayashi; Toshiharu
`Matsuda. Oura-gun. all of Japan
`
`[73] Assignee: Sanyo Electric Co., Ltd.. Osaka. Japan
`
`[21] App]. No.: 866,425
`_
`FllCd!
`
`[22]
`
`May 309 1997
`.
`.
`.
`‘
`.
`.
`Foreign Appllcauon Priority Data
`[30]
`May 31. 1996
`[JP]
`Japan .................................... 8-139207
`Mar. 18, 1997
`[JP]
`Japan .................................... 9—065042
`1
`.6 ...................
`‘
`,
`HOIL 2113346581251; 32322::
`[22}
`(Ill; (31
`
`'
`"
`[
`f
`'
`’
`'
`[53] Field Of Search ..................................... 438/257—267.
`257/314-321‘ 324
`
`[56]
`
`.
`References CItEd
`us PATENT DOCUMENTS
`
`gagggg 32% 3‘1"]: et 31' """""""""""""""" 3:23:
`
`9/1991 Y:h """"""" 43505;,
`5’045’488
`
`5,067,108
`“/1991 Jenq
`365/185
`
`5,1995 Komori a al.
`5:427:966
`438/257
`............................... 438/258
`5,552,331
`9/1996 Hsu et a].
`FOREIGN PATENT DOCUMENTS
`
`[57]
`
`ABSTRACT
`
`.
`_
`A first convex pornon and a second convex pomon are
`formed on a semiconductor substrate at a prescribed interval.
`3" imPUfitY diffusing region is form“! 011 an “P1351" Portion
`of the semiconductor substrate placed between the first and
`second convex portions. and a thinned first polysilicon film
`is formed on the impurity diffusing region and the first and
`second convex portions. Thereafter. arsenic ions are
`implanted into the first polysilicon film to make the first
`polysilicon film conductive. Thereafter. a second polysilicon
`film having a film thickness larger than that of the first
`polysilicon film is formed, and phosphorus ions are
`implanted into the second polysilicon film to make the
`second polysilicon film conductive. Thereafter. a tungsten
`silicide film is formed on the second polysilicon film. and
`thC tungsten silicide film and the first and secondpolysilicon
`films are patterned. Therefore. a two—layer structured elec-
`trode wiring film composed of a patterned tungsten silicide
`film and a combination of a patterned first polysilicon film
`and a patterned second polysilicon film is formed. Because
`the first polysilicon film is thinned. the first polysilicon film
`can be sufliciently conductive. Therefore. the first polysili-
`con film is electrically connected with the second polysili—
`con film on the first and second convex portions even though
`the second polysilicon film is not sufficiently conductive.
`and thc clwfiodt wiring film can be clcctricauy conncctcd
`with the impurity djlfusing region.
`
`5267368
`
`10/1993
`
`Japan .
`
`4 Claims, 12 Drawing Sheets
`
`
`mm‘t‘
`turn!
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`37
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`42
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`33
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`32
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`42 42 37
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`32
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`37
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`38
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`4|
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`3|
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`IP Bridge Exhibit 2220
`IP Bridge Exhibit 2220
`TSMC v. Godo Kaisha IP Bridge 1
`TSMC v. Godo Kaisha IP Bridge 1
`IPR2017-01843
`IPR2017-01843
`
`

`

`US. Patent
`
`Aug. 11, 1998
`
`Sheet 1 of 12
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`5,792,695
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`F lG.l (PRIOR ART)
`9A
`IOB
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`

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`US. Patent
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`Aug. 11, 1998
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`Sheet 2 of 12
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`5,792,695
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`FIG. 3
`(PRIOR ART)
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`
`
`FIG.5
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`US. Patent
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`Aug. 11, 1998
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`Sheet 3 of 12
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`F | G. 7
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`
`- '9
`
`
`IIII‘
`I'llla.
`l
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`l7
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`l6
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`ISA
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`14A
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`

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`Aug. 11, 1998
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`Sheet 4 of 12
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`US. Patent
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`Aug. 11,1993
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`Sheet 5 of 12
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`FIG.|O
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`US. Patent
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`Aug. 11, 1998
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`Sheet 6 of 12
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`US. Patent
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`Aug. 11, 1998
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`Sheet 7 of 12
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`FIG.
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`l2
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`
`

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`US. Patent
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`Aug. 11, 1998
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`Sheet 8 of 12
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`Aug. 11, 1998
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`Sheet 9 of 12
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`FIG.I6
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`36
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`41
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`37
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`33
`
`FIG.
`
`IT
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`75AS+
`
`/¢w
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`

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`US. Patent
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`Aug. 11, 1998
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`Sheet 10 of 12
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`US. Patent
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`Aug. 11, 1993
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`Sheet 11 of 12
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`5,792,695
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`F | G .20
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`488
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`4546 47
`48A
`48A
`r—A*—\
`r—Afl49 49A
`454647
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`47 46 45
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`
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`38 41
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`38 33
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`36
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`33
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`38
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`4|
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`3|
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`US. Patent
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`Aug. 11, 1998
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`Sheet 12 of 12
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`5,792,695
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`

`

`1
`MANUFACTURING METHOD OFA
`SEMICONDUCTOR EPROM DEVICE
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`
`The present invention relates generally to a manufacturing
`method of a semiconductor apparatus. and more particularly
`to a method in which a two—layer structured electrode wiring
`film including a silicide film such as a combination of a
`polysilicon film and a tungsten silicide (WSix) film is
`formed.
`
`2. Description of the Prior Art
`A conventional semiconductor apparatus is described
`with reference to FIG. 1.
`
`As shown in FIG. 1. an impurity diflusing region 2 is
`formed on an upper surface of a semiconductor substrate 1.
`two MOS transistors are formed on the semiconductor
`substrate 1 to be adjacent to the impurity diffusing region 2.
`a two—layer structured electrode wiring film 9A composed of
`a polysilicon film 8 making contact with the impurity
`diffusing region 2 and a tungsten silicide (WSix) film 9 is
`formed between the MOS transistors.
`
`In detail. the impurity diffusing region 2 is formed by
`implanting n+ impurity into an upper portion of the semi-
`conductor substrate 1. a gate insulating film 3 is formed on
`the semiconductor substrate 1 so as to expose the impurity
`diflusing region 2. and a first gate electrode 4A and a second
`gate electrode 4B facing each other are formed on the gate
`insulating film 3. Also. a first insulating film 5A is formed on
`the first gate electrode 4A. and a second insulating film 5B
`is formed on the second gate electrode 413. Also. a first side
`wall spacer film 7A is formed on a side wall of a combina-
`tion of the first gate electrode 4A and the first insulating film
`5A. and a second side wall spacer film 7B is formed on a
`side wall of a combination of the second gate electrode 4B
`and the second insulating film 5B on condition that the first
`and second side walls 7A and 7B face each other.
`
`the electrode wiring film 9A composed of the
`Also.
`polysilicon film 8 and the tungsten silicide (WSix) film 9 is
`formed on the impurity difiusing region 2. In the polysilicon
`film 8. impurity is implanted to make the polysilicon film 8
`conductive. so that the polysilicon film 8 electrically con-
`nected with the impurity difiusing region 2.
`In addition. a first wiring film 6A is formed on the first
`insulating film SA. a second wiring film 6B is formed on the
`second insulating film 5B. and the first and second wiring
`films 6A and 6B and the first and second insulating films 5A
`and 5B are covered with an inter-layer insulating film 10A
`made of boron-phoso silicate glass.
`Also. after a photo-resist film (not shown) is formed on
`the inter-layer insulating film 10A. an opening area is
`' formed in the inter-layer insulating film 10A by using the
`photo-resist film as a mask so as to expose the electrode
`wiring film 9A composed of the polysilicon film 8 and the
`tungsten silicide (WSix) film 9. and the electrode wiring film
`9A and the inter-layer insulating film 10A are covered with
`a metal wiring film 1013 made of aluminum or a material
`including aluminum (for example. Al-Si-Cu) to electrically
`make the electrode wiring film 9A contact with the metal
`wiring film 10B.
`To obtain a structure of the conventional apparatus shown
`in FIG. 1. the polysilicon film 8 is formed to be filled in a
`concave area between the first side wall spacer film 7A
`formed on the side wall of the combination of the first gate
`electrode 4A and the first insulating film 5A and the second
`
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`side wall spacer film 7B formed on the side wall of the
`combination of the second gate electrode 4B and the second
`insulating fihn SB. ions are implanted in the polysilicon film
`8 to make the polysilicon film 8 conductive. and the tungsten
`silicide (WSix) film 9 is formed on the polysilicon film 8.
`Thereafter. after a photo-resist film is formed on the tungsten
`silicide film 9. the tungsten silicide film 9 and the polysilicon
`film 8 are patterned by etching and removing a portion of the
`tungsten silicide film 9 and a portion of the polysilicon film
`8 while using the photo-resist film as a mask. Therefore. as
`shown in FIG. 2. the electrode wiring film 9A is formed.
`Thereafter. after the inter-layer insulating film 10A is
`formed over the entire Sin-face of the electrode wiring film
`9A and the entire surface of the first and second insulating
`films 5A and 5B. an opening area is formed in the inter—layer
`insulating film 10A to expose the tungsten silicide film 9. an
`aluminum film is formed over the entire surface of the
`tungsten silicide film 9 and the entire stu'face of the inter-
`layer insulating film 10A and is patterned. Therefore. the
`metal wiring film 108 electrically connected with the elec-
`trode wiring film 9A is formed.
`However. in cases where the conventional semiconductor
`apparatus is manufactured according to the above method.
`there are many drawbacks. That is. it is required to thin the
`polysilicon film 8 to arrange the electrode wiring film 9A
`composed of the polysilicon film 8 and the tungsten silicide
`(WSix) film 9 in the conventional semiconductor apparatus.
`In this case. because a film thickness of the polysilicon film
`8 is made small. as shown in FIG. 2. a ravine area CP is
`formed on the tungsten silicide (WSix) film 9 when the
`tungsten silicide (WSix) film 9 is formed on the polysilicon
`film 8. Therefore. when a photo-resist film planned to be
`used as a mask in a patterning operation of the electrode
`wiring film 9A is patterned in a photo-lithography process
`by exposing the photo—resist film to light. the photo-resist
`film undesirably remains in the ravine area CP. so that there
`is a first drawback that the electrode wiring film 9A cannot
`be reliably patterned. To prevent this drawback. in cases
`where an intensity of the exposing light is increased. hala-
`tion occtn's in the exposing operation. so that there is another
`drawback that the photo-resist film is not correctly patterned
`and the electrode wiring film 9A cannot be patterned with
`high accuracy.
`Also. because a film thickness of the polysilicon film 8 is
`made small. a height of the electrode wiring film 9A is
`lowered. Therefore. as shown in FIG. 1. a height al of a side
`wall of the inter-layer insulating film 10A is heightened. an
`opened area surrounded by the side wall of the inter-layer
`insulating film 10A is deepened. In this case. there is a
`second drawback that a step coverage of the metal wiring
`film 10B arranged on the side wall of the inter-layer insu-
`lating film 10A is degraded.
`To avoid the first and second drawbacks. as shown in FIG.
`3. there is an idea that a polysilicon film 8A placed beneath
`the tungsten silicide (WSix) film 9 is thickened.
`However. in an ion implanting process pm‘formed to make
`the polysilicon film 8A conductive. though ions are suffi-
`ciently implanted in an upper portion of the polysilicon film
`8A. ions are not sufiiciently implanted into a bottom portion
`PB of the polysilicon film 8A near to the impurity difiusing
`region 2. Also. ions are not sufficiently dilfused from the
`bottom portion PB of the polysilicon film 8A to the substrate
`1. Therefore. the polysilicon film 8A is not sufl‘iciently made
`conductive. Accordingly. there is another drawback that a
`contact resistance of the polysilicon film 8A becomes higher
`than a desired value. Also. there is another drawback that
`
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`contact resistances in various portions of the polysilicon film
`8A cannot be uniformly set because implanting amounts of
`ion in the various portions of the polysilicon film 8A differ
`from each other.
`To sufficiently inject ions into the bottom portion PB of
`the polysilicon film 8A. there is an idea that an acceleration
`voltage applied to the ions is heightened.
`However. in this case. an amount of ion implanted into the
`impurity difiusing region 2 placed beneath the polysilicon
`film 8A is increased. the ions implanted into the impurity
`dilfusing region 2 are ditfused in a lateral direction. so that
`there is another drawback that a punch through occurs in the
`MOS transistors of the conventional semiconductor appa—
`ratus. Also. to prevent the implantation of ions into the first
`and second gate electrodes 4A and 4B through the first and
`second insulating films 5A and 513. it is required to cover a
`region other than an ion implanting region positioned on the
`electrode wiring film 9A with a photo-resist. Therefore.
`there is another drawback that the number of manufacturing
`processes is increased by adding a masldng process.
`SUMMARY OF THE INVENTION
`
`An object of the present invention is to provide. with due
`consideration to the drawbacks of such a conventional
`semiconductor apparatus. a semiconductor apparatus in
`which a two—layer structured electrode wiring film com-
`posed of a silicide film and a polysilicon film is arranged to
`be electrically connected with an impurity diffusing region
`on condition that the polysilicon film is sufficiently thick—
`ened and contact resistances in various portions of the
`polysilicon film are uniformly set to a low value.
`In a manufacturing method of a semiconductor apparatus
`according to the present invention. a first thinned polysilicon
`film is formed on a first convex portion. a second convex
`portion and an impurity ditfusing region. ions are implanted
`into the first polysilicon film to make the first polysilicon
`film conductive. a second polysilicon film having a film
`thickness larger than that of the first polysilicon film is
`formed on the first polysilicon film. ions are implanted into
`the second polysilicon film to make the second polysilicon
`film conductive. and a silicide film is formed on the second
`polysilicon film. Therefore. even though a total thiclmess of
`the first and second polysilicon films is made large and a
`height of an electrode wiring-film composed of the silicide
`film and the first and second polysilicon films is heightened.
`a contact resistance of a group of the first and second
`polysilicon films can be made small and set to a desired
`value.
`
`Therefore. because it is not required to thin the group of
`the first and second polysilicon films for the purpose of
`maintaining the contact resistance of the group of the first
`and second polysilicon films to a low value. there is no case
`that a photo-resist film planned to be used as a mask in a
`patterning operation of the electrode wiring film is incor-
`rectly patterned in a photo-lithography process. Also.
`because a height of a side wall of an inter-layer insulating
`film surrounding an opening area placed on the electrode
`wiring film is not heightened. the depth of the opening area
`is not deepened. so that there is no case that a step coverage
`of a metal wiring film formed on the inter-layer insulating
`film along the side wall of the inter-layer insulating film is
`degraded.
`Also. because the ions can be uniformly implanted into
`each of the first and second polysilicon films. contact
`resistances in various portions of each polysilicon film can
`be uniformly set. Therefore. conductivity of each of the first
`and second polysilicon films can be uniformly set.
`
`4
`Also. in cases where the semiconductor apparatus accord—
`ing to the present invention is applied for a non—volatile
`semiconductor memory. when an electrode wiring film com-
`posed of a silicide film and a polysilicon film making contact
`with a small contact hole is formed on an impurity difiusing
`region formed according to a self—aligning process such as a
`drain region. an ion implanting process performed to make
`the polysilicon film conductive can be stabilized. the reli—
`ability of the apparatus can be improved. a contact resistance
`of the polysilicon film can be lowered. and data writing and
`reading operations can be performed in the storing apparatus
`with a high speed.
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a cross sectional view of a conventional semi-
`conductor apparatus.
`FIG. 2 is a first cross sectional view of the conventional
`semiconductor apparatus in a manufacturing step to explain
`a drawback in a manufacturing method of the conventional
`semiconductor apparatus.
`FIG. 3 is a second cross sectional view of another
`conventional semiconductor apparatus in a manufacturing
`step to explain another drawback in a manufacturing method
`of the conventional semiconductor apparatus.
`FIG. 4 is a first cross sectional view of a semiconductor
`apparatus in a first manufacturing process according to a first
`embodiment of the present invention.
`FIG. 5 is a second cross sectional view of the semicon-
`ductor apparatus in a second manufacturing process accord—
`ing to the first embodiment of the present invention.
`FIG. 6 is a third cross sectional view of the semiconductor
`apparatus in a third manufacturing process according to the
`first embodiment of the present invention.
`FIG. 7 is a fourth cross sectional view of the semicon-
`ductor apparatus in a fourth manufacturing process accord-
`ing to the first embodiment of the present invention.
`FIG. 8 is a fifth cross sectional view of the semiconductor
`apparatus in a fifth manufacturing process according to the
`first embodiment of the present invention.
`FIG. 9 is a sixth cross sectional view of the semiconductor
`apparatus in a sixth manufacturing process according to the
`first embodiment of the present invention.
`FIG. 10 is a first cross sectional View of a semiconductor
`apparatus according to a second embodiment of the present
`invention.
`FIG. 11 is a plan view of the semiconductor apparatus
`according to the second embodiment of the present inven-
`tion.
`FIG. 12 is a second cross sectional view of the semicon-
`ductor apparatus in a first manufacturing process according
`to the second embodiment of the present invention.
`FIG. 13 is a third cross sectional view of the semicon-
`ductor apparatus in a second manufacturing process accord-
`ing to the second embodiment of the present invention.
`FIG. 14 is a fourth cross sectional view of the semicon—
`ductor apparatus in a third manufacturing process according
`to the second embodiment of the present invention.
`FIG. 15 is a fifth cross sectional View of the semiconduc-
`tor apparatus in a fourth manufacturing process according to
`the second embodiment of the present invention.
`FIG. 16 is a sixth cross sectional view of the semicon—
`ductor apparatus in a fifth manufacturing process according
`to the second embodiment of the present invention.
`FIG. 17 is a seventh cross sectional view of the semicon-
`ductor apparatus in a sixth manufacturing process according
`to the second embodiment of the present invention.
`
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`FIG. 18 is an eighth cross sectional view of the semicon-
`ductor apparatus in a seventh manufacturing process accord-
`ing to the second embodiment of the present invention.
`FIG. 19 is a ninth cross sectional view of the semicon—
`ductor apparatus in an eighth manufacturing process accord-
`ing to the second embodiment of the present invention.
`FIG. 20 is a tenth cross sectional View of the semicon-
`ductor apparatus in a ninth manufacturing process according
`to the second embodiment of the present invention.
`FIG. 21 is an eleventh cross sectional view of the semi-
`conductor apparatus in a tenth manufacturing process
`according to the second embodiment of the present inven-
`tion.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`Preferred embodiments of a semiconductor apparatus
`according to the present invention are described with refer-
`ence to drawings.
`
`(First Embodiment)
`In a semiconductor apparatus according to the first
`embodiment. two MOS transistors are formed on a semi-
`conductor substrate on condition that the MOS transistors is
`adjacent to an impurity diffusing region formed in an upper
`portion of the semiconductor substrate. and a twolayer
`structured electrode wiring film composed: of a polysilicon
`film and a tungsten silicide (WSix) film is formed on the
`semiconductor substrate and the MOS transistors on condi-
`tion that the polysilicon is made contact with the impurity
`difiusing region.
`A plurality of manufacturing steps performed to obtain a
`structure of a semiconductor apparatus shown in FIG. 4 are
`initially described.
`An upper portion of a semiconductor substrate 11 is
`oxidized to form a gate“ insulating film 13 having a film
`thickness of about 100 A. and a polysilicon film having a
`film thickness of about 2500 A is formed on the gate
`insulating film 13. The polysilicon film is planned to func-
`tion as gate electrodes of MOS transistors.
`Next. an oxide film having a film thickness of about 2500
`A is formed on the polysilicon film and the polysilicon film
`and the oxide film are patterned to form a first gate electrode
`14A and a second gate electrode 14B. and a first and second
`insulating films 15A and 1513 are formed on the first gate
`electrode 14A and the second gate electrode 14B respec-
`tively.
`The gate electrodes 14A and 14B are planned to be
`adjacent to both ends of an n+ type impurity ditfusing region
`12 through the gate insulating film 13.
`Thereafter. impurity is implanted into an upper portion of
`the semiconductor substrate 11 placed between the first and
`second gate electrodes 14A and 14B and is diflused in the
`semiconductor substrate 11. Therefore. the n+ type impurity
`diffusing region 12 is formed. In this impurity diflusing
`region forming step. an n—type impurity such as phosphorus
`ions (31?) is implanted into the upper portion of the
`semiconductor substrate 11 at a dose of 1.0“ 1013 cm"2 and
`an accelerating voltage of 40 KeV while using the first and
`second gate electrodes 14A and 14B and the first and second
`insulating films 15A and 158 as a mask. the semiconductor
`substrate 11 is annealed to diffuse the n-type impurity into
`the semiconductor substrate 11. so that the n+ type impurity
`diffusing region 12 is formed.
`In this embodiment. phosphorus ions (3’?) are used as
`the n-type impurity. However. it is applicable that arsenic
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`ions (75As+) be implanted into the semiconductor substrate
`11 at a dose of 5.0*1015 cm2 and an accelerating voltage of
`60 KeV.
`
`Thereafter. an insulating film (or an oxidized film) having
`a film thickness of about 2000 A is formed on the entire
`surface of the semiconductor apparatus according to a CVD
`method. and an anisotropic etching is performed for the
`insulating film to form a first side wall spacer film 22A on
`side walls of the first gate electrode 14A and the first
`insulating film 15A and form a second side wall spacer film
`2213 on side walls of the second gate electrode 14B and the
`second insulating film 15B. Thereafter. as shown in FIG. 4.
`a first polysilicon layer 16 is formed on the entire surface of
`the semiconductor apparatus at a film thickness ranging
`from 200 A to 500 A according to the CVD method. and an
`n-type impurity such as arsenic ions (75As+) is implanted
`into the first polysilicon layer 16 at a dose of 5.O*10ls cm‘2
`and an accelerating voltage ranging from 30 KeV to 100
`Kev. Therefore. the first polysilicon layer 16 is sufficiently
`made conductive. and the first polysilicon layer 16 is elec-
`trically connected with the n+ type impurity diffusing region
`12.
`
`As an optimum condition of the implantation of the n—type
`impurity.
`in cases where the film thickness of the first
`polysilicon layer 16 is. for example. 500 A. arsenic ions
`(75As+) are implanted into the first polysilicon layer 16 as a
`first ion implantation at a dose of 5.0“ 1015 crn‘2 and an
`accelerating voltage of 30 KeV. and arsenic ions (75As+) are
`implanted into the first polysilicon layer 16 as a second ion
`implantation at a dose of 5.0"‘10ls crn‘2 and an accelerating
`voltage of 95 KeV. Therefore. a peak of a concentration
`distribution of the arsenic ions in the first ion implantation
`is positioned at the center of the first polysilicon layer 16.
`and a peak of a concentration distribution of the arsenic ions
`in the second ion implantation is positioned at an interface
`between a bottom portion of the first polysilicon layer 16 and
`the semiconductor substrate 11. Accordingly. contact resis-
`tances in various portions of the first polysilicon layer 16 can
`be uniformly set to a low value.
`In this embodiment. arsenic ions (75As+) are used as the
`n-type impurity. However. it is applicable that phosphorus
`ions (3 1P4») be implanted into the first polysilicon layer 16.
`Next. an electrode wiring film forming process. in which
`an electrode wiring film is formed in a concave area placed
`between a first MOS transistor denoting a first convex
`portion and a second MOS transistor denoting a second
`convex portion to be made contact with the n+ type impurity
`dilfusing region 12. is described In this embodiment. a
`height of each convex portion is set to about 5000 A. and a
`width between the convex portions is set to about 0.4 pm
`(4000 A).
`As shown in FIG. 5. a second polysilicon film 17 is
`formed on the entire surface of the semiconductor apparatus
`according to the CVD method at a film thickness ranging
`from 2000 A to 3000 A sufficiently larger than that in the
`first polysilicon film 16. and an n-type impurity such as
`phosphorus ions (3 1P+) is implanted into the second poly—
`silicon film 17 at a dose of 5.0*10‘5 cm'2 and an acceler-
`ating voltage of 60 Kev. Therefore. the second polysilicon
`film 17 is made conductive. In this case. the second poly-
`silicon filrn 17 is sufliciently thickened. so that any narrowed
`convex portion is not forrued on the second polysilicon film
`17. Thereafter. as shown in FIG. 6. a tungsten silicide
`(WSix) film 18 having a film thickness of 1000 A is formed
`on the entire surface of the second polysilicon film 17. In this
`case. it is applicable that arsenic ions (75As+) be used as the
`n—type impurity in place of the phosphorus ions (3’P+).
`
`

`

`5 ,792,695
`
`7
`In this embodiment. after the first polysilicon film 16 is
`sufficiently made conductive. the second polysilicon film 17
`is formed on the first polysilicon film 16. and the n—type
`impurity is implanted into the second polysilicon film 17 to
`made the second polysilicon film 17 conductive. Therefore.
`as shown in FIG. 6. even though the implantation of the
`phosphorus ions (31P+) into the second polysilicon film 17
`is not sufficiently performed and the phosphorus ions (31P+)
`10 do not reach a bottom portion PB of the second polysili-
`con film 17 (refer to the symbol x in FIG. 6). because the
`phosphorus ions (“P-l») Io sufficiently reach portions of the
`second polysilicon film 17 close to upper ends of the first
`and second side wall spacer films 22A and 22.13. the portions
`of the second polysilicon film 17 can be electrically con-
`nected with the n+ type impurity diffusing region 12 through
`the first polysilicon fih'n 16.
`Accordingly. in the prior art shown in FIG. 3. though a
`contact resistance of the polysilicon film 8A is increased
`because the n-type impurity does not sufficiently reach the
`bottom portion PB of the polysilicon film 8A and contact
`resistances of various portions of the polysilicon film 8A are
`not uniformly set because the n—type impurity does not
`uniformly implanted into the bottom portion PB of the
`polysilicon film 8A. this drawback can be prevented in this
`embodiment.
`Thereafter. as shown in FIG. 7. a photo-resist film 19 is
`formed on a region in which the formation of an electrode
`wiring film is planned. and portions of the tungsten silicide
`(WSix) film 18 and the first and second polysilicon films 16
`and 17 are etched and removed to pattern the tungsten
`silicide (WSix) film 18 and the first and second polysilicon
`films 16 and 17 while using the photo-resist film 19 as a
`mask. Therefore. as shown in FIG. 8. a two-layer structured
`electrode wiring film 18A composed of a combination of the
`polysilicon films 16 and 17 and the tungsten silicide (WSix)
`film 18 is formed.
`
`In this embodiment. a combined polysilicon film com-
`posed of the polysilicon films 16 and 17 is sufficiently
`thickened. Accordingly. in the prior art shown in FIG. 2. the
`ravine area CP is formed on the tungsten silicide (WSix) film
`9 so that a resist—film used for the patterning of the tungsten
`silicide (WSix) film 9 undesirably remains in the ravine area
`CP or a halation occurs in cases where an intensity of the
`exposing light is increased to prevent the resist—film unde—
`sirably remain in the ravine area CP. Therefore. the pattern—
`ing of the tungsten silicide (WSix) film 9 cannot be correctly
`performed in the prior art. However. in this embodiment. any
`narrowed concave area is not formed on the second poly-
`silicon film 17 because the second polysilicon film 17 is
`sufficiently thickened Therefore. the patterning of the elec-
`trode wiring film 18A can be correctly performed.
`Thereafter. as shown in FIG. 9. a first wiring film 19A is
`formed on the first insulating film 15A. 3 second wiring film
`198 is formed on the second insulating film 158, an
`inter-layer insulating film 20 made of boron-phoso silicate
`glass is formed on the entire surface of the semiconductor
`apparatus. and an opening area is formed in the inter—layer
`insulating film 20 to expose the electrode wiring film 18A
`composed of the combined polysilicon film (the polysilicon
`films 16 and 17) and the tungsten silicide (WSix) film 18.
`Thereafter. aluminum or Al-Si-Cu is formed on the entire
`surface of the semiconductor apparatus and is patIerned to
`form a metal wiring film 21. Therefore. the electrode wiring
`film 18A is electrically connected with the metal wiring film
`21. and the manufacturing of the semiconductor apparatus is
`completed.
`Accordingly. as shown in FIG. 9. a height of the electrode
`wiring film 18A composed of the combined polysilicon film
`
`8
`(the polysilicon films 16 and 17) and the tungsten silicide
`(WSix) film 18 can be heightened. and a height a2 of a side
`wall of the inter—layer insulating film 20 facing an opening
`area placed on the electrode wiring film 18A can be lowered
`than the height al of the side wall of the inter—layer insu-
`lating film 10A in the prior art (32 <a1). Therefore. a step
`coverage of the metal wiring film 21 formed along the side
`wall of the inter-layer insulating film 20 is not degraded.
`In this embodiment. the electrode wiring film 18A is
`formed by laminating the combined polysilicon film (the
`polysflicon films 16 and 17) and the tungsten silicide (WSix)
`film 18. However. it is applicable that an electrode wiring
`film be formed by laminating the combined polysilicon film
`and a silicide film other than the tungsten silicide (WSix)
`film.
`
`Also. in this embodiment. the height of each convex
`portion is set to about 5000 A. the width between the convex
`portions is set to about 0.4 pm (4000 A). the first polysilicon
`film 16 is set to the film thickness ranging from 200 A to 500
`A. and the second polysilicon film 17 is set to the film
`thickness ranging from 2000 A to 3000 A. However. this
`embodiment is not limited these values. For example. in
`cases where the height of each convex portion is ranged
`from 4000 A to 6000 A and the width between the convex
`portions is ranged from 0.1 pm to 0.4 pm (1000 A to 4000
`A). the same effects as those in the first embodiment can be
`obtained on condition that the heights of the first and second
`polysilicon films 16 and 17 are the same as those in the first
`embodiment. Also. even though the height of each convex
`portion and the width between the convex portions are
`changed. in cases where the heights of the first and second
`polysilicon films 16 and 17 are adjusted according to the
`changed height of each convex portion and the changed
`width between the convex portions and ion implanting
`conditions are adjusted according to the adjusted heights of
`the first and second polysilicon films 16 and 17. the same
`effects as those in the first embodiment can be obtained.
`Also.
`in this embodiment.
`two MOS transistors are
`formed on the semiconductor substrate 11 to be adjacent to
`the impurity diffusing region 12 formed on the upper portion
`of the semiconductor substrate 11. and the two—layer struc-
`tured electrode wiring film 18A composed of the combined
`polysilicon film and the tungsten silicide (WSix) film 18 is
`formed between the two MOS transistors to make contact
`with the impurity difiusing region 12. However.
`this
`embodiment is not limited to this configuration. and it is
`applicable that a two—layer structured electrode wiring film
`be formed in a concave area placed between both convex
`portions. For example. it
`is applicable that a two-layer
`structured electrode wiring film be formed in a contact hole
`surrounded by an insulating film.
`
`(Second Embodiment)
`
`A second embodiment according to the present invention
`is described with reference to FIGS. 10 to 21.
`
`FIG. 11 is a plan view of the semiconductor apparatus
`according to a second embodiment of the present invention.
`and FIG. 10 is a cross sectiona