United States Patent
`Date of Patent:
`Nihira et a1.
`[45]
`Mar. 13, 1990
`
`[11]
`
`Patent Number:
`
`4,908,324
`
`[19]
`
`[54] METHOD OF MANUFACTURING BIPOLAR
`TRANSISTOR
`
`Attorney, Agent, or Firm—Oblon, Spivak, McClelland,
`Maier & Neustadt
`
`[75]
`
`Inventors:
`
`Hiroyuki Nihira, Ayase; Nobuyuki
`Itoh, Tokyo, both of Japan
`
`[73] Assignee:
`
`Kabushiki Kaisha Toshiba, Kawasaki,
`Japan
`
`[21]
`
`[22]
`
`Appl. No.: 225,804
`Filed:
`’Jul. 29, 1988
`
`Foreign Application Priority Data
`[30]
`Jul. 29, 1987 [JP]
`Japan ................................ 62-189419
`Oct.27, 1987 [JP]
`Japan ................................ 62-269259
`
`Int. c1.4 ................... H01L 21/314; H01L 21/225
`[51]
`[52] US. Cl. ........................................ 437/31; 437/33;
`437/162; 437/223; 357/34; 156/653
`[58] Field of Search ..................... 437/31,32,33, 162,
`437/228, 239; 357/34, 35; 156/643, 653;
`148/DIG. 51, DIG. 103, DIG. 131
`References Cited
`
`[56]
`
`U.S. PATENT DOCUMENTS
`
`4,693,782
`
`9/1987 Kikuchi et a1.
`
`....................... 437/31
`
`OTHER PUBLICATIONS.
`
`. 1’, IEEE
`Konaka, S. et al., “A 30—ps Si Bipolar IC .
`Trans. Elect. Devices, vol. ED—33, No. 4, Apr. 1986, pp.
`526-531.
`Kikuchi, K. et al., “A High-Speed Bipolar LSI Procen
`. .”, IEEE—IEDM Tech. Digest, 1986, pp. 420—423.
`
`Primary Examiner—Brian E. Hearn
`Assistant Exgminer—T. N. Quach
`
`[57]
`
`ABSTRACT
`
`A method of manufacturing a bipolar transistor is dis-
`closed. A first mask material film pattern is formed on
`an internal base region prospective portion on a colleo
`tor region of a first conductive type, and then a first
`conductive film is deposited. A recess around the pro-
`jection of the mask film pattern are transferred on the
`surface of the first conductive film. After a second mask
`
`material film pattern is buried in the recess, the first
`conductive film is selectively etched using the second
`mask material pattern as a mask, thereby exposing the
`first mask material film pattern. The first conductive
`film is continuously, selectively etched by anisotropic
`etching using the exposed first mask material film pat-
`tern and the second mask material film pattern as etch—
`ing masks to form a first opening between the two mask
`material film patterns. An impurity of a second conduc-
`tivity type is doped through the first opening to form an
`external base region. The first opening is buried with a
`second conductive film before or after formation of the
`external base region. The first mask material film pat-
`tern is removed to form a second opening. After a ther-
`mal oxide film is formed on the surface of the second
`conductive film, an impurity of the second conductivity
`type is doped through the second opening,
`thereby
`forming the internal base region. An impurity of the
`first conductivity type is doped in the wafer through the
`second opening to form an emitter region.
`
`19 Claims, 16 Drawing Sheets
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`IP Bridge Exhibit 2219
`IP Bridge Exhibit 2219
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`TSMC v. Godo Kaisha IP Bridge 1
`IPR2017-01843
`IPR2017-01843
`
`

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`US. Patent Mar.13, 1990
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`US. Patent Mar. 13, 1990
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`US. Patent Mar.13, 1990
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`US. Patent Mar. 13, 1990
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`' US. Patent Mar. 13,1990
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`US. Patent Mar. 13,1990
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`_ US. Patent Mar. 13, 1990
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`US. Patent Mar. 13,1990
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`US. Patent Mar. 13, 1990
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`US. Patent Mar.13, 1990
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`'
`
`1
`
`4,908,324
`
`METHOD OF MANUFACTURING BIPOLAR
`TRANSISTOR
`
`BACKGROUND OF THE INVENTION
`l. Field of the Invention
`
`The present invention relates to a method of manu-
`facturing a high-performance ultra-miniaturized bipolar
`transistor and, more particularly, to a method of form-
`ing a base region and an emitter region by self align-
`ment.
`2. Description of the Prior Art
`A high performance bipolar transistor is required in
`various fields such as computers, optical communica-
`tion, and various analog circuits. Especially, an ultra-
`miniaturized bipolar transistor which has a high cut—off
`frequency and can be integrated in an LSI is required.
`In order to manufacture the above ultra-miniaturized
`bipolar transistor, several techniques for forming a base
`region and an emitter region by self alignment have
`been recently proposed. Cut-off frequencies of bipolar
`transistors manufactured by these techniques almost
`reach 30 GHz.
`
`(1) IEEE Trans. on Electron Devices, Vol. ED-33,
`No. 4, Apr. 1986, p.526,
`(2) Japanese Patent Disclosure (Kokai) No. 58-7862,
`(3) ISSCC87, 1987, p.58.
`Typical conventional techniques and their problems
`will be described below.
`FIGS. 1A to 1D show manufacturing steps in one
`conventional technique. As shown in FIG. 1A, a wafer
`has n+~type buried region 22 formed on p-type Si sub-
`strate 21 and n«type epitaxial layer 23 formed thereon.
`P-type channel stopper region 24 is formed in element
`isolation region of the wafer, and field oxide film 25 is
`formed by selective oxidation. Thin thermal oxide film
`26 is-formed on the surface of an element region of the
`wafer, nitride-film (Si3N4 film) 27 serving as an anti-oxi-
`dation mask is deposited, and then first polycrystalline
`silicon film 28 is deposited. Subsequently, film 28 is
`selectively, thermally oxidized to change an unneces-
`sary portion on the element isolation region into oxide
`film 29. Then, boron is doped in film 28 by ion implanta-
`tion. Thereafter, film 28 is selectively etched by photo-
`etching to form an opening in an emitter formation
`region as shown in FIG. 1A.
`Then, as shown in FIG. 1B, the resultant structure is
`heat-treated in an oxygen atmosphere to form oxide film
`30 on the surface of film 28, and then film 27 at the
`opening portion is etched by a heated aqueous phos-
`phoric acid solution, using film 30 as a mask. Thereafter,
`exposed film 26 is removed by an aqueous NH4F solu-
`tion to expose the wafer surface. At this time, by inten-
`tionally over-etching film 27, overhang portion 31 is
`formed along an edge of film 28 as shown in FIG. 1B.
`Then, second polycrystalline silicon film 32 is depos-
`ited on the entire surface, and embedded in overhang
`portion 31. Subsequently,
`the second polycrystalline
`film 32 is etched, thereby exposing the oxide film 30 and
`the surface of the wafer in the opening, as shown in
`- FIG. 1C.
`Then, the exposed wafer surface and a side surface of
`film 32 as shown in FIG. 1C, are thermally oxidized to
`form thermal oxide film 33, as shown in FIG. 1D. Dur-
`ing thermal oxidation, the boron doped in film 28 is
`diffused into the wafer through film 32, thereby forming
`p-type external base region 34. Subsequently, boron is
`ion-implanted through the opening portion to form
`
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`p—type internal base region 35. Thereafter, CVD insulat—
`ing film 36 and third polycrystalline silicon film 37 are
`deposited and then etched back by reactive ion etching
`so that films 36 and 37 remain on side walls of the open-
`ing portion. Then, film 33 on the wafer surface at the
`opening portion is etched using residual film 37 as a
`mask to expose the wafer surface. Thereafter, fourth
`polycrystalline silicon film 38 doped with arsenic hav-
`ing a high concentration is deposited and annealed. At
`this time, the arsenic in film 38 is diffused into the wafer
`to form n-type emitter region 39, thereby obtaining a
`bipolar transistor shown in FIG. 1D. Note that first and
`second polycrystalline silicon films 28 and 32 are used
`as a base electrode, and fourth polycrystalline silicon
`film 38 is used as an emitter electrode.
`
`According to the above method shown in FIGS. 1A
`to 1D, the base and emitter regions are formed by self
`alignment. In addition, since a structure is miniaturized,
`i.e., the width of an emitter diffusion window is as small
`as 0.35 pm, a bipolar transistor having excellent high-
`speed operation .characteristics can be obtained. How- _
`ever, according to this method, it is difficult to control
`the size of overhang portion 31 in FIG. 1B. That is, in
`a step of etching nitride film 27 by an aqueous phos-
`phoric acid solution to form overhang portion 31, it is
`difficult to control conditions such as a temperature, a
`concentration of the phosphoric acid, and a stirring
`state . For this reason, the size of overhang portion 31
`varies in different wafers and in each individual wafer,
`resulting in variations in element characteristics.
`In the step of FIG. 1C, when second polycrystalline
`film 32 is etched to be buried below overhang portion
`31, the wafer surface formed also of silicon is simulta—
`neously etched. Therefore, the wafer surface of the
`emitter region is damaged. In addition, the width of the
`polycrystalline silicon film (which largely affects the
`width of the external base region) to be buried below
`the overhand portion varies, resulting in variations in
`characteristics such as a breakdown voltage and a cut-
`off frequency.
`FIGS. 2A to 2D show manufacturing steps of an-
`other conventional method. In this method, as shown in
`FIG. 2A, n+-type buried region 42 is formed on p-type
`Si substrate 41 to grow n-type epitaxial layer 43. P-type
`channel stopper region 44 is formed in an element isola-
`tion region, and thick field oxide film 45 is formed. The
`above steps are the same as in the above conventional
`method. Thereafter, nitride film 46 serving as an anti-
`oxidation mask and CVD oxide film 47 are sequentially
`deposited on the entire surface and patterned so that
`films 46 and 47 remain in an emitter region of an ele-
`ment and the element isolation region.
`Then, as shown in FIG. 2B, first polycrystalline sili-
`con film 48 is deposited on the entire surface, and boron
`is ion-implanted in film 48. Subsequently, thick photore-
`sist film 49 is formed on the surface of film 48, and the
`entire surface is flattened. Thereafter, the thick photore-
`sist film is etched back. As a result, as shown in FIG.
`213, film 48 on film 47 is exposed, and photoresist 49 is
`buried in the recess of film 48.
`Then, film 48 is etched using photoresist 49 as a mask
`to expose the surface of film 47. Thereafter, CVD insu-
`lating film 471 at a portion serving as an emitter region
`is removed, and thermal oxidation is performed using
`film 46 as a mask, thereby forming oxide film 50 on the
`surface of film 48. At the same time, the boron in film 48
`is thermally diffused into the wafer to form p<type layer
`
`

`

`4,908,324
`
`3
`51 serving as an external base region as shOWn in FIG.
`2C.
`Thereafter, film 46 is removed by a heated aqueous
`phosphoric acid solution to form an emitter opening
`portion. Then, as shown in FIG. 2D, second polycrys-
`talline silicon film pattern 53 for burying the emitter
`opening portion is formed. Boron is ion-implanted in
`film 53 at a high concentration and annealed, thereby
`diffusing the boron into the wafer to form internal base
`layer 52. Then, arsenic is ion-implanted in film 53 at a
`high concentration and annealed, thereby diffusing the
`arsenic into the wafer to form n-type emitter layer 54.
`As a result, an npn transistor is completed.
`In the conventional method shown in FIGS. 2A to
`2D, unlike in the conventional method shown in FIGS.
`1A to ID, no overhang portion is formed and therefore
`a polycrystalline silicon film is not buried below the
`overhang portion, i.e., manufacturing steps difficult to
`be controlled are not present. In addition, the emitter
`and internal base layers can be formed by self align-
`ment.
`
`However, according to the conventional method
`‘ shown in FIGS. 2A to 2D, a relationship between exter-
`nal base region 51 and emitter region 54 cannot be com-
`pletely defined by self alignment. This is because a por-
`tion from CVD insulating film 471 which defines the
`emitter region to insulating film 45 is entirely the exter-
`nal base region as shown in FIG. 2C. Therefore, if mask
`alignment for forming CVD insulating films 471 to 473 is
`offset in FIG. 1A, widths of external base region 51
`differ from each other at right and left sides of emitter
`region 54, resulting in variations in the element charac-
`teristics. In addition, in order to form CVD insulating
`film 471 for defining the emitter region, a mask align-
`ment margin must be assured in a photolithography
`step. For this reason, the external base region is en-
`larged to increase the size of the element as a whole. As
`a result, an unnecessary stray capacitance or parasitic
`resistance is increased.
`As described above, according to the conventional
`methods of manufacturing a high-performance bipolar
`transistor, it is difficult to control formation of an over—
`hang portion, or self alignment is incomplete. There-
`fore, a bipolar transistor which stably performs a high-
`speed operation cannot be obtained.
`SUMMARY OF THE INVENTION
`
`It is, therefore, an object of the present invention to
`provide a method of manufacturing a bipolar transistor,
`which solves the above-described prior art problems.
`The above object of the present invention is achieved
`by a method of manufacturing a bipolar transistor, com-
`prising the following steps (a) to (l):
`(a) forming an insulating film on a semiconductor
`wafer having a collector region of a first conduc-
`tivity type;
`(b) depositing a first mask material film on the insulat-
`ing film, and patterning the first mask material film,
`thereby forming a first mask material film pattern
`covering an internal base region prospective por-
`tion, the first mask material film pattern having a
`step at its end portion with respect to a surrounding
`wafer surface;
`(0) depositing a conductive material on the surface to
`cover the first mask material film pattern, thereby
`forming a first conductive film to be used as a part
`of a base electrode, the surface of the first conduc-
`tive film having a recess at a position spaced apart
`
`4
`from a side end of the first mask material film pat-
`tern in a transverse direction by a distance corre-
`sponding to the film thickness of the first conduc-
`tive film;
`(d) burying a second mask material film pattern in the
`recess of the first conductive film surface;
`(e) selectively etching the first conductive film using
`the second mask material film pattern as an etching
`mask to expose the first mask material film pattern;
`(0 continuously, selectively etching the first conduc-
`tive film by etching using the exposed first mask
`material film pattern and the second mask material
`film pattern as etching masks, thereby forming a
`first opening for forming an external base region
`between the two mask material film patterns;
`(g) removing the second mask material film pattern;
`(h) burying a second conductive film serving as a part
`of a base electrode in the first opening, while dop-
`ing an impurity of a second conductivity type into
`the wafer through the first opening to form the
`external base region of the second conductivity
`tYPe;
`(i) removing the first mask material film pattern to
`form a second opening for forming an internal base
`region;
`0) forming a thermal oxide film on the surface of the
`second conductive film;
`(k) doping an impurity of the second conductivity
`type into the wafer through the second opening to
`form the internal base region of the second conduc-
`tivity type; and
`(1) doping an impurity of the first conductivity type
`into the wafer through the second opening.
`According to the method of the present invention,
`the emitter region and'the internal base region are deter-
`mined by the first mask material film pattern formed in
`the element region, and the external base region is deter-
`mined by the first opening. The first opening is defined
`by the first mask material film pattern and the second
`mask material film pattern. A distance between the
`patterns is defined by the film thickness of the first
`conductive film. Therefore, the external and internal
`base regions are formed completely by self alignment
`with respect to the emitter region.
`Furthermore, a step of forming an overhang and
`burying a polycrystalline silicon film therebelow, which
`is difficult to be controlled, is not necessary. Therefore,
`size accuracy with small variations can be obtained.
`Moreover, the width of the external base region can be
`easily and accurately controlled by selecting the film
`thickness of the first conductive film. Therefore, ac-
`cording to the present invention, a high-performance
`bipolar transistor can be obtained.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIGS. 1A to ID are sectional views showing a con-
`ventional method of manufacturing a bipolar transistor;
`FIGS. 2A to 2D are sectional views showing another
`conventional method of manufacturing a bipolar tran-
`sistor;
`FIGS. 3A to 3H are sectional views for explaining an
`embodiment of a method of manufacturing a bipolar
`transistor according to the present invention;
`FIGS. 4 and 5 are sectional views for explaining
`other embodiments of the present invention, respec-
`tively;
`
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`5
`FIGS. 6A and 6B and FIGS. 7A and 7B are sectional
`views for explaining other embodiments of the present
`invention, respectively; and
`FIGS. 8A to SJ are sectional views for explaining a
`preferred embodiment of the present invention.
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`
`FIGS. 3A to 3H are sectional views showing manu-
`facturing steps of a bipolar transistor according to an
`embodiment of the present invention.
`In this embodiment, as shown in FIG. 3A, n+-type
`buried region 2 is formed on p-type Si substrate 1, and
`n-type epitaxial layer 3 serving as a collector region is
`formed thereon. Layer 3 is formed as an n-type layer
`having
`an
`impurity
`concentration
`of
`IX 1016
`atoms/cm3 by a vapor growth method. Subsequently, a
`groove is formed in an element isolation region of this
`wafer, and a groove is formed in the element isolation
`region between a base emitter region and a collector
`contact region. Thereafter, selective oxidation is per-
`formed to form element isolating oxide film 4 and elec—
`trode isolating oxide film 5 in the groove. Note that the
`collector contact region is not shown. Oxide film 6
`having a thickness of about 200 A is formed on the
`entire surface of the element-isolated wafer by thermal
`oxidation. Then, silicon nitride film 7 is deposited as an
`anti-oxidation insulating film to a thickness of about
`1,000 A, and a CVD oxide film 8is deposited as a first
`mask material film to a thickness of about 5,000 A. The
`CVD oxide film is patterned by photolithography so
`that oxide film patterns 81 to 83 remain on an internal
`base region prospective portion and the element isola-
`tion region (FIG. 3A). At this time, patterning is per-
`formed by reactive ion etching (RIE) such that thick
`oxide film patterns 81 to 83 has substantially vertical side
`walls.
`Then, first—polycrystalline silicon film 9 is deposited
`as a first copductive film. The thickness of film 9 is
`about 3,500 A. Subsequently, a photoresist is coated on
`the entire surface as a second mask material film, and
`the surface is flattened. Thereafter, the resultant struc-
`ture is etched back in an 02 plasma atmosphere, thereby
`exposing the surface of film 9 formed on film 8. That is,
`as shown in FIG. 3B, photoresist pattern 10 is buried in
`a recess of film 9.
`Then, film 9 is etched using pattern 10 as a mask by
`RIE. After patterns 81 to 83 are exposed, these oxide
`film patterns are also used as a mask together with pat-
`tern 10. In this manner, film 9 is continuously etched
`until it remains below only pattern 10. In addition, ex-
`posed film 7 is etched. This etching is performed by
`RIE so as not to form an overhang. When film 7 is
`etched to expose film 6, film 6 is etched using an aque~
`ous NH4F solution to expose the wafer surface. In this
`manner, first opening A for forming an external base
`region is formed (FIG. 3C). Note that the wafer surface
`may be exposed by etching using RIE. In either case, a
`sufficient etching selection ratio of film 6 and layer 3
`can be obtained, the wafer is not damaged.
`Then, as shown in FIG. 3D, pattern 10 is removed.
`Subsequently, second polycrystalline silicon film 11 is
`deposited as a second conductive film to a thickness of
`about 6,000 A and then etched back. In this manner, as
`shownin FIG. 3E film 11IS buriedin opening A while
`the surface of film 8 is exposed. In addition, the surfaces
`of residual films 9 and 11 are flattened. The film thick-
`ness of film 11 need only be half or more the width of
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`6
`opening A. However, in order to obtain practical flat-
`ness, film 11 preferably has the film thickness 1.5 times
`the width of opening A.
`Then, ion implantation is performed to dope boron in
`film 11. In this case, boron may be doped not only in
`film 11 but also in film 9. Ion implantation conditions of
`the boron are given as an acceleration voltage of 50 keV
`and a dose of 1><1015ions/cm2
`Then, CVD oxide film 81 on an emitter formation
`region is selectively removed by photolithography to
`form second opening B for forming an internal base
`region, as shown in FIG. 3F. Subsequently, the resul-
`tant structure is thermally oxidized using exposed film 7
`as a mask to form oxide film 13 on the surface of films
`9 and 11, as shown in FIG. 3G. In this case, thermal
`oxidation is wet oxidation performed at a temperature
`of 800° to 950°, and film 13 having a thickness of about
`3,000 AIS formed on the upper and side surfaces of the
`polycrystalline silicon film. As a result, a contact width
`between film 11 and the wafer becomes about 2,000 A.
`In this thermal oxidation step, the boron dopedin film
`11 is diffused into the wafer to form p-type external base
`region 12. If necessary, annealing may be performed in
`an inert atmosphere such as an N2 gas atmosphere in
`addition to a thermal oxidation step, thereby controlling
`a diffusion depth and a impurity concentration of the
`p-type external base region.
`Thereafter, film 7 in opening B is removed by plasma
`etching, and film 6 below film 7 is removed by an aque-
`ous NH4F solution, thereby exposing the wafer surface»
`in openingB. A thin oxide film having a thickness of
`about 250 Ais formed on the wafer surface exposed1n
`opening B by thermal oxidation. Then, boron is ion—
`implanted under the conditions of an acceleration volt-
`age of 15 keV and a dose of 5x1013 ions/cmz, thereby
`forming p-type internal base region 14. Subsequently,
`the oxide film in opening B is removed, and third poly-
`crystalline silicon film 15 is deposited as a third conduc-
`tive film so as to cover the opening portion. Arsenic is
`ion-implanted in film 15 under the conditions of an
`acceleration voltage of 50 keV and a dose of 1X10l6
`ions/cmz, and then film 15 is patterned into a shape
`required as an emitter electrode. Thereafter, the resul-
`tant structure is annealed to diffuse the arsenic con-
`tained in film 15 into the wafer, thereby forming n-type
`emitter layer 16' (FIG. 3H).
`Thereafter, although not shown, a base contact hole
`for films 9 and 11 is formed in oxide film 13, and A1
`wiring of an emitter, a base, and a collector is formed,
`thereby completing the transistor.
`According to the above embodiment, CVD oxide
`film pattern 81 formed in the element region is used to
`form the external base layer having the predetermined
`width by self alignment around pattern 81. In addition,
`the internal base region and the emitter region are se-
`quentially formed by self alignment
`in regions from
`which pattern 81 is removed. That is, these impurity
`regions are formed completely by self alignment. Espe-
`cially, first opening A for forming the external base
`region is formed so as to have a width corresponding to
`the film thickness of first polycrystalline silicon film 9.
`Therefore, controllability of the present
`invention is
`better than that‘of the conventional method which uti-
`lizes an overhang as shown in FIGS. 1A to 1D. That is,
`by changing the film thickness of film 9, the width of
`the external base region can be easily changed.
`In the above embodiment, boron is ion-implanted in
`second polycrystalline silicon film 11, and external base
`
`

`

`7
`layer 12 is formed using film 11 as a diffusion source.
`However, such solid-phase diffusion need not be per-
`formed. For example, boron may be ion-implanted di-
`rectly in the wafer in the state of FIG. 3C or 3D to form
`the external base layer. In this case, an impurity concen-
`tration can be increased, and therefore a resistance of
`the external base region can be reduced.
`In addition,
`in the above embodiment, the internal
`base region is formed by etching nitride film 7 and oxide
`film 6 and forming a thin thermal oxide film. However, 10
`the internal base region may be formed by ion implanta-
`tion when film 7 is removed or when film 6 is removed.
`Furthermore, in the above embodiment, emitter re-
`gion 16 is formed by solid-phase diffusion from third
`polycrystalline silicon film 15. However, region 16 may
`be formed by ion implantation. In this case, the oxide
`film used as a buffer layer to perform internal base re«
`gion 14 by ion implantation may be directly used as a
`buffer layer to perform ion implantation for forming the
`emitter region therethrough. Alternatively, this oxide
`film may be removed to perform ion implantation.
`Moreover, by adjusting an acceleration voltage of ion
`implantation,
`ion implantation can be performed
`through third polycrystalline silicon film 15 for an emit-
`ter electrode.
`
`15
`
`.0
`
`Referring to FIGS. 4 to 7B, other embodiments of the
`present invention will be described.
`FIG. 4 shows another embodiment in which photore-
`sist pattern 10 is buried preferably in a recess of first
`polycrystalline silicon film 9 if the recess is wide. When
`the recess of film 9 is wide, it is not easy to flatten the
`surface even if a photoresist is coated thereon. In this
`case, as shown in FIG. 4, auxiliary photoresist pattern
`101 is formedjn advance in the wide (e.g., 3-um wide or 35
`more) recess by normal photolithography. When an
`actual width of the recess is narrowed in this manner,
`the entire surface can be easily flattened by coating
`photoresist 102 thereon.
`Note that in either of the embodiments shown in 40
`FIGS. 3A to 3H and FIG. 4,
`ion implantation with
`respect to the photoresist film is effective. This is be-
`cause the photoresist film is hardened by ion implanta-
`tion, and an anti-etching property required for an etch-
`ing mask is improved. Note that an ion seed used for this 45
`purpose is not limited. Examples of the ion seed are B+,
`P+, As+, and Ar+
`FIG. 5 shows still another embodiment in which the
`width of an emitter region is reduced. For example, in
`order to increase an emitter breakdown voltage, a rela- 50
`tionship between an external base region size and an
`emitter region size must be sometimes controlled. In
`order to reduce an emitter junction capacitance or to
`suppress an emitter-clouding effect,
`the width of an
`emitter region must be sometimes reduced. This em- 55
`bodiment is effective in these cases. In this embodiment,
`after internal base region 14 is formed, polycrystalline
`silicon film 17 is selectively left on side walls of second
`opening B to narrow the opening. This state is obtained
`by depositing a polycrystalline silicon film having a 60
`predetermined thickness and etching the entire surface
`by RIE, after performing ion implantation for forming
`region 14. If necessary, the polycrystalline silicon film
`and a CVD oxide film are stacked, and these stacked
`films are left on the side wall of opening B. In this case, 65
`a smaller opening for emitter diffusion is obtained. In
`addition, if a material having a small specific dielectric
`constant is selected as a material to be left on the side
`
`4,908,324
`
`5
`
`8
`wall of the second opening, an emitter-base stray capac-
`itor can be reduced.
`FIGS. 6A and 6B show still another embodiment in
`which a degree of freedom for controlling the width of
`an external base region is improved. In this embodi-
`ment, after first polycrystalline silicon film 9 is depos-
`ited on the entire surface as in the embodiment shown in
`FIGS. 3A to 3H, spacer film 18 consisting of a CVD
`oxide film is formed on side walls of the step of film 9 as
`shown in FIG. 6A. Film 18 is formed by depositing the
`CVD oxide film on the entire surface and etching-back
`the film by RIE.
`Thereafter, first opening A for forming an external
`base region is formed as follows. First, as in the embodi-
`ment shown in FIGS. 3A to 3H, photoresist 10 is buried
`in a recess. CVD oxide film 18 is etched and removed
`by an aqueous NH4F solution using photoresist 10 as a
`mask. Then, polycrystalline silicon film 9 is etched by
`RIE using photoresist 10 and CVD oxide film 8. Subse-
`quently, nitride film 7 and oxide film 6 are sequentially
`etched in the same manner as in the embodiment of
`FIGS. 3A to 3H, thereby forming first opening A for
`forming an external base (FIG. 6B).
`As described above,
`in the embodiment shown in
`FIGS. 6A and 6B, the width of first opening A (i.e., the
`width of the external base region) is determined by a
`sum of the film thickness of first polycrystalline silicon
`film 9 and that of spacer film 18. Therefore, if necessary,
`the width of the external base region can be arbitrarily
`set without depending on the film thickness of film 9.
`Note that in addition to the CVD oxide film, various
`films can be used as film 18.
`In the above embodiments, the polycrystalline silicon
`film is used as the first to third conductive films. How-
`ever, if the films are not used as a solid-phase diffusion
`source of an impurity, other conductive materials may
`be used. In this case, however, a material for the second
`conductive film is selected such that a thermal oxide
`film can be formed on the surface thereof. Examples of
`the material capable of forming a thermal oxide film are
`refractory metal silicides such as molybdenum silicide,
`tungsten silicide, and tantalum silicide. As the first con-
`ductive film, a refractory metal film of molybdenum or
`tantalum not capable of forming a good thermal oxide
`film can also be used.
`FIGS. 7A and 7B show an embodiment in which the
`above refractory metal film is used as the first conduc~
`tive film instead of the polycrystalline silicon film. A
`state shown in FIG. 7A (corresponding to FIG. 3E) is
`obtained in the same as in the embodiment of FIGS. 3A
`to 3H except that the refractory metal film is used as
`described above. As shown in FIG. 7A, the surface is
`flattened while refractory metal film 19 serving as the
`first conductive film is covered with polycrystalline
`silicon film 11 serving as the second conductive film.
`Thereafter, a bipolar transistor shown in FIG. 7B is
`obtained in the same manner as in the embodiment of
`FIGS. 3A to 3H.
`The bipolar transistor obtained in the embodiment of
`FIGS. 7A and 7B has the following specific advantages.
`That is, since the refractory metal having a small resis-
`tivity is used as a base electrode, a base resistance can be
`sufficiently reduced, and a high-speed operation can be
`achieved. In addition, since a contact with external base
`region 12 is formed through second polycrystalline
`silicon film 11, junction breakdown caused by electro-
`migration of the refractory metal can be prevented.
`
`

`

`4,908,324
`
`9
`However, all the above embodiments have the fol-
`lowing problem.
`That is, as shown in FIG. 3F, polycrystalline silicon
`film 11 is in direct contact with nitride film 7. There
`fore, i