(12) United States Patent
`US 6,924,237 B2
`(10) Patent N0.:
`
` Ootsuka et al. (45) Date of Patent: Aug. 2, 2005
`
`
`USOO6924237B2
`
`(54) METHOD FOR MANUFACTURING
`SEMICONDUCTOR INTEGRATED CIRCUIT
`DEVICE
`
`(75)
`
`Inventors: Fumio Ootsuka, Tokorozawa (JP);
`Satoshi Yamamoto, Ome (JP); Satoshi
`Sakai, Yokohama (JP)
`
`6,210,999 B1 *
`6,380,589 B1 *
`
`............. 438/183
`4/2001 Gardner et a1.
`4/2002 Krivokapic ................. 257/347
`
`OTHER PUBLICATIONS
`
`D.A. Buchanan, et al., “80 nm poly—silicon gated n—FETs
`With ultra—thin A1203 gate dielectric for ULSI applications”.
`
`(73) Assignee: Renesas Technology Corp., Tokyo (JP)
`
`* cited by examiner
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U-S-C- 154(b) by 281 days.
`
`21 A l. N .: 10 281 189
`)
`pp
`0
`/
`’
`(
`(22)
`Filed:
`Oct. 28, 2002
`_
`.
`_
`Pr10r Publlcatlon Data
`US 2003/0096501 A1 May 22, 2003
`
`(65)
`
`(30)
`
`Foreign Application Priority Data
`
`....................................... 2001—355053
`(JP)
`NOV. 20, 2001
`(51)
`Int. Cl.7 .............................................. H01L 21/302
`(52) US. Cl.
`....................... 438/696; 438/303; 438/305;
`438/585; 438/591; 438/589; 438/595
`(58) Field of Search ................................. 438/303; 305;
`438/585; 591; 589, 595, 696
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`Primary Examiner—George A. Goudreau
`(74) Attorney, Agent, or Firm—Antonclli, Tcrry, Stout &
`Kraus, LLP
`(57)
`
`ABSTRACT
`.
`.
`.
`.
`.
`A method ls used to form a c1rcu1t to ach1eve a high-speed
`performance and a circuit to attain a high reliability on one
`andthe samesubstrate, in a semiconductor integrated circuit
`deV1ce contammg MIS tran51stors, 1n Wh1ch the gate msu-
`lating film is made of a high dielectric constant insulating
`film. In the method, the high dielectric constant insulating
`film is removed on the diffusion regions of the MIS tran-
`sistors in the logic region and I/O region, and silicide layers
`of a low resistance are formed on the surfaces of the
`diffusion regions. In the memory region, on the other hand,
`the silicide layers are not formed on the diffusion regions of
`the MIS transistors, and the diffusion regions are covered
`With the high dielectric constant insulating film, thereby
`preventing damage to the semiconductor substrate during
`forming of the spacers, silicide layers, and contact holes.
`
`6,159,782 A * 12/2000 Xiang et al.
`
`................ 438/197
`
`20 Claims, 11 Drawing Sheets
`
`
`
`IP Bridge Exhibit 2217
`IP Bridge Exhibit 2217
`TSMC v. Godo Kaisha IP Bridge 1
`TSMC V. Godo Kaisha IP Bridge 1
`IPR2017-01843
`IPR2017-01843
`
`

`

`US. Patent
`
`Aug. 2, 2005
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`US 6,924,237 B2
`
`1
`METHOD FOR MANUFACTURING
`SEMICONDUCTOR INTEGRATED CIRCUIT
`DEVICE
`
`BACKGROUND OF THE INVENTION
`
`The present invention relates to a technique for use in the
`manufacture of a semiconductor integrated circuit device;
`and more specifically, the invention relates to a technique
`that is effective for application to a semiconductor integrated
`circuit device including a short channel MIS (metal insulator
`semiconductor) having a gate length, i.e. the width of the
`gate electrode, which is less than 0.1 pm.
`The film thickness of the gate insulating film in a MIS
`transistor having a gate length which is less than 0.07 ,um is
`presumed to be less than 1.2 nm. However,
`thinning a
`conventionally used silicon oxide film for use in the gate
`insulating film will cause the leakage current to exceed 10
`A/cm2, which involves an increase in the standby current,
`thereby creating a problem.
`Accordingly, a trial has been conducted using an insulat-
`ing film having a comparably high relative dielectric con-
`stant (hereunder referred to as a high dielectric constant
`insulating film), for example, an alumina film having a
`relative dielectric constant which is about 7 to 11 for the gate
`insulating film, and in which the effective film thickness is
`reduced while maintaining the physical film thickness at 1.5
`nm or more. Here, the effective film thickness signifies an
`equivalent silicon oxide film thickness in consideration of
`the relative dielectric constant.
`
`As an example, the publication IEDM (International Elec-
`tron Device Meetings in an article entitled “80 nm poly-
`silicon gated n-FETs with ultra-thin A1203 gate dielectric
`for ULSI applications” at pp. 223—226, 2000) discloses the
`performance characteristic of a MIS transistor having a gate
`insulating film made of an alumina film, with a gate length
`of less than 0.1 pm.
`
`SUMMARY OF THE INVENTION
`
`As the integration of semiconductor devices increases, the
`MIS transistor is being made still finer according to the
`scaling law; and, accompanied with this, the resistances of
`the gate, source, and drain regions increase, thus leading to
`a problem in that the micro-structuring of the MIS transistor
`does not provide a high-speed performance. And, in the MIS
`transistor having a gate length of less than 0.2 pm, for
`example, a high-speed performance has been pursued by
`silicifying the conductive film forming the gate, as well as
`the semiconductor regions forming the sources and drains.
`For example,
`in order to form silicide layers on the
`surfaces of the semiconductor regions forming sources and
`drains, a method is employed which removes an insulating
`film on the same layer as a gate insulating film on the
`substrate, for example, by reactive etching, and, thereafter,
`forms silicide layers of a low resistance on the surfaces of
`the semiconductor regions forming sources and drains by
`use of a self-aligning method. The above-mentioned reactive
`etching is one example of dry etching techniques typically
`used in a semiconductor manufacturing process, in which
`etching through a chemical reaction is performed by utiliz-
`ing a chemically active excited activator. This technique will
`restrain etching damage so as to achieve a comparably high
`etching selection ratio.
`However, the inventor of this invention has examined the
`technique used in the manufacture of a MIS device using a
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`high dielectric constant insulating film for the gate insulating
`film, and it was confirmed clearly that with the reactive
`etching, it is difficult to remove the high dielectric constant
`insulating film, and this leads to an impossibility of silici-
`fying the semiconductor regions forming sources and drains.
`As a means to solve the above problem that hinders
`manufacturing a high-speed MIS device, the technique of
`sputter etching has been examined for use in physically
`removing a high dielectric constant insulating film on the
`semiconductor regions forming sources and drains. The
`result shows that sputter etching is likely to damage the
`substrate, and,
`thereby,
`this invites the lowering of the
`reliability of the MIS transistor. As an example, applying
`sputter etching to memory cells tends to create a problem
`that increased junction leakage currents and retention data
`errors, and so forth, are caused.
`An object of the present invention is to provide a tech-
`nique that makes it possible to form a circuit to accomplish
`a high-speed performance and a circuit to attain a high
`reliability on one and the same substrate, in a semiconductor
`integrated circuit device having plural
`types of M18
`transistors, in which the gate insulating film is made of a
`high dielectric constant insulating film.
`The above and other objects and novel features of the
`invention will become apparent from the following descrip-
`tions and the accompanying drawings.
`The typical aspects of the invention disclosed in this
`application will be summarized as follows.
`(1) The method of manufacture of a semiconductor inte-
`grated circuit device includes the steps of: preparing a
`semiconductor substrate of a first conductive type,
`having a first region and a second region on a surface
`thereof; forming plural trenches on the surface of the
`semiconductor substrate in the first region and the
`second region, and forming a first insulating film inside
`the plural trenches; forming a second insulating film
`having a relative dielectric constant that is higher than
`that of the first insulating film on the surface of the
`semiconductor substrate in the first region and the
`second region; forming a first conductive piece on the
`second insulating film in the first region, and forming
`a second conductive piece on the second insulating film
`in the second region; introducing first impurities of a
`second conductive type opposite to the first conductive
`type into the surface of the semiconductor substrate, in
`a region of both ends of the first conductive piece and
`a region of both ends of the second conductive piece;
`removing the second insulating film, except at least a
`lower layer of the first conductive piece and the second
`region; depositing a high melting point metal film to
`overlie the semiconductor substrate; and selectively
`forming a silicide layer in a region between the first
`conductive piece on the surface of the semiconductor
`substrate and the first insulating film, in the first region.
`(2) The method of manufacture of a semiconductor inte-
`grated circuit device further includes, in addition to the
`steps included in the above-described manufacturing
`method (1), the steps of: depositing a third insulating
`film in the first and second regions; applying etching to
`the third insulating film to form a first contact hole in
`a region between the first conductive piece and the first
`insulating film, in the first region; applying etching to
`the third insulating film to form a second contact hole
`in a region between the second conductive piece and
`the first
`insulating film,
`in the second region; and
`forming a third conductive piece in the first contact
`
`

`

`US 6,924,237 B2
`
`3
`hole, and a fourth conductive piece in the second
`contact hole, in which the distance between the first
`conductive piece and the first insulating film in the first
`region is larger than the distance between the second
`conductive piece and the first insulating film in the
`second region.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a block diagram of a semiconductor integrated
`circuit device representing one embodiment of the inven-
`tion;
`FIG. 2 is an equivalent circuit diagram of a DRAM cell
`formed in a memory region;
`FIG. 3 is an equivalent circuit diagram of a SRAM cell
`formed in a memory region;
`FIG. 4 is a sectional view of a major part of the semi-
`conductor substrate, which illustrates an n-channel MIS
`transistor formed in a memory region;
`FIG. 5 is a sectional view of a major part of the semi-
`conductor substrate, which illustrates the n-channel MIS
`transistor formed in a logic region;
`FIG. 6 is a sectional view of a major part of the semi-
`conductor substrate, which illustrates the n-channel MIS
`transistor formed in an I/O region;
`FIG. 7 is a sectional view of a major part of the semi-
`conductor substrate, which illustrates the n-channel MIS
`transistor forming a capacitance element;
`FIG. 8 is a sectional view of a major part of the semi-
`conductor substrate, which illustrates a step in a method of
`manufacturing the semiconductor integrated circuit device
`according to one embodiment of the invention;
`FIG. 9 is a sectional view of a major part of the semi-
`conductor substrate, which illustrates a step in the method of
`manufacturing the semiconductor integrated circuit device
`according to the one embodiment of the invention;
`FIG. 10 is a sectional view of a major part of the
`semiconductor substrate, which illustrates a step in the
`method of manufacturing the semiconductor integrated cir-
`cuit device according to the one embodiment of the inven-
`tion;
`FIG. 11 is a sectional view of a major part of the
`semiconductor substrate, which illustrates a step in the
`method of manufacturing the semiconductor integrated cir-
`cuit device according to the one embodiment of the inven-
`tion;
`FIG. 12 is a sectional view of a major part of the
`semiconductor substrate, which illustrates a step in the
`method of manufacturing the semiconductor integrated cir-
`cuit device according to the one embodiment of the inven-
`tion;
`FIG. 13 is a sectional view of a major part of the
`semiconductor substrate, which illustrates a step in the
`method of manufacturing the semiconductor integrated cir-
`cuit device according to the one embodiment of the inven-
`tion;
`FIG. 14 is a sectional view of a major part of the
`semiconductor substrate, which illustrates a step in the
`method of manufacturing the semiconductor integrated cir-
`cuit device according to the one embodiment of the inven-
`tion;
`FIG. 15 is a sectional view of a major part of the
`semiconductor substrate, which illustrates a step in the
`method of manufacturing the semiconductor integrated cir-
`cuit device according to the one embodiment of the inven-
`tion;
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`FIG. 16 is a sectional view of a major part of the
`semiconductor substrate, which illustrates a step in the
`method of manufacturing the semiconductor integrated cir-
`cuit device according to the one embodiment of the inven-
`tion;
`FIG. 17 is a sectional view of a major part of the
`semiconductor substrate, which illustrates a step in the
`method of manufacturing the semiconductor integrated cir-
`cuit device according to the one embodiment of the inven-
`tion;
`FIG. 18 is a sectional view of a major part of the
`semiconductor substrate, which illustrates a step in the
`method of manufacturing the semiconductor integrated cir-
`cuit device according to the one embodiment of the inven-
`tion;
`FIG. 19 is a sectional view of a major part of the
`semiconductor substrate, which illustrates a step in the
`method of manufacturing the semiconductor integrated cir-
`cuit device according to the one embodiment of the inven-
`tion;
`FIG. 20 is a sectional view of a major part of the
`semiconductor substrate, which illustrates a step in the
`method of manufacturing a semiconductor integrated circuit
`device according to a second embodiment of the invention;
`FIG. 21 is a sectional view of a major part of the
`semiconductor substrate, which illustrates a step in the
`method of manufacturing the semiconductor integrated cir-
`cuit device according to the second embodiment of the
`invention; and
`FIG. 22 is a sectional view of a major part of the
`semiconductor substrate, illustrating an n-channel MIS tran-
`sistor formed in a memory region, according to a third
`embodiment of the invention.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`
`The embodiments of the invention will be described in
`
`detail with reference to the accompanying drawings. In all
`the drawings, those members having the same functions are
`identified by the same symbols, and repetitive descriptions
`thereof will be omitted.
`
`Embodiment 1
`
`FIG. 1 is a block diagram showing one example of the
`semiconductor integrated circuit device according to one
`embodiment of the invention. First, a general outline of the
`construction of the semiconductor integrated circuit device
`of the embodiment 1 will be described with reference to the
`
`drawing.
`The semiconductor integrated circuit device is roughly
`divided into a memory region, logic region, and I/O (Input/
`Output interface) region.
`The memory region A1 has 2N+M memory cells MC (or,
`simply cells) arrayed, each of which memorizes,
`for
`example, one bit of binary information, so that the memory
`region A1 is capable of memorizing 2N+M bits of informa-
`tion. The memory cells MC are arrayed two-dimensionally
`in a matrix structure, among which a memory cell MC is
`accessed by enabling each one of the selection lines L1, L2
`in the row and column directions to select the memory cell
`MC lying at
`the intersection thereof. Assuming that the
`number of selection lines L1 in the row direction is 2N and
`the number of the selection lines L2 in the column direction
`is 2M, the number of the circuits to drive the memory cells
`is 2N+2M. The memory region A1 is called a memory cell
`
`

`

`US 6,924,237 B2
`
`5
`array, a memory matrix, a memory array, or simply an array.
`And, the selection line L1 in the row direction is called a row
`line, X line, or word line; while, the selection line L2 in the
`column direction is called a column line, Y line, or data line.
`The logic region A2 is an associated circuit block that
`controls the memory region Al on the basis of the control
`signals or data supplied to the I/O region A3, and it
`exchanges data with the memory region Al. One of the
`typical circuit blocks is a decoder, for example. The decod-
`ers constitute a logic circuit group that receives N pairs and
`M pairs of address signals from the address buffers inside the
`I/O region A3, and selects one row line among the 2N row
`lines and one column line among 2M column lines. The
`drivers connected to the outputs of individual decoders drive
`the row lines and the column lines. It also includes an I/O
`control circuit that controls the exchange of data, and so
`forth.
`
`The I/O region A3 is a circuit block that converts the
`control signals and the write data inputted from the outside
`into internal signals and operates to transfer the results to the
`logic region A2, and it outputs to the outside the read data
`that is taken out to the logic region A2 from the memory
`region Al. One of the typical circuit blocks is an address
`buffer, for example. The address buffers are circuits that
`receive (N+M) address input signals for appointing cell
`selection addresses inside the memory region A1, and they
`generate N pairs and M pairs of internal address signals. It
`also includes a data I/O circuit, write control circuit or
`control block circuit, and so forth.
`Next, a memory cell arranged in the memory region A1
`will be described as an example. FIG. 2 illustrates an
`equivalent circuit of a memory cell of a DRAM (Dynamic
`Random Access Memory); while, FIG. 3 illustrates an
`equivalent circuit of a memory cell of a SRAM (Static
`Random Access Memory). In addition to these, memory
`cells can be cited which constitute a logic consolidated
`memory having memory circuits and logic circuits formed
`on one substrate, and a nonvolatile memory, etc., however,
`the explanations of these will be omitted.
`As shown in FIG. 2, a DRAM cell is composed of a MIS
`transistor Q that performs as a switch, and a capacitor C that
`stores information in the form of a charge. The DRAM cell
`stores information on the basis of whether the capacitor C
`holds a charge or not, that is, whether the terminal voltage
`across the capacitor C is high or low, in correspondence with
`the binary information “1”, “0”. A data write operation
`involves the applying of a voltage corresponding to the data
`from the outside to the cell. A data read operation involves
`taking out information indicating whether the capacitor C
`holds a charge or not to the outside of the cell, in corre-
`spondence with the high or low level of the voltage, and
`checking the information.
`As shown in FIG. 3, a SRAM cell is composed of a
`flip-flop circuit that operates to store data and two transfer
`MIS transistors Qt. By applying a voltage to the word line
`WL to turn on the transfer MIS transistors Qt, data is
`exchanged between the data line pair D, /D and the flip-flop
`circuit. The flip-flop circuit is configured with two inverters,
`such that the input of one inverter is connected to the output
`of the other inverter, and the output of the one is connected
`to the input of the other. The inverters are made up of load
`elements Lo and drive MIS transistors Qd. The load element
`Lo can be a MIS transistor or a resistance element, for
`example, a polycrystalline silicon film.
`During data writing, the high voltage (H) is applied to one
`of the data line pair D, /D, and the low voltage (L) is applied
`
`6
`to the other to supply these voltages to a pair of nodes N1,
`N2. The two combinations of these voltages to be given (D,
`/D are given H, L or L, H, respectively) are associated with
`the binary write data. The data reading is performed by
`detecting the voltages appearing on the data line pair D, /D
`in correspondence with the combinations of the high and
`low levels of the voltages at the nodes N1, N2.
`Next, an example of the semiconductor integrated circuit
`device representing the embodiment 1 will be described with
`reference to sectional views of a major part of the semicon-
`ductor substrate, as illustrated in FIG. 4 through FIG. 7. FIG.
`4 illustrates an n-channel MIS transistor formed in the
`
`memory region; FIG. 5 illustrates the n-channel MIS tran-
`sistor formed in the logic region; FIG. 6 illustrates the
`n-channel MIS transistor formed in the I/O region; and FIG.
`7 illustrates the n-channel MIS transistor forming a capaci-
`tance element.
`
`First, an n-channel MIS transistor Q1 formed in the
`memory region will be described with reference to FIG. 4.
`As an example, the n-channel MIS transistor Q1 can be
`identified as the selection MIS transistor Q which forms a
`constituent element of the DRAM cell mentioned with
`reference to FIG. 2, and the transfer MIS transistor Qt and
`the drive MIS transistor Qd which form constituents of the
`SRAM cell mentioned with reference to FIG. 3. The thresh-
`
`is
`old voltage (Vth) of the n-channel MIS transistor Q,
`comparably high, which can be regarded as, for example,
`about 0.4 Volt. In case of using two kinds of supply voltages,
`for example,
`the operation voltage (Vcc) applied to the
`n-channel MIS transistor Q1 is a low voltage, which can be
`set to, for example, about 0.85 Volt.
`The n-channel MIS transistor Q, is formed in an active
`region that is surrounded by device isolation sections formed
`on a p-type semiconductor substrate 1. The device isolation
`sections are made up of shallow trenches 2 formed on the
`semiconductor substrate 1, and a silicon oxide film 3 embed-
`ded therein. On the surface of the semiconductor substrate 1,
`a pair of n-type semiconductor regions 12 forms the source
`and the drain.
`
`A gate insulating film 8, that is formed of a high dielectric
`constant insulating film 7, is formed on the semiconductor
`substrate 1, on which there is a gate electrode (conductive
`piece) 11 formed of a polycrystalline silicon film 10. The
`high dielectric constant
`insulating film 7 is formed on
`substantially the whole surface of the active regions and the
`device isolation sections overlying the semiconductor sub-
`strate 1. A spacer (sidewall insulating film) 13, that is made
`of, for example, a silicon oxide film, is formed on the
`sidewall of the gate electrode 11, and a silicide layer 14 is
`formed on the gate electrode 11.
`To cover substantially the whole surface of the semicon-
`ductor substrate 1, a SAC (self-aligned contact) insulating
`film 15 and an interlayer insulating film 16 are formed in
`order from the lower layer. The SAC insulating film 15 can
`be made of, for example, a silicon nitride film; and, the
`interlayer insulating film 16 can be made of, for example, a
`silicon oxide film. The SAC insulating film 15 functions as
`an etching stopper layer for the interlayer insulating film 16.
`However, in case the high dielectric constant insulating
`film 7 can be used as an etching stopper layer for the
`interlayer insulating film 16, it is not necessary to form the
`SAC insulating film 15.
`Contact holes 17a are formed through the interlayer
`insulating film 16,
`the insulating film 15, and the high
`dielectric constant insulating film 7 on the same layer as the
`gate insulating film 8, so as to reach a pair of the n-type
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`US 6,924,237 B2
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`7
`semiconductor regions 12. Wires 19 are connected to a pair
`of the n-type semiconductor regions 12 through plugs
`(conductive pieces) 18 buried in the contact holes 1701. For
`the shape of the hole used to bury the plug 18, a circular
`contact hole is preferred, because of the necessity of reduc-
`ing the parasitic capacitance. However, a slot shape may be
`adopted, which is formed so as to bridge the n-type semi-
`conductor regions 12 forming the source and the drain and
`the device isolation sections. In this case, conductive films
`to be buried in this slot can also be used as local wirings.
`Next, an n-channel MIS transistor 02 that is formed in the
`logic region will be described with reference to FIG. 5. The
`threshold voltage (Vth) of the n-channel MIS transistor O2
`is comparably low, which can be regarded as, for example,
`about 0.1 Volt. In case of using two kinds of supply voltages,
`for example,
`the operation voltage (Vcc) applied to the
`n-channel MIS transistor O2 is a low voltage, which can be
`set to, for example, about 0.85 Volt.
`The n-channel MIS transistor O2 is formed, in the same
`manner as the n-channel MIS transistor Q1, in the active
`region surrounded by the device isolation sections formed
`on the p-type semiconductor substrate 1. On the surface of
`the semiconductor substrate 1, a pair of the n-type semicon-
`ductor regions 12 forms the source and the drain. Further, the
`gate insulating film 8, that is formed of the high dielectric
`constant insulating film 7, is formed on the semiconductor
`substrate 1, on which the gate electrode 11 formed of the
`polycrystalline silicon film 10 is formed. The spacer 13 and
`the silicide layer 14 are formed on the sidewall and on the
`upper surface of the gate electrode 11, respectively.
`However, the high dielectric constant insulating film 7 is
`formed only in a region surrounded by the gate electrode 11,
`the spacer 13, and the semiconductor substrate 1, which
`makes up the gate insulating film 8. The silicide layers 14 for
`lowering the resistance are formed on a pair of the n-type
`semiconductor regions 12.
`To cover substantially the whole surface of the semicon-
`ductor substrate 1,
`the SAC insulating film 15 and the
`interlayer insulating film 16 are formed in order from the
`lower layer. Contact holes 17 are formed through the inter-
`layer insulating film 16 and the insulating film 15 so as to
`reach the silicide layers 14 on a pair of the n-type semicon-
`ductor regions 12. Wires 19 are connected to the silicide
`layers 14 on a pair of the n-type semiconductor regions 12
`through the plugs 18 buried in the contact holes 17.
`Next, an n-channel MIS transistor 03, that is formed in the
`I/O region, will be described with reference to FIG. 6. The
`threshold voltage (Vth) of the n-channel MIS transistor O3
`is comparably high, which can be regarded as, for example,
`about 0.4 Volt. In case of using two kinds of supply voltages,
`for example,
`the operation voltage (Vcc) applied to the
`n-channel MIS transistor O3 is a high voltage, which can be
`set to, for example, about 1.5 Volt.
`The n-channel MIS transistor O3 is formed, in the same
`manner as the n-channel MIS transistor Q1, in the active
`region surrounded by the device isolation sections that are
`formed on the p-type semiconductor substrate 1. On the
`surface of the semiconductor substrate 1, a pair of the n-type
`semiconductor regions 12 forms the source and the drain.
`However, a gate insulating film 9, having a laminated
`structure made of a silicon oxide film 6 and the high
`dielectric constant insulating film 7, is formed on the semi-
`conductor substrate 1. The gate electrode 11 of the poly-
`crystalline silicon film formed on the gate insulating film 9.
`And, the laminated layer (the silicon oxide film 6 and the
`high dielectric constant insulating film 7) is formed only in
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`a region surrounded by the gate electrode 11, the spacer 13,
`and the semiconductor substrate 1, which makes up the gate
`insulating film 9. The silicide layers 14 are formed on a pair
`of the n-type semiconductor regions 12.
`To cover substantially the whole surface of the semicon-
`ductor substrate 1,
`the SAC insulating film 15 and the
`interlayer insulating film 16 are formed in order from the
`lower layer. The contact holes 17 are formed through the
`interlayer insulating film 16 and the insulating film 15 so as
`to reach the silicide layers 14 on a pair of the n-type
`semiconductor regions 12. The wires 19 are connected to the
`silicide layers 14 on a pair of the n-type semiconductor
`regions 12 through the plugs 18 buried in the contact holes
`17.
`
`Next an n-channel MIS transistor Q4, forming the capaci-
`tance element will be described with reference to FIG. 7. In
`case of using two kinds of supply voltages, for example, the
`operation voltage (Vcc) applied to the n-channel MIS tran-
`sistor O4 is a low voltage, which can be set to, for example,
`about 0.85 Volt.
`
`The n-channel MIS transistor Q4 has substantially the
`same structure as the n-channel MIS transistor Q1. However,
`in the active region that forms the n-channel MIS transistor
`Q4, an n-well 4a can be formed, in addition to a p-well of the
`same conductive type as the semiconductor substrate 1. And,
`the operation voltage (Vcc) is applied to the gate electrode
`11, and a pair of the n-type semiconductor regions 12 is
`connected to the ground voltage.
`
`TABLE 1
`
`Capacitance
`Memory
`element
`Logic region region
`I/O region
`0.85 V
`0.85 V
`0.85 V
`1.5 V
`Vcc
`High (0.4 V) Low (0.1 V) High (0.4 V) —
`Vth
`Gate insulating High-k/SiO High-k
`High-k
`High-k
`film
`Included
`Silicide layer
`SAC insulating SiN
`film
`(Optional)
`Shape of
`Circular
`contact hole
`
`Not included Included
`SiN or
`SiN
`High-k
`(Optional)
`Circular or
`Circular
`slot
`
`Included
`SiN
`(Optional)
`Circular
`
`High-k: high dielectric constant insulating film
`SiO: silicon oxide film
`SiN: silicon nitride film
`
`Table 1 gives a brief summary of the construction of the
`MIS transistor in the memory region, the MIS transistor in
`the logic region, the MIS transistor in the I/O region, and the
`MIS transistor forming the capacitance element.
`the MIS
`In the MIS transistor in the memory region,
`transistor in the logic region, and the MIS transistor forming
`the capacitance element, to which a low voltage is applied
`in correspondence with the two kinds of supply voltages, the
`gate insulating film is made of a high dielectric constant
`insulating film; whereas, in the MIS transistor in the I/O
`region, the gate insulating film is made of a laminated film
`composed of a silicon oxide film and a high dielectric
`constant insulating film.
`The silicide layers are formed on the upper surfaces of a
`pair of the n-type semiconductor regions that form the
`sources and the drains of the MIS transistors in the logic
`region, MIS transistors in the I/O region, and MIS transistors
`forming the capacitance elements; however,
`the silicide
`layers are not formed on the upper surfaces of a pair of the
`n-type semiconductor regions that form the sources and the
`drains of the MIS transistors in the memory region.
`When the circumstances need the SAC technique that
`permits an alignment dislocation between the contact holes
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`US 6,924,237 B2
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`9
`and the gate electrode, the SAC insulating film is formed
`beneath the interlayer insulating film, which has a high
`etching selection ratio relative to the interlayer insulating
`film and fun