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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`____________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`____________
`
`TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD,
`Petitioner,
`
`v.
`
`GODO KAISHA IP BRIDGE 1,
`Patent Owner.
`____________
`
`Case IPR2017-01842
`Patent 7,893,501
`____________
`
`PATENT OWNER’S PRELIMINARY RESPONSE
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`TABLE OF CONTENTS
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`I.
`
`INTRODUCTION ........................................................................................... 1
`
`A. Overview of ‘501 Patent ....................................................................... 2
`
`B.
`
`The Petition’s Grounds Fail .................................................................. 4
`
`1.
`
`2.
`
`3.
`
`Overview of Igarashi ................................................................... 5
`
`Igarashi Does Not Teach Isolation or Active Regions in
`the Fifth Embodiment Relied Upon in Grounds 1 and 2 ............ 7
`
`The Petition Provides No Motivation to Modify
`Igarashi’s Fifth Embodiment to Use the Isolation Regions
`of Igarashi’s First Embodiment .................................................. 9
`
`4. Woerlee Does Not Remedy Igarashi’s Failure to Teach
`Isolation Regions Forming an Active Region in
`Igarashi’s Fifth Embodiment. ................................................... 10
`
`5.
`
`All Challenged Claims Distinguish Over the Petitioner’s
`Alleged Igarashi/Woerlee Combination ................................... 12
`
`a.
`
`b.
`
`The Region Bounded and Defined by the STI
`Regions Is Not an Active Region of Either of the
`Two MISFETs in the Memory Cell ................................ 13
`
`The Channel Region of Each Transistor Is Not an
`Active Region as Claimed .............................................. 15
`
`II.
`
`OVERVIEW OF THE ‘501 PATENT AND CHALLENGED
`CLAIMS ........................................................................................................ 17
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`III. CHALLENGED CLAIMS ............................................................................ 23
`
`IV. LEVEL OF ORDINARY SKILL IN THE ART ........................................... 24
`
`V.
`
`CLAIM INTERPRETATION ....................................................................... 24
`
`A.
`
`“wherein the MISFET includes: an active region made of a
`semiconductor substrate” .................................................................... 25
`
`1.
`
`The ‘501 Patent Specification Describes a MISFET's
`Active Region as Defined by Isolation Regions That
`Isolate the MISFET from Other Transistors Formed in
`the Substrate .............................................................................. 26
`
`i
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`

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`2.
`
`The ‘501 Patent Specification’s Usage Is Consistent with
`the Ordinary Meaning in the Art of a Transistor’s “Active
`Region” ..................................................................................... 29
`
`VI. THE PETITION SHOULD BE DENIED BECAUSE IT FAILS TO
`DEMONSTRATE A REASONABLE LIKELIHOOD OF
`PREVAILING AS TO ANY CHALLENGED CLAIM. .............................. 31
`
`A. Ground 1: Claims 5, 6, 12, 15, 19, and 21 Are Not Rendered
`Obvious by Igarashi and Woerlee. ...................................................... 31
`
`1.
`
`2.
`
`3.
`
`Overview of Igarashi ................................................................. 32
`
`Overview of Woerlee ................................................................ 36
`
`The Petition Fails to Demonstrate that a POSITA
`Following the Teachings of Igarashi and Woerlee Would
`Have Been Led to a Semiconductor Device as Claimed .......... 37
`
`a.
`
`b.
`
`Igarashi Does Not Teach that the Fifth
`Embodiment (Fig. 12) Relied Upon in the Ground
`Includes Isolation Regions or an Active Region
`Formed Thereby.............................................................. 38
`
`The Petition Provides No Motivation to Modify
`Igarashi’s Fifth Embodiment to Use the Isolation
`Regions of Igarashi’s First Embodiment ........................ 44
`
`c. Woerlee Does Not Remedy Igarashi’s Failure to
`Teach Isolation Regions Forming an Active
`Region in Igarashi’s Fifth Embodiment. ........................ 47
`
`d.
`
`Even If Igarashi Is Considered to Teach What the
`Petition Alleges, All Challenged Claims
`Distinguish Over the Petitioner’s Alleged
`Igarashi/Woerlee Combination ....................................... 51
`
`(1) The Region Bounded and Defined by the
`STI Regions Is Not an Active Region of
`Either of the Two MISFETs in the Memory
`Cell ....................................................................... 52
`
`(2) The Channel Region of Each Transistor Is
`Not an Active Region as Claimed ........................ 55
`
`4.
`
`None of Dependent Claims 5, 6, 12, 15, 19, and 21
`Would Have Been Obvious Over Igarashi and Woerlee. ......... 58
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`ii
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`B.
`
`Ground 2: Claim 13 Is Not Rendered Obvious by Igarashi,
`Woerlee, and Hokazono. ..................................................................... 59
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`VII. CONCLUSION .............................................................................................. 60
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`
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`
`iii
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`
`
`CASES
`
`TABLE OF AUTHORITIES
`
`Cuozzo Speed Techs., LLC v. Lee,
`136 S.Ct. 2131 (2016) .......................................................................................... 24
`
`In re Stepan Co.,
`868 F.3d 1342 (Fed. Cir. 2017) ........................................................... 9, 10, 45, 46
`
`KSR Int’l Co. v. Teleflex Inc.,
`550 U.S. 398 (2007) ........................................................................................ 9, 44
`
`Liberty Mut. Ins. Co. v. Progressive Cas. Ins. Co.,
`CBM2012-00003, Paper No. 8 (PTAB Oct. 25, 2012) ................................. 39, 41
`
`PPC Broadband, Inc. v. Corning Optical Commc’ns RF, LLC,
`815 F.3d 747 (Fed. Cir. 2016) .............................................................................. 25
`
`SAS Inst., Inc. v. ComplementSoft, LLC,
`825 F.3d 1341 (Fed. Cir. 2016) ............................................................................ 25
`
`Smith & Nephew, Inc. v. Arthrex, Inc.,
`IPR2016-00918, Paper No. 42 (PTAB Oct. 16, 2017) ......................................... 43
`
`Straight Path IP Grp., Inc. v. Sipnet EU S.R.O.,
`806 F.3d 1356 (Fed. Cir. 2015) ............................................................................ 24
`
`Trivascular, Inc. v. Samuels,
`812 F.3d 1056 (Fed. Cir. 2016) ............................................................................ 24
`
`STATUTES
`
`35 U.S.C. § 314(a) ................................................................................................... 31
`
`REGULATIONS
`
`37 C.F.R. § 42.100(b) .............................................................................................. 24
`
`
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`iv
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`I.
`
`INTRODUCTION
`
`Petitioner seeks inter partes review of claims 5-6, 12-13, 15, 19, and 21
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`(“the challenged claims”) of U.S. Patent No. 7,893,501 (“the ‘501 patent,” Ex.
`
`1101). Each of the challenged claims is a dependent claim that depends from
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`claim 1 of the ‘501 patent. With respect to the limitations of independent claim 1
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`of the ‘501 patent, Petitioner asserts the same arguments based on the same prior
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`art references asserted in IPR2017-01841. To the extent the Board denies
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`institution on independent claim 1 in IPR2017-01841, institution should likewise
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`be denied on all grounds in this petition for the same reasons. To be clear, Patent
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`Owner is not incorporating its other preliminary response by reference; Patent
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`Owner repeats those arguments here.
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`Despite its repeated assertions that claim 1 recites nothing but a
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`“conventional” “standard” MISFET, the Petition implicitly acknowledges that
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`those assertions are unsupported by the evidence. The two Grounds advanced in
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`the Petition are not based upon alleged anticipation of claim 1 by any of the
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`references cited in the Petition, but instead are based on alleged obviousness over
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`Igarashi (Ex. 1104) in view of Woerlee (Ex. 1109). The Petition fails to meet its
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`burden of establishing that the alleged Igarashi/Woerlee combination meets all the
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`limitations of claim 1. Because none of the other asserted combinations of prior art
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`address these deficiencies with respect to claim 1, the Petition fails to meet its
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`1
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`burden with respect to any of the challenged claims, which all depend from claim
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`1, and therefore the Petition should be denied.
`
`A. Overview of ‘501 Patent
`
`
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`The ‘501 patent describes and claims an improved semiconductor device
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`comprising one or more metal-insulator-semiconductor field-effect transistors
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`(“MISFETs”). E.g., Ex. 1101 (‘501 Patent) at Abstract, 1:56-61. As shown in Fig.
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`1 (reproduced below), the semiconductor device has a substrate 1 and a plurality of
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`isolation regions 2 (highlighted in blue) that divide the substrate into a plurality of
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`active regions 1a, 1b (highlighted in yellow). Id. at 3:21-28.
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`‘501 Patent, Ex. 1101, Fig. 1, Annotated
`
`
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`A single MISFET is formed in each active region, and the isolation regions
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`that bound an active region electrically isolate the MISFET formed in that active
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`2
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`

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`region from all other MISFETs formed in the substrate. Id. at 3:21-28, 6:22-26,
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`10:51-54, 12:25-28, Figs. 1-9.
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`Each MISFET comprises source and drain regions, a gate electrode, and a
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`film (e.g., silicon nitride film 8a) that extends from the gate electrode to upper
`
`surfaces of the source/drain regions. Id. at 3:29-37, 41-49, 53-58. The film (e.g.,
`
`silicon nitride film 8a) applies stress to the channel region of the transistor (below
`
`the gate and between the source and drain regions), and through a phenomenon
`
`known as the “piezo resistivity effect,” the applied stress enhances the mobility of
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`charge carriers (e.g., electrons, holes) through the channel and thereby increases
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`the operating speed of the MISFET. Id. at 1:20-23, 1:56-61, 4:34-52.
`
`The ‘501 patent describes each MISFET’s “active region” as a region 1a, 1b
`
`of the substrate that is dedicated to that MISFET and bounded by isolation regions
`
`2 that isolate the MISFET from other transistors formed in the substrate. Id. at
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`3:21-28; see also id. at 6:22-26, 10:51-54, 12:25-28, Figs. 1-9.
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`As discussed in § V.A.2 below, this use of the term “active region” is
`
`consistent with how the term is used in the art. Indeed, all the evidence submitted
`
`with the Petition, including the Petition’s supporting expert declaration from Dr.
`
`Shanfield, refers to an “active region” of a transistor (e.g., a MISFET) as a region
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`dedicated to the transistor and bounded by isolation regions that define the active
`
`region and isolate the transistor from other devices formed in the substrate. See,
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`3
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`e.g., Ex. 1111 (Kang) at 28 (“To achieve a sufficient level of electrical isolation
`
`between neighboring transistors on a chip surface, the devices are typically
`
`created in dedicated regions called active areas, where each active area is
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`surrounded by a relatively thick oxide barrier called the field oxide.”)1; Ex. 1102
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`(Shanfield Decl.) at ¶ 67 (an “active region is formed in the substrate and defined
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`by the STI [shallow trench isolation] regions.”); id. (citing Ex. 1110 (Rabaey) at
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`42-43 as teaching that active regions are regions where transistors will be
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`constructed and that all other areas are covered with a field oxide that acts as an
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`insulator between neighboring devices); id. at ¶ 70 (citing Ex. 1109 (Woerlee) at
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`4:66-5:5 as teaching that insulating regions “define an active region 4 in which a
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`transistor … is to be manufactured.”); id. at ¶ 80 (“Woerlee and the ‘501 patent
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`both describe the active region made of the substrate as the region bounded by
`
`isolations [sic] regions where the transistor is formed.”).
`
`B.
`
`The Petition’s Grounds Fail
`
`Ground 1 of the Petition alleges obviousness over Igarashi in view of
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`Woerlee, and Ground 2 of the Petition alleges obviousness over Igarashi in view of
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`Woerlee and Hokazono (Ex. 1107). Both of these Grounds fail for two reasons.
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`First, both of these Grounds rely upon disparate features from different
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`embodiments in Igarashi that Igarashi nowhere describes as being used together
`
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`1 Emphasis added throughout unless otherwise indicated.
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`4
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`and arranged in the manner required by the claims. Second, even if a POSITA
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`would have been led to combine the features of Igarashi and Woerlee in the
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`manner alleged in the Petition, the resulting semiconductor device does not include
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`a MISFET having an active region as claimed. Ground 1 fails for at least these
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`reasons. In addition, because Hokazono, which has been cited in the Petition for
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`the sole purpose of disclosing a gate insulating film that is a silicon oxynitride film,
`
`fails to remedy these deficiencies of Igarashi and Woerlee, Ground 2 also fails for
`
`the same reasons that Ground 1 fails.
`
`1. Overview of Igarashi
`
`Igarashi discloses six different embodiments of a semiconductor device. Ex.
`
`1104 (Igarashi) at ¶¶ 0043, 0087, 0101, 0108, 0116, 0123. Grounds 1 and 2 of the
`
`Petition both rely on the “Fifth Embodiment,” which is illustrated in Fig. 12 of
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`Igarashi (reproduced below). Petition at 21-22, 36-45. Igarashi’s Fifth
`
`Embodiment is directed to a memory cell formed by a pair of interconnected
`
`metal-oxide-semiconductor (MOS) transistors that share a common source/drain
`
`region (e.g., a region comprising an impurity diffusion layer 4 and a silicide film
`
`5). See Ex. 1104 (Igarashi) at ¶¶ 0088, 0117. The Fifth Embodiment has a silicon
`
`nitride film (highlighted in blue below), but it serves a different purpose than the
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`silicon nitride film in the ‘501 patent and does not apply compressive and/or tensile
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`5
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`

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`stresses to impact the performance of either of the two MOS transistors in the
`
`memory cell.
`
`Igarashi, Ex. 1104, Fig. 12, Annotated
`
`
`
`
`
`Igarashi provides no disclosure of isolation regions formed in the substrate
`
`in connection with the Fifth Embodiment, and no disclosure of active regions
`
`formed between such isolation regions in the Fifth Embodiment. That is fatal to
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`both of the Petition’s Grounds.
`
`The Petition points to a disclosure in Igarashi of an “active element region”
`
`formed by isolation regions, but that disclosure relates to a different embodiment
`
`of Igarashi – the “First Embodiment” in Figs. 1-5 – and not to the Fifth
`
`Embodiment that is the basis for Grounds 1 and 2. Petition at 24-25 (citing
`
`Igarashi at ¶ 0068). Unlike Igarashi’s Fifth Embodiment, Igarashi’s First
`
`Embodiment is a single transistor device. Ex. 1104 (Igarashi) at ¶ 0044, Figs. 1-5.
`
`Thus, Igarashi’s disclosure of an “active element region” for a single transistor is
`
`consistent with the ‘501 patent and the other evidence of record, which all describe
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`6
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`an active region of a MISFET as a region dedicated to that MISFET and bounded
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`by isolation regions that electrically isolate the MISFET from other transistors
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`formed in the substrate.
`
`Neither of the two MOS transistors in the memory cell of Igarashi’s Fifth
`
`Embodiment (Fig. 12) could be formed in an active region bounded by isolation
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`regions, because the two MOS transistors in the memory cell of the Fifth
`
`Embodiment share a common source/drain region (highlighted in green below), so
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`those two transistors cannot be electrically isolated from one another.
`
`Igarashi, Ex. 1104, Fig. 12, Annotated
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`
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`2.
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`Igarashi Does Not Teach Isolation or Active Regions in the
`Fifth Embodiment Relied Upon in Grounds 1 and 2
`
`The Petition alleges that Igarashi teaches shallow trench isolation (STI)
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`regions in Igarashi’s Fifth Embodiment (Fig. 12), and that these STI regions form
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`an “active region” as shown in the below-reproduced figure from the Petition.
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`Petition at 24-26.
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`7
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`Pet. at 26, Petitioner’s Annotated Version of Igarashi, Ex. 1104, Fig. 12
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`Petitioner annotated Igarashi’s Fig. 12 to add the “STI regions” and the
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`“Active Region” allegedly formed between them. The Petition asserts that a
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`POSITA would have understood Igarashi to disclose the STI regions and the active
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`region formed therebetween in the Fifth Embodiment of Fig. 12:
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`because [Igarashi] explicitly discloses a [sic] ‘active element
`
`region’ and because [Igarashi] discloses using the ‘trench
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`method’ for ‘element isolation,’ meaning the trench method is
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`used to form shallow trench isolation (STI) regions that define
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`the active region where the transistor is formed.
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`Petition at 25.
`
`However, the cited disclosure in Igarashi of forming isolation regions that
`
`define an active element region relates to Igarashi’s single-transistor First
`
`Embodiment, not to Igarashi’s Fifth Embodiment. Id. (citing Igarashi at ¶ 0068,
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`8
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`which describes “the method for manufacturing the semiconductor device of the
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`First Embodiment”). The Petition’s assertion that Igarashi teaches that its Fifth
`
`Embodiment (Fig. 12) includes STI regions, and the active region allegedly formed
`
`thereby, is unsupported by any evidence or analysis. That is fatal to the Petition’s
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`Grounds.
`
`3.
`
`The Petition Provides No Motivation to Modify Igarashi’s
`Fifth Embodiment to Use the Isolation Regions of Igarashi’s
`First Embodiment
`
`To render a challenged claim obvious, it is not enough to show that each of
`
`its elements was independently disclosed in the prior art. KSR Int’l Co. v. Teleflex
`
`Inc., 550 U.S. 398, 418 (2007). Instead, a reason must be identified that would
`
`have prompted a POSITA to combine the elements in the way the claimed
`
`invention does. Id. This principle applies not just to combinations of separate
`
`prior art references, but also to combinations of separate embodiments within the
`
`same prior art reference. In re Stepan Co., 868 F.3d 1342, 1346 n.1 (Fed. Cir.
`
`2017) (“Whether a rejection is based on combining disclosures from multiple
`
`references, combining multiple embodiments from a single reference, or selecting
`
`from large lists of elements in a single reference, there must be a motivation to
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`make the combination.”).
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`The Petition fails to offer any reason or motivation for a POSITA to have
`
`combined the STI regions from the single-transistor semiconductor device of
`
`9
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`Igarashi’s First Embodiment with the multi-transistor memory cell of Igarashi’s
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`Fifth Embodiment. Indeed, the Petition does not even argue that features from
`
`these different embodiments are combined, and instead relies entirely on the
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`erroneous assertion that Igarashi explicitly teaches isolation regions and an active
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`region in Igarashi’s Fifth Embodiment (Fig. 12). The failure to offer “a motivation
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`to make the combination” of “multiple embodiments” from Igarashi also is fatal to
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`Grounds 1 and 2 of the Petition. In re Stepan Co., 868 F.3d at 1346 n.1.
`
`4. Woerlee Does Not Remedy Igarashi’s Failure to Teach
`Isolation Regions Forming an Active Region in Igarashi’s
`Fifth Embodiment.
`
`Igarashi provides no detail about where the isolation (STI) regions are
`
`located in the vertical dimension of the First Embodiment (Figs. 1-5). That is,
`
`Igarashi does not disclose whether the isolation regions are formed in substrate 1,
`
`silicide film 5, or silicon nitride film 8. The Petition relies upon Woerlee for the
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`sole purpose of establishing where Igarashi’s STI regions are formed in the vertical
`
`(not horizontal) dimension, and to establish that the STI regions are formed in the
`
`semiconductor substrate rather than in a layer above the substrate. Petition at 26-
`
`31.
`
`As the Petition acknowledges, Woerlee teaches isolation (STI) regions 3 that
`
`form an active region 4 for each transistor, so that each transistor has a dedicated
`
`active region and is electrically isolated from the other transistors formed in the
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`10
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`substrate. Petition at 26-29 (citing Woerlee Fig. 13 and 4:66-5:5 (“[isolation]
`
`regions 3 … define an active region 4 in which a [singular] transistor … is to be
`
`manufactured.”)). Thus, as shown in Woerlee’s Fig. 13 reproduced in the Petition
`
`at page 27 (and below), Woerlee does not teach placement of isolation regions 3
`
`around a multi-transistor memory cell like Igarashi’s Fifth Embodiment, but rather
`
`only around a single transistor.
`
`Woerlee, Ex. 1109, Fig. 13
`
`
`
`Woerlee does not suggest placement of isolation regions around the entire
`
`Igarashi memory cell in the locations asserted in the Petition and shown in
`
`Petitioner’s annotated version of Igarashi Fig. 12. Indeed, the Petition does not
`
`even allege that Woerlee would have motivated a POSITA to insert isolation
`
`regions into the Fifth Embodiment of Igarashi at all. Rather, the Petition only
`
`relies on Woerlee to teach that such isolation regions (allegedly taught by
`
`Igarashi) would be formed in Igarashi’s substrate.
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`11
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`Thus, Woerlee does not cure the Petition’s failure to provide any evidence
`
`supporting the assertion that Igarashi’s Fifth Embodiment has isolation regions
`
`forming an active region.
`
`5.
`
`All Challenged Claims Distinguish Over the Petitioner’s
`Alleged Igarashi/Woerlee Combination
`
`Even if Igarashi is considered to teach that its Fifth Embodiment has
`
`isolation regions around the entire memory cell as the Petition alleges, such a
`
`semiconductor device does not comprise a MISFET that includes an active region
`
`as required by all the challenged claims.
`
`The ‘501 patent and all the evidence of record (see § V.A.2 below) establish
`
`that an “active region” of a MISFET is a region dedicated to that MISFET and
`
`bounded by isolation regions that define the boundaries of the active region and
`
`electrically isolate the MISFET from other transistors formed in the substrate.
`
`There is no such active region for either MISFET in Igarashi’s Fifth Embodiment
`
`(Fig. 12).
`
`The Petition fails to provide a clear explanation of how the Igarashi/Woerlee
`
`combination is alleged to meet the requirement in all challenged claims of a
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`“MISFET [that] includes: an active region made of a semiconductor substrate.” As
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`shown in Petitioner’s annotated version of Fig. 12 (reproduced below), the Petition
`
`identifies the alleged “Active Region” with two arrows pointing to areas under the
`
`gates of the two MISFETs in Fig. 12, and alleges that the “active element region is
`
`12
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`made of the substrate 1 of Igarashi and divided by STI regions.” Petition at 26-31,
`
`36.
`
`
`
`Pet. at 26, Petitioner’s Annotated Version of Igarashi, Ex. 1104, Fig. 12
`
`a.
`
`The Region Bounded and Defined by the STI Regions
`Is Not an Active Region of Either of the Two
`MISFETs in the Memory Cell
`
`To the extent the Petition asserts that the entire memory cell has one “Active
`
`Region” bounded by the STI regions which Petitioner (improperly) inserted into
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`Igarashi’s Fig. 12, that assertion is unsupported by any evidence. The only usage
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`of the term “active region” in the record is to describe a region that is dedicated to
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`a single transistor and bounded by isolation regions that isolate the transistor from
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`other devices (e.g., transistors) formed in the substrate. See § V.A.2 below. The
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`region bounded by the STI regions Petitioner inserted into Igarashi’s Fig. 12
`
`encompasses the entire memory cell of Fig. 12, and is not an active region of either
`
`MISFET in the memory cell.
`
`13
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`In the semiconductor device the Petition alleges that Igarashi discloses in
`
`Fig. 12, the STI regions do not separate and electrically isolate the two MISFETs
`
`in the memory cell. Indeed, those MISFETs share a source/drain region
`
`(comprising impurity diffusion layer 4 and silicide film 5 which are outlined in red
`
`in the figure below) and are electrically coupled. The region of the substrate the
`
`Petition alleges is an “active region” (highlighted in yellow below) includes this
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`shared source/drain region, as well as the other source/drain regions of the two
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`MISFETs in the memory cell. Thus, neither of the MISFETs in the
`
`Igarashi/Woerlee combination includes an active region that is bounded by
`
`isolation regions that electrically isolate the MISFET from the other transistor with
`
`which it shares the memory cell.
`
`Pet. at 26, Petitioner’s Annotated Version of Igarashi, Ex. 1104, Fig. 12
`Further Annotated with Yellow Highlighting and Red Outlining by Patent Owner
`
`
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`14
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`b.
`
`The Channel Region of Each Transistor Is Not an
`Active Region as Claimed
`
`In Petitioner’s annotated version of Igarashi’s Fig. 12, the “Active Region”
`
`is identified with two arrows, each pointing to the channel region of one of the
`
`MISFETs in the memory cell. The Petition does not allege that there are two
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`separate active regions in Igarashi’s Fig. 12 – one corresponding to each of the two
`
`MISFETS in the memory cell. Any such assertion would fail, for two reasons.
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`Pet. at 26, Petitioner’s Annotated Version of Igarashi, Ex. 1104, Fig. 12
`Further Annotated with Red and Yellow Highlighting by Patent Owner
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`First, all the evidence of record, as the Petition itself acknowledges
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`repeatedly, establishes that an active region as claimed is a region bounded by and
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`defined by isolation regions. See § V.A.2 below; see, e.g., Petition at 25
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`(“isolation (STI) regions that define the active region where the transistor is
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`formed.”); id. (“the active region is … defined by the STI regions.”); id. at 27
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`(“isolation regions 3 … define the active region 4 of the substrate body 1 where the
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`transistor is formed.”); id. at 29 (“the active region is an area of the semiconductor
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`body 1 defined and separated by field insulation region 3”). The channel region
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`for each transistor (highlighted in red above) is not a region defined by the
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`isolation (STI) regions the Petition alleges are present in the Igarashi/Woerlee
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`combination. Only the much larger substrate area (highlighted in yellow above)
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`for the entire memory cell is bounded by and defined by the STI regions Petitioner
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`inserted into the Igarashi/Woerlee combination, and that larger area is not an active
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`region of either individual MISFET in the memory cell for the reasons stated in
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`§ I.B.5.a above.
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`Second, any assertion that the channel region meets the claimed “active
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`region” of the MISFET is contradicted not only by the evidence of record
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`establishing the ordinary meaning of “active region” as a region bounded by
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`isolation regions (see § V.A.2 below), but also by the specification of the ‘501
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`patent. The specification clearly differentiates between active regions 1a and 1b
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`into which the substrate is divided by isolation regions, and much smaller channel
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`regions 1x and 1y, each of which is the “[p]art of the active region 1a [1b] … in
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`which [carriers] move (travel) when the nMISFET [pMISFET] is in an operation
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`state.” Ex. 1101 (‘501 patent) at 3:29-52. Therefore, the ‘501 patent specification
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`makes clear that the channel region for a MISFET (highlighted in red below) is not
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`the active region for that MISFET (highlighted in yellow below) as claimed, but
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`rather the channel region is part of a much larger active region.
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`Channel Regions
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` ‘501 Patent, Ex. 1101, Fig. 1, Annotated
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`Thus, even if Igarashi disclosed STI regions in the locations inserted by
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`Petitioner – which it does not – the Igarashi/Woerlee combination is not a
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`“semiconductor device, comprising a MISFET, wherein the MISFET includes: an
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`active region” as recited in all the challenged claims. Ground 1 fails for at least
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`this additional reason. Since Hokazono does not cure the deficiencies of the
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`alleged Igarashi/Woerlee combination, Ground 2 also fails for at least this reason.
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`II. OVERVIEW OF THE ‘501 PATENT AND CHALLENGED CLAIMS
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`The ‘501 patent describes and claims an improved semiconductor device
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`comprising one or more electrically isolated MISFETs, where at least one MISFET
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`of the device comprises a silicon nitride film and a gate electrode protruding from
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`the silicon nitride film. As an illustrative example, Fig. 1 of the ‘501 patent
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`(reproduced below) shows a semiconductor device comprising two MISFETs – an
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`nMISFET and a pMISFET. Ex. 1101 (‘501 patent) at 3:19-28.
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`Channel Regions
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` ‘501 Patent, Ex. 1101, Fig. 1, Annotated
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`As shown in Figure 1, the semiconductor device comprises a semiconductor
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`substrate 1 that is divided into a plurality of active regions 1a and 1b (highlighted
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`in yellow above) by isolation regions 2. Id. The nMISFET is formed in an
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`nMISFET formation region Rn that includes active region 1a. Id. The pMISFET
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`is formed in a pMISFET formation region Rp that includes active region 1b. Id.
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`The nMISFET comprises n-type source/drain regions 3a and 4a, each of
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`which comprises an n-type lightly-doped region, an n-type heavily-doped region,
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`and a silicide layer. Id. at 3:29-32. The nMISFET also comprises a gate insulating
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`film 5 deposited on semiconductor substrate 1 over active region 1a, a gate
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`electrode 6a deposited on gate insulating film 5, and silicon oxide sidewalls 7
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`positioned on either side of gate electrode 6a. Id. at 3:32-37; see id. at 8:10-12,
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`8:46-49. Silicon nitride film 8 is formed over source/drain regions 3a and 4a such
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`that gate electrode 6a protrudes upward from parts of silicon nitride film 8 located
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`at both side surfaces of gate electrode 6a. Id. at 3:53-55.
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`The pMISFET comprises p-type source/drain regions 3b and 4b, each of
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`which comprises a p-type lightly-doped region, a p-type heavily-doped region, and
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`a silicide layer. Id. at 3:41-44. The pMISFET also comprises a gate insulating
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`film 5 deposited on semiconductor substrate 1 over active region 1b, a gate
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`electrode 6b deposited on gate insulating film 5, and silicon oxide sidewalls 7
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`positioned on either side of gate electrode 6b (active regions are highlighted in
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`yellow above). Id. at 3:44-49; see id. at 8:10-12, 8:46-48. TEOS film 8b is formed
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`over source/drain regions 3b and 4b such that gate electrode 6b protrudes upward
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`from parts of TEOS film 8b located at both side surfaces of gate electrode 6b. Id.
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`at 3:55-59.
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`In operation of the nMISFET, a gate voltage may be applied to gate
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`electrode 6a, which affects the flow of charge carriers (electrons) through channel
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`region 1x (highlighted in red above) between source/drain regions 3a and 4a. Id. at
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`3:37-40. Similarly, in operation of the pMISFET, a gate voltage applied to gate
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`electrode 6b affects the flow of charge carriers (holes) through channel region 1y
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`(highlighted in red above) between source/drain regions 3b and 4b. Id. at 3:49-52.
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`The mobility of charge carriers (electrons for the nMISFET and holes for the
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`pMISFET) through channel regions 1x and 1y is increased by the use of “internal
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`stress films.” The ‘501 patent describes two types of internal stress films. A “first-
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`type internal stress film” generates a tensile stress substantially parallel to the
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`direction (referred to as the “gate length direction”) that carriers move between the
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`source and drain. Id. at 4:3-7. A “second-type internal stress film” generates a
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`compressive stress substantially parallel to the gate length direction. Id. at 4:8-12.
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`For example, in the nMISFET, a first-type internal stress film is used to
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`generate a tensile stress in the gate length direction in the channel region of the
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`nMISFET between the source and drain. Id. at 4:34-50. This is accomplished by
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`using a stress film that generates a compressive stress within the film itself, and
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`applying that compressive stress “to the source region 3a and the drain region 4a in
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`the active region 1a of the nMISFET in the parallel direction to the principal
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`surface.” Id. As shown conceptually in the figure below, applying compressive
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`stresses to the source and drain regions (red arrows) creates the desired tensile
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`stress (blue arrows) in the channel region between the source and the drain regions.
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` ‘501 Patent, Ex. 1101, Portion of Fig. 1, Annotated
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`For the pMISFET, the second-type internal stress film is used to generate a
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`compressive stress in the gate length direction in the channel region of the
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`pMISFET between the source and drain. Id. at 5:32-51. This is accomplished by
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`using a stress film that generates a tensile stress within the film itself, and applying
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`that tensile str