IEEE ELECTRON DEVICE LETTERS, VOL. 11, NO. 5. MAY 1990
`
`221
`
`A New LDD Structure: Total Overlap with
`Polysilicon Spacer (TOPS)
`J. E. MOON, T. GARFINKEL, J. CHUNG, M. WONG, P. K. KO, AND CHENMING HU, FELLOW, IEEE
`
`Abstract—This letter presents a new fully overlapped lightly doped
`drain structure—~the total overlap with polysilicon spacer (TOPS) struc-
`ture. The TOPS structure achieves full gate overlap of the lightly doped
`region with simple processing. TOPS devices have demonstrated superior
`performance and reliability compared to oxide-spacer lightly doped drain
`(LDD) devices, with an order of magnitude advantage in current
`degradation under stress for the same initial current drive or 30% more
`drive for the same amount of degradation. TOPS devices also show a
`much smaller sensitivity to n‘ dose variation than LDD devices. Gate-
`induced drain leakage (GIDL) is reported for the first time in fully
`overlapped LDD devices.
`
`I. INTRODUCTION
`
`HE long-term reliability of n—channel MOSFET's has
`been a major concern as device channel lengths have been
`reduced to submicrometer and deep-submicrometer dimen-
`sions [1], [2]. The lightly doped drain (LDD) structure [3] has
`been widely investigated as a means of reducing the lateral
`electric field and the associated hot—carrier effects on reliabil—
`
`ity. Theoretical and experimental investigations [4]—[6] have
`demonstrated that gate control over the n‘ region is a crucial
`element
`in both the performance and reliability of LDD
`devices. This letter presents a new fully overlapped lightly
`doped drain structure—the total overlap with polysilicon
`spacer (TOPS) structure. Unlike other proposed fully over—
`lapped structures which require complicated fabrication se-
`quences or unusual fabrication techniques [5]—[7], the TOPS
`structure achieves full overlap with simple and proven
`processing techniques.
`11. DEVICE PROCESSING
`
`1 shows the critical steps in the fabrication sequence.
`Fig.
`Gate oxide is grown after LOCOS isolation, and then layers of
`thin polysilicon, very thin LPCVD oxide, and thick doped
`polysilicon are deposited. Wafers were cleaned in piranha
`(HZSO4/H202) after thin polysilicon deposition, followed by
`removal of chemical oxide in dilute HF;
`the thin oxide
`deposition was followed directly by thick polysilicon deposi-
`tion. Gate definition (using the thin LPCVD oxide as an etch
`stop) is followed by n‘ implantation through the thin oxide
`and thin polysilicon layers, and removal of the thin oxide in
`
`Manuscript received November 14, 1989; revised January 25, 1990. This
`work was supported in part by JSEP under Contract F4962087-C»0041 and
`by ISTO/SDIO through ONR under Contract N00014—85-K-0603. J. E. Moon
`was supported by a Doctoral Award from Eastman Kodak Company.
`The authors are with the Department of Electrical Engineering and
`Computer Sciences, University of California, Berkeley, CA 94720.
`IEEE Log Number 9035748.
`
`
`LPCVD oxide 100 R
`
`/ poly 400 A
`4,0xide 150 A
`/substrate
`
`
`
`
`gate lithographyi+ poly etch + LTO strip
`
`
`
`
`
`
`
`
`
`Fig. l. TOPS structure layered gate and polysilicon spacer formation. Gate
`and spacer definitions are accomplished by plasma etching with oxide
`endpoint detection. Typical CVD film thicknesses are shown.
`
`dilute buffered HF. Doped polysilicon is then deposited and
`etched to form the polysilicon spacer. The last etch proceeds
`until a well—defined endpoint corresponding to gate oxide and
`field oxide is detected. Both polysilicon etches are very easily
`controlled and do not require the extremely high selectivity or
`timed etching of previously reported structures [5], [6]. The
`oxide-spacer LDD devices were prepared by n‘ implantation
`after gate definition, followed by LPCVD oxide deposition,
`densification, and etch-back to form the oxide spacer [8].
`Control over formation of the TOPS polysilicon spacer is
`much easier than that of the LDD oxide spacer because of the
`easily detected endpoint; the oxide spacer etch must be timed.
`Source/drain nJr implantation, contact formation, and metalli—
`zation follow a standard process sequence. Although it was not
`done in this initial study, silicidization of gate, source, and
`drain could be done by additional process steps after the
`polysilicon spacer formation.
`All devices had a gate oxide of 15 nm and were fabricated
`using the deep—submicrometer optical lithographic technique
`reported earlier [9]. All spacer lengths were designed to be 0.2
`um. TOPS devices received n‘ doses of 0.5, 1.0, and 3.0 X
`1013 cm”, and the oxide—spacer LDD devices received doses
`of 0.5 and 1.5 X 1013 cm”. Two types of TOPS devices,
`having either in-Situ doped or undoped thin polysilicon, were
`
`074173106/90/0500e0221$01.00 © 1990 lEEE
`
`TMSC 1116
`
`TMSC 1116
`
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`

`222
`
`IEEE ELECTRON DEVICE LETTERS, VOL. 11, N0. 5. MAY 1990
`
`TABLE I
`EFFECT OF n“ DOSE VARIATION ON PERFORMANCE OF TOPS AND LDD
`DEVICES
`
`
`
`
`
`1,15,, values measured at Vg : 5 V; gmHt values measured at Vd : 3 V.
`
`
`.
`Performance1
`Structure
`Dose (cm 2)
`—
`'
`
`I,m (mA/um
`gm,“ (mS/mm)
`l
`
`0.5 x [0‘3
`045/036
`118/103
`‘
`
`g
`1.0 x 10IT
`0.4§/0.36
`120/104
`.5
`,
`3.0 x 10’3
`048/038
`122/104
`0.5 x 10
`036/032
`90/34
`LDD
`
`1.5 x 10”
`043/036
`110/98
`[
`' Dual entries are for Lefi=0.5 um and 1350.8 um.
`
`
`TOPS
`
`Tax—15mm
`a LDD-1E13
`i LDD-5E12
`A NON-LDD
`
`o TOPS-3E1}
`O TOPS-1E”
`v TOPS-lEiJmum
`A TOPS-5E! 2
`may—mun.
`
`('r=1zoosec) 1 0“1
`dId/Id(x)
`
`7O
`
`
`90
`130
`140
`100
`110
`120
`
`80
`
`(mS/mm)
`Gus“.
`Fig. 2. Overall performance comparison of TOPS, LDD. and non—LDD
`technologies. Degradation values are for forward linear operation and gm.“
`values are measured at Vd : 3 V.
`
`made in order to investigate the possibility of modifying the
`gate work function through the doping of the bottom layer of
`the gate [10]. In~situ doped polysilicon was used in all TOPS
`devices for
`the thick top layer of the gate and for the
`polysilicon spacer.
`
`III. PERFORMANCE AND RELIABILITY
`
`Performance and reliability characteristics of non-LDD,
`conventional oxide—spacer LDD, and TOPS n—MOSFET de-
`vices have been evaluated. Table 1 contains a comparison of
`TOPS and LDD device performance for Le” of 0.5 and 0.8 pm.
`The TOPS structure, due to the fully overlapped gate, shows
`better current drive and larger transconductance than an LDD
`structure of comparable channel length. The gm characteristics
`of the TOPS devices approach those of non—LDD‘s
`in
`magnitude. At Vd = 3 V the peak gm of non—LDD, TOPS, and
`oxide spacer LDD devices were 109, 104, and 98 mS/mm,
`respectively, for an Leff of 0.8 pm. The drive advantage of
`TOPS devices over LDD devices was seen to increase with
`decreasing channel
`length, with as much as 20% more at
`Leg = 0.3 pm (0.62 versus 0.52 mA/pm). Importantly, the
`TOPS devices show a much smaller sensitivity to n‘ dose
`variation than the LDD devices do over the range of doses
`evaluated, as shown in Table I. It should be noted that device
`and process characteristics have not necessarily been opti-
`
`mized with respect to n‘ dose and spacer length in this initial
`feasibility study.
`For a given L,“ the TOPS device has significantly less
`substrate current than the non-LDD device. Peak [m (at Vd =
`5 V and Vg ~ 2 V; W = 10 am, Le“ = 0.8 um) was 81.16,
`and 8 “A for non—LDD, TOPS, and LDD devices,
`respec—
`tively. Although TOPS devices have more 1M, than oxide
`spacer LDD devices, they exhibit significantly less hot-carrier
`degradation. After 20 min of stressing at peak 1M, and VD = 6
`V, a TOPS device with Le“ = 0.8 pm shows a forward linear
`current degradation of 1.0% compared to 4.4 and 34% for the
`LDD and non-LDD devices, respectively. Creation of inter-
`face traps by hot carriers and subsequent electron trapping is
`offset in the TOPS device by the overlapped gate, whereas in
`the LDD device only fringing fields are available to exert
`control over the resistive 11’ region. A definitive comparison
`of performance and reliability among the three device struc-
`tures is shown in Fig. 2. The superiority of the TOPS devices
`compared to the LDD and non-LDD devices in this study is
`clearly demonstrated, with roughly an order of magnitude
`advantage in degradation for the same drive or 30% more
`drive for the same amount of degradation. Fig. 2 also shows
`the effect of 11’ close variations for the levels studied. The
`TOPS structure again appears to be less sensitive to n’ dose
`variability.
`The doping of the thin polysilicon layer (as deposited) had
`no demonstrable effect on the current drive or reliability of the
`TOPS devices. One plausible explanation for the lack of a
`noticeable effect of thin polysilicon doping on both perform—
`ance and reliability is that the undoped thin polysilicon may
`have been subsequently doped by diffusion from the top gate
`and spacer polysilicon. The thermal cycle after gate definition
`and source/drain implant was carefully controlled in order to
`limit junction drive-in (a total of 30 min at 925°C), but it is
`possible that dopant diffusion occurred rapidly along polysili-
`con grain boundaries.
`The gate—induced drain leakage (GIDL) [ll] behavior of
`non-LDD, oxide—spacer LDD, and TOPS devices are com—
`pared in Fig. 3. Besides hot-carrier degradation, GIDL is
`considered to be another major factor in limiting the power-
`supply voltage for deep—submicrometer MOS technologies [2].
`The non-LDD MOSFET has the largest GIDL, as expected
`[11]. Of the remaining two devices, the oxide—spacer LDD is
`GIDL—free while the TOPS device still shows significant
`
`

`

`223
`
`reported here, implying less overall process sensitivity. GIDL
`was noted in the TOPS devices, the first such report of this
`behavior in fully overlapped LDD devices. This represents an
`important design constraint for submicrometer devices. The
`superior performance and reliability characteristics of the
`TOPS structure merit further investigation for deep-submicro—
`meter applications.
`
`[3]
`
`REFERENCES
`[1] C. Hu et al., “Hot—electron induced MOSFET degradation—Model.
`monitor, and improvement,“ IEEE Trans. Electron Devices, vol.
`ED—32, no. 2. p. 375, 1985.
`for deepesubmicmmeter
`[2] M.—C.
`Ieng e!
`(11.,
`“Design guidelines
`MOSFET’s," in IEDM Tech. Dig., 1988. p. 386.
`S. Ogura. P. J, Tsang, W. W. Walker, D. L. Critchlow, and I. F.
`Shepard, “Design and characteristics of the lightly doped drain—source
`(LDD) insulated gate field-effect transistor,“ IEEE Trans. Electron
`Devices, vol. ED-27, no. 8, p. 1359, 1980.
`[4] K. Mayaram, J. C. Lee, and C. Hu, “A model for the electric field in
`lightly doped drain structures,“ IEEE Trans. Electron Devices, vol.
`ED-34, no. 7, p. 1509, 1987.
`[5] T.»Y. Huang et
`(11.. “A new LDD transistor with inverse-T gate
`structure,” IEEE Electron Device Lett., vol. EDL—8, no. 4, p. 151,
`1987.
`[6] R. Izawa, T. Kure, S. Iijima, and E. Takeda, “The impact of gate—
`drain overlapped LDD (GOLD)
`for deep submicron VLSI‘s," in
`IEDM Tech. Dig., 1987. p. 38.
`[7] T. Hori, K. Kurimoto, T. Yabu, and G. Fuse, “A new submicmn
`MOSFET with LATlD (large-tilt—angle implanted drain) structure," in
`Dig. Tech. Papers Symp. VLSI Technol, 1988, p. 15.
`S. Ogura, P. J. Tsang, W. W. Walker, D. L. Critchlow, and J. F.
`Shepard, “Elimination of hot electron gate current by the lightly doped
`drain»source structure,” in IEDM Tech. Dig., 1981, p. 651.
`J. Chung et (11., “Deep-submicrometer MOS device fabrication using a
`photoresist-ashing technique,” IEEE Eleclrort Device Lem, vol. 9,
`no. 4, p. 186, 1988.
`J. R. Pfiester and L. C. Parrillo. "A novel p"/p* poly gate CMOS
`VLSI Technology,“ IEEE Trans. Electron Devices, vol. 35, n0. 8, p.
`1305, 1988.
`T. Y. Chan, J. Chen. P. K. K0. and C. Hu, “The impact of gate-
`induced drain leakage current on MOSFET scaling,” in IEDM Tech.
`Dig., 1987. p. 718.
`
`[8]
`
`[9]
`
`[10]
`
`[11]
`
`MOON et (11.: TOTAL OVERLAP WITH POLYSILICON SPACER
`
`n<channel MOSFET’s
`I
`= 15 "m
`0X
`
`1504
`
`W/LEff = 10/5 um
`VD = 5 V
`
`
`
`1E-06
`
`1E708
`
`gE
`
`E3
`U
`
`{2
`
`lE-10
`
`115-12
`
`1E—14
`
`— 2.4
`
`- 1.6
`
`- 0.8
`(V)
`Gate Voltage
`Fig. 3. GIDL behavior of TOPS, LDD, and non~LDD devices. Implanted
`n' doses are 3 X 10” and 1.5 X 10" cm‘2 for the TOPS and LDD
`devices, respectively.
`
`0.0
`
`0.8
`
`GIDL. Because the gate would overlap the n+ region in any
`fully overlapped LDD device such as TOPS, we expect GIDL
`to be an important design consideration for fully overlapped
`LDD structures.
`
`IV. CONCLUSIONS
`
`A new fully overlapped LDD structure—TOPS—has been
`fabricated and characterized. TOPS devices produce more
`current drive and better transconductance than oxide—spacer
`LDD devices of equivalent size. A major advantage of TOPS
`over LDD is its improved reliability. Even though the TOPS
`devices had greater 15",, than LDD devices, current degrada—
`tion under hot—electron stressing conditions is significantly less
`for the TOPS devices. The choice of [1“ dose is less critical for
`the TOPS structure than for the LDD structure in the results
`
`