`Filed By: David L. Cavanaugh, Reg. No. 36,476
`Dominic E. Massa, Reg. No. 44,905
`Michael H. Smith, Reg. No. 71,190
`1875 Pennsylvania Ave. NW
`Washington, DC 20006
`Tel: (202) 663-6000
`Email: David.Cavanaugh@wilmerhale.com
`Dominic.Massa@wilmerhale.com
`MichaelH.Smith@wilmerhale.com
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________________________________
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________________________________
`
`
`TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
`Petitioner
`
`v.
`
`GODO KAISHA IP BRIDGE 1
`Patent Owner.
`
`Case IPR2017-01842
`
`
`PETITIONER’S UPDATED EXHIBIT LIST
`
`
`
`
`U.S. Patent 7,893,501
`IPR2017-01842
`Petitioner’s Updated Exhibit List
`
`
`
`
`Pursuant to the Board’s Order dated December 29, 2017, Petitioner hereby
`
`submits the December 19, 2017 Conference Call Transcript as Exhibit 1129 and
`
`the infringement contentions dated February 1, 2017 for U.S. Patent 7,893,501
`
`from Godo Kaisha IP Bridge 1 v. Xilinx, Inc., Case No. 2:17-cv-00100 (E.D. Tex.)
`
`as Exhibit 1130. Petitioner also hereby submits an updated exhibit list.
`
`
`
`
`
`Respectfully Submitted,
`
`/ Michael Smith/
`
`_______________________________
`Michael H. Smith
`Registration No. 71,190
`Wilmer Cutler Pickering
`Hale & Dorr LLP
`Tel: 202-663-6000
`Fax: 202-663-6363
`
`1
`
`
`
`U.S. Patent 7,893,501
`IPR2017-01842
`Petitioner’s Updated Exhibit List
`
`
`CERTIFICATE OF SERVICE
`I hereby certify that, on January 9, 2018, I caused a true and correct copy of the
`
`foregoing materials:
`
` Petitioner’s Updated Exhibit List
` Petitioner’s List of Exhibits
` Exhibits 1129 and 1130
`
`to be served via email on the following counsel of record as listed in Patent
`
`Owner’s Mandatory Notices:
`
`Gerald B. Hrycyszyn, Registration No. 50,474
`GHrycyszyn-PTAB@wolfgreenfield.com
`
`Richard F. Giunta, Registration No. 36,149
`RGiunta-PTAB@wolfgreenfield.com
`
`Edmund J. Walsh, Registration No. 32,950
`EWalsh-PTAB@wolfgreenfield.com
`
`Wolf, Greenfield & Sacks, P.C.
`600 Atlantic Avenue
`Boston, Ma 02210
`
`
`Respectfully Submitted,
`
`/Michael Smith/
`
`___________________________
`Michael H. Smith
`Registration No. 71,190
`
`1
`
`
`
`U.S. Patent 7,893,501
`IPR2017-01842
`Petitioner’s Updated Exhibit List
`
`
`PETITIONER’S LIST OF EXHIBITS FOR
`IPR2017-01842
`
`Exhibit
`
`Description
`
`1101
`
`U.S. Patent No. 7,893,501
`
`1102
`
`Declaration of Stanley R. Shanfield, Ph.D. Regarding U.S. Patent
`No. 7,893,501, Claims 5, 6, 12, 13, 15, 19, and 21 (“Shanfield
`Decl.”)
`
`1103
`
`Applicant’s Amendment and Response dated August 6, 2010
`
`1104
`
`U.S. Patent Publication No. 2002/0145156 to Igarashi et al.
`(“Igarashi”)
`
`1105
`
`U.S. Patent No. 5,960,270 to Misra et al. (“Misra”)
`
`1106
`
`1107
`
`1108
`
`1109
`
`1110
`
`1111
`
`1112
`
`1113
`
`1114
`
`J. Plummer et al., Silicon VLSI Technology: Fundamentals,
`Practice and Modeling, (1st ed. 2000)
`
`U.S. Patent Publication No. 2002/0000611 to Hokazono et al.
`(“Hokazono”)
`
`U.S. Patent No. 6,228,777 (“Arafa”)
`
`U.S. Patent No. 6,406,963 to Woerlee et al. (“Woerlee”)
`
`J. Rabaey et al., Digital Integrated Circuits, at 40-44 (2d ed. 2003)
`
`S. Kang and Y. Leblebici, CMOS Digital Integrated Circuits:
`Analysis and Design, (2d. ed. 2003)
`
`K. Maex, Simply irresistible silicides, Physics World, at 35-39
`(Nov. 1995)
`
`Notice of Allowance dated October 15, 2010
`
` U.S. Patent No. 6,444,566 to Tsai et al. (“Tsai”)
`
`i
`
`
`
`U.S. Patent 7,893,501
`IPR2017-01842
`Petitioner’s Updated Exhibit List
`
`
`Description
`
`Fumio Shimura, Semiconductor Silicon Crystal Technology, at 104-
`112 (1989) (“Shimura Textbook”)
`
`J. Moon et al., A New LDD Structure: Total Overlap with
`Polysilicon Spacer (TOPS), IEEE Electron Device Letters, Vol. 11,
`No. 5, at 221-223 (May 1990)
`
`Exhibit
`
`1115
`
`1116
`
`1117
`
`D. Baglee et al., Reduced Hot-Electron Effects in MOSFET’s with
`an Optimized LDD Structure, IEEE Electron Device Letters, Vol.
`EDL-5, No. 10, at 389-391 (Oct. 1984)
`1118 W.O. Publication No. 2002/043151 with certified English
`translation (“Shimizu”)
`
`1119
`
`1120
`
`1121
`
`1122
`
`1123
`
`1124
`
`1125
`
`1126
`
`M. Green et al., Ultrathin (<4 nm) SiO2 and Si-O-N gate dielectric
`layers for silicon microelectronics: Understanding the processing,
`structure, and physical and electrical limits, J. Appl. Phys., Vol.
`90, No. 5, at 2057-2121 (Sep. 1, 2001)
`
`E. Gusev et al., Growth and characterization of ultrathin nitride
`silicon oxide films, IBM J. Res. And Dev., Vol. 43, No. 3, at 265-
`286 (May 3, 1999)
`
`H. Wong, Beyond the conventional transistor, IBM Journal of
`Research and Development, Vol. 46, No. 2/3, at 133-168
`(March/May 2002)
`
`U.S. Patent No. 6,509,234
`
`U.S. Patent No. 5,726,479
`
`U.S. Patent No. 6,512,266
`
`U.S. Patent No. 6,806,584
`
`Togo, M. et al. “Low Leakage and High Reliability 1.5 nm SiON
`Gate-Dielectric Using Radical Oxynitridation for Sub-0.1 µm
`
`ii
`
`
`
`U.S. Patent 7,893,501
`IPR2017-01842
`Petitioner’s Updated Exhibit List
`
`
`Exhibit
`
`Description
`CMOS,” 2000 Symposium on VLSI Technology Digest of
`Technical Papers (2000) (“Togo”)
`
`1127
`
`1128
`
`Mizuno, T. et al., “Hot-Carrier Injection Suppression Due to the
`Nitride-Oxide LDD Spacer Structure”, IEEE Trans. Electron Dev.,
`Vol. 38, No. 3, March, 1991 (“Mizuno”)
`
`High k dielectrics – Current status and Materials Properties
`Considerations, Wilk, G.D., et al., J. App. Phy. Vol. 89, No. 10,
`May 15, 2001
`
`1129
`
`December 19, 2017 Conference Call Transcript
`
`1130
`
`Infringement contentions dated February 1, 2017 for U.S. Patent
`7,893,501 from Godo Kaisha IP Bridge 1 v. Xilinx, Inc., Case No.
`Case No. 2:17-cv-00100 (E.D. Tex.)
`
`
`
`
`iii
`
`