UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________________________________
`
`TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
`Petitioner
`
`v.
`
`GODO KAISHA IP BRIDGE 1
`Patent Owner.
`
`Case IPR2017-018411
`
`REPLY DECLARATION OF STANLEY R. SHANFIELD, PH.D.
`
`1 Case IPR2017-01842 has been consolidated with this proceeding.
`
`TSMC 1027
`TSMC v. GODO KAISHA
`IPR2017-01841
`
`
`____________________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________________________________
`
`TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
`Petitioner
`
`v.
`
`GODO KAISHA IP BRIDGE 1
`Patent Owner.
`
`Case IPR2017-018411
`
`REPLY DECLARATION OF STANLEY R. SHANFIELD, PH.D.
`
`1 Case IPR2017-01842 has been consolidated with this proceeding.
`
`TSMC 1027
`TSMC v. GODO KAISHA
`IPR2017-01841
`
`
`
`U.S. Patent 7,893,501
`IPR2017-01841
`Reply Declaration of Stanley R. Shanfield, Ph.D.
`
`
`
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`I, Stanley R. Shanfield, Ph.D., declare as follows:
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`1. My name is Stanley R. Shanfield. I have been retained by counsel for
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`Taiwan Semiconductor Manufacturing Company, Ltd. to serve as a technical
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`expert in this inter partes review proceeding.
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`2. My background is set forth in paragraphs 2-12 of my initial
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`Declaration in this proceeding (Ex. 10022). As I explained in paragraphs 2-12 and
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`30-32 of my initial Declaration, I would have been a person with at least ordinary
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`skill in the art of U.S. Patent No. 7,893,501 (the “’501 patent”) as of the time of its
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`alleged invention.
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`3.
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`Since my prior declaration, I have reviewed Patent Owner’s
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`Preliminary Responses dated November 7, 2017, Patent Owner’s district court
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`infringement contentions (Ex. 1021), the Board’s Decision to Institute dated
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`February 6, 2018, the transcript of my deposition on March 27, 2018 and March
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`28, 2018 (Exs. 2009 and 2010), the Patent Owner’s Response dated April 20, 2018,
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`the Declaration of Dr. Alexander D. Glew (Ex. 2007), the transcript of Dr. Glew’s
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`deposition (Ex. 1024), and the exhibits submitted in connection with the forgoing.
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`2 Unless otherwise specified with the “-01842” prefix, references to exhibits and
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`papers herein are to those filed in Case IPR2017-01841.
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`Reply Declaration of Stanley R. Shanfield, Ph.D.
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`I confirm that everything I included in my prior declaration, and all of the
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`testimony given during my deposition on March 27, 2018 and March 28, 2018
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`remain true to the best of my knowledge. I have been asked to provide expert
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`testimony in this declaration in reply to issues raised by the Patent Owner’s
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`Response (“Response”) and the Declaration of Alexander D. Glew (Ex. 2007).
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`4.
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`Specifically, I understand that Patent Owner again argues that the
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`“active region” should be limited to a single transistor. As I will discuss, there is
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`nothing in the ’501 patent or any other evidence I have reviewed that supports such
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`a narrow interpretation.
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`5.
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`I also understand that Patent Owner again argues that the Fifth
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`Embodiment described in Igarashi does not teach shallow trench isolation (“STI”)
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`regions forming an active region and that the Petition relies on Woerlee only for
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`the location of the STI regions, not formation of STI regions in Igarashi’s fifth
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`embodiment. As I explained in my initial Declaration, a POSITA would have
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`understood that the disclosure of the features in Igarashi common to its different
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`illustrations—including the STI regions—are applicable to the Fifth Embodiment
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`shown in, for example, Figure 12. See e.g., Ex. 1002, ¶60 (“A POSITA would
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`have understood that the disclosure of the features in Igarashi common to different
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`illustrations are applicable to the embodiment shown in Figure 12 because the
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`Reply Declaration of Stanley R. Shanfield, Ph.D.
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`same reference numerals are used to describe common features of Igarashi’s
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`disclosure.”) Moreover, I also explained that it would have been obvious to apply
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`Igarashi’s undisputed teaching of an active region to the Fifth Embodiment. See
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`e.g., Ex. 1002, ¶75 (“[I]t would have been obvious to apply Woerlee’s teachings to
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`Igarashi by forming Igarashi’s active region in the substrate and defining it with
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`STI regions that divide the active region.”)
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`6.
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`I provide further explanation below regarding these issues, with which
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`I disagree with the Patent Owner and Dr. Glew.
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`
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`I.
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`Patent Owner’s Interpretation of “an active region made of a
`semiconductor substrate” is Inappropriately Narrow
`7.
`In its Response, Patent Owner claims that “there is no dispute that
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`under BRI, ‘an active region made of a semiconductor substrate’ is ‘an area of the
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`semiconductor substrate defined by an isolation region where the transistor is
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`formed.’” Response, 26. PO then advances an unduly narrow interpretation of this
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`proposed construction that seeks to limit the active region to having only a single
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`transistor, as it sought to do through a different construction in the POPR, which
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`the Board properly rejected. Response 74; POPR, 25, 29; DI, 9. Nothing in the
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`’501 patent or prior art requires such a one-to-one correspondence. Under PO’s
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`Reply Declaration of Stanley R. Shanfield, Ph.D.
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`inappropriately narrow interpretation, PO’s proposed construction for “an active
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`region made of a semiconductor substrate” is indeed disputed.
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`8.
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`First, Patent Owner already tried to advance its narrow view of an
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`“active region” in the POPR, proposing the following construction: “a region of a
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`semiconductor substrate dedicated to the MISFET and defined by isolation regions
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`that isolate the MISFET from other transistors formed in the substrate.” POPR, 25.
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`Patent Owner then (as it does again in the Response) further interpreted its
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`construction to require a single transistor. E.g., POPR, 29 (arguing the “‘active
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`region’ refers to a region dedicated to a single transistor”) (emphasis original);
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`Response, 74 (arguing “active region refers to a region in which a single transistor
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`is formed”). The Board properly rejected this position in the DI, highlighting
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`examples of active regions in the prior art having more than one transistor:
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`“For example, Plummer describes that “regions between these
`[isolation] layers, where transistors will be built, are called the ‘active’
`regions of the substrate” (Ex. 1008, 53), and Rabaey describes “active
`regions” as “the regions where transistors will be constructed” (Ex.
`1010, 42). Nothing about these descriptions connotes a requirement
`for a one-to-one correspondence of active regions-to-transistors, as
`Patent Owner contends.”
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`DI, 9 (emphasis added).
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`Reply Declaration of Stanley R. Shanfield, Ph.D.
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`9.
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`Now in its Response, Patent Owner has merely reworded its prior
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`construction and still attempts to interpret the new construction in the same way
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`already rejected by the Board. That is, Patent Owner is forcing an additional “one-
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`to-one correspondence” requirement into its interpretation of an “active region”
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`(compare “active region” as “a region of a semiconductor substrate dedicated to
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`the MISFET and defined by isolation regions that isolate the MISFET from other
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`transistors formed in the substrate,” POPR, 25, with “an active region made of a
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`semiconductor substrate” as “an area of the semiconductor substrate defined by an
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`isolation region where the transistor is formed,” Response, 26 (emphasis
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`added)).3
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`10.
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`Second, I do not agree with Patent Owner’s construction as Patent
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`Owner interprets it. As noted above, Patent Owner mistakenly claims that there is
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`3 Patent Owner’s Responses in this proceeding and in related IPR2017-01843 also
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`make clear its constructions are driven by attempting to avoid the prior art because
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`Patent Owner offers constructions for different terms in each Response, despite
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`those Responses both addressing the same challenged patent and claims. Compare
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`IPR2017-01841 Response (construing only the term “active region made of a
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`no dispute as to this construction and that the only dispute between the parties
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`relates to whether the claim requirement that “the MISFET includes: an active
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`region” is met by the prior art relied upon in the grounds. Response, 26-27. To
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`support this assertion, Patent Owner adopts language similar to that used in the
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`Petition and during my deposition, but then proposes interpreting this language in
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`the same manner as its previously rejected construction. Id., 27-28. This unilateral
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`statement by Patent Owner does not signal Petitioner’s agreement with the
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`incorrect interpretation that an active region contains only one transistor. There is
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`nothing in the ’501 patent or prior art that prohibits multiple transistors from being
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`formed in an active region, or that requires each transistor to be isolated from any
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`other transistor.
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`11. Third, Patent Owner cannot reconcile its incorrect interpretation with
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`its own infringement contentions in the co-pending litigation, which identify an
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`alleged “active region” having multiple transistors and which were made of record
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`in this proceeding months before Patent Owner filed its response. As highlighted
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`semiconductor substrate”) with IPR2017-01843 (construing only the term “silicon
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`nitride film”).
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`by Patent Owner’s infringement contentions, the alleged “active region” shown in
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`blue contains at least four transistors:
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`
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`
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`Ex. 1021, 32.
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`12. Patent Owner’s inconsistent positions on an “active region” infect its
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`arguments throughout its Response. For example, Patent Owner argues that the
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`MISFET must “include” the entirety of the active region. Response, 16 (“the plain
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`language and structure of the claims require that it is the MISFET that is the larger
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`whole that ‘includes’ the entirety of the active region and not the other way
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`around.”) This is simply another indirect way of Patent Owner rearguing its
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`rejected construction requiring a one-to-one correspondence of active regions-to-
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`transistors and is directly contradicted by Patent Owner’s own district court
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`infringement allegations, which allege the opposite. Patent Owner cannot have it
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`both ways.
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`13. Fourth, as recognized by the Board, the Petition and the
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`semiconductor textbooks cited in the Petition consistently recognize the “active
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`region” as the region where transistors are formed. For example:
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` “The active regions are found between the shallow trench isolation regions
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`(STI). (See Rabaey at 42-43 (Ex-1010).) The active regions are where the
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`transistors are formed. (Id. at 42.) The source and drain regions (green), the
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`channel (area between the source and drain regions), and the well (‘N Well’
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`and ‘P Well’) are formed in regions of the active regions. (Plummer at 86
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`(Ex-1008).)” Petition, 7 (emphasis added).
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` “[T]he manufacturing process for a MISFET ‘starts with the definition of the
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`active regions—these are the regions where transistors will be constructed.
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`All other areas of the die will be covered with a thick layer of silicon dioxide
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`(SiO2) called the field oxide. This oxide acts as the insulator between
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`neighboring devices, and it is either grown (as in the process of Figure 2-1)
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`Reply Declaration of Stanley R. Shanfield, Ph.D.
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`or deposited in etched trenches (Figure 2-2)—hence, the name trench
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`insulation.’” Petition, 26 (quoting Ex-1010); see also Petition, 8; DI, 8-9.
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`
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`And indeed, a region bounded by isolation regions where transistors are
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`formed is precisely what is shown in Igarashi, as I identified in my initial
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`declaration:
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` “A POSITA would have understood that Igarashi discloses an active region
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`made of the semiconductor substrate 1 because Igarashi discloses: ‘First, an
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`insulating film for isolating elements is formed on a silicon semiconductor
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`substrate 1. Element isolation is performed using methods such as the
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`LOCOS method or the trench method. Thereafter, ion implantation is
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`performed to the active element region for forming the well and controlling
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`the threshold value.’ (Igarashi at [0068] (Ex-1004).)” Ex. 1002, ¶66.
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` “The use of the ‘trench method’ confirms the ‘active element region’ (active
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`region) is made of the semiconductor substrate 1 because according to the
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`trench method the active region is formed in the substrate and defined by the
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`STI regions.” Ex. 1002, ¶66.
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`14. Fifth, Patent Owner’s reliance on the exemplary embodiments of the
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`’501 to argue that “[e]very embodiment in the specification includes a single
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`transistor in an active region bounded by isolation regions” does not compel an
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`Reply Declaration of Stanley R. Shanfield, Ph.D.
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`interpretation of “active region” having only a single transistor. E.g., Response,
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`28-29, 74. For example, where Patent Owner cites to the description of Figure 1
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`(Response, 28, citing Ex. 1001, 3:21-23), that figure shows only “a cross-sectional
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`view illustrating a semiconductor device according to a first embodiment of the
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`present invention.” Ex. 1001, 3:19-21. Where Patent Owner cites to various
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`descriptions of manufacturing process steps (e.g., Response, 28, citing Ex. 1001,
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`6:22-26, 9:38-39, 10:53-54, 12:25-28), those steps are directed to “the first
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`embodiment,” “modified example[s]” of the first embodiment, or “a second
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`embodiment.” Ex. 1001, 6:18-21, 9:32-35, 10:48-50, 12:21-24. Critically, nothing
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`in the specification or claims of the ’501 patent states that the “active region” can
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`only contain a single transistor.
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`15. Moreover, the cited figures in the ’501 patent only show a “cross-
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`sectional” (i.e., from the side) view of the example embodiments (the “plane view”
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`of Figure 9 is directed to a different, “third embodiment”). Ex. 1001, 2:47-3:7,
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`Figs. 1-8; see also, Ex. 1024, 80:2-81:5 (confirming that “the views of the first
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`embodiment and its modifications are all cross-sectional views,” which “merely
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`show[] what can be viewed in one cutaway.”) These cross-sectional perspectives
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`do not foreclose on the existence of additional transistors within the active regions.
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`Because neither the specification nor the claims of the ’501 patent limit the “active
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`region” to a one-to-one correspondence of active regions-to-transistors, Patent
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`Owner cannot rely on its presumptions about certain exemplary embodiments
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`depicted in the drawings to support a narrowing interpretation of the “active
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`region.”
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`16. Finally, Patent Owner’s interpretation of an “active region” does not
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`make technical sense. For example, all functional MOSFET transistors have an
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`active region and Dr. Glew cites no evidence to the contrary. A POSITA would
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`understand that the active region is electrically isolated from other active regions
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`with isolation regions. Nothing about this understanding precludes multiple
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`transistors from being formed within the active region. In the case where two
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`transistors share a drain, electrical isolation is not required between the transistors
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`and both transistors are formed within the same active region.
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`17. Other examples in the prior art confirm the understanding that more
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`than one transistor can exist in an active region. For example, U.S. Patent No.
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`5,389,810 to Agata (“Agata”) describes a “plurality of pairs of MOSFETs 10 []
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`arranged in a row in the active region 2.” Ex. 1025, 5:18-19. First MOSFET 10a
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`and second MOSFET 10b make up an example pair which, as shown, share
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`“source region 11.” Id., 5:37-38. Critically, both MOSFET 10a and MOSFET 10b
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`(annotated below in green) are formed and exist in the same “active region 2,”
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`(annotated below in blue) as shown in the annotated Figure 2 of Agata below. Id.,
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`5:33-37.
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`
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`Id., Figure 2.
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`18.
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`Isolation regions are designed to isolate one active region from
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`another active region, not each transistor from every other transistor. That is, the
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`isolation regions do not necessitate a one-to-one correspondence of active regions-
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`to-transistors as Patent Owner asserts. For example, when observing a plan view
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`laying out a configuration of semiconductor devices, it becomes evident that an
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`active region can include more than one transistor. U.S. Patent No. 8,618,607 to
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`Rashed et al. (“Rashed”) illustrates such a plan view, describing a device that
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`Reply Declaration of Stanley R. Shanfield, Ph.D.
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`“includes a continuous active region defined in a semiconducting substrate, first
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`and second transistors formed in and above the continuous active region.” Ex.
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`1026, Abstract. Rashed even acknowledges that the prior art teaches the formation
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`of multiple devices in a single active region, as shown for example in its Figure 1.
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`Ex. 1026, 1:55-58 (“A plurality of PFET devices 20P1-2 are formed in and above
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`the active region 12PA and a plurality of PFET devices 20P3-4 are formed in and
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`above the active region 12PB.”)
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`19. Dr. Glew states that semiconductor devices have been made without
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`isolation regions and cites a single patent from the 1980’s stating that a retrograde
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`doping profile may be used “with or without trench dielectric isolation structures.”
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`E.g., Ex. 2007, ¶¶112-113, citing Ex. 2014 at 5:41-47. These examples are
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`misleading. First, even transistors that do not use isolation regions such as STI
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`still have active regions—otherwise, the transistors would simply not function.
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`The absence of an isolation region does not signify the absence of an active region.
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`Second, by the time of the alleged invention in 2003, virtually all transistors
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`included isolation regions. A POSITA at the time of the alleged invention would
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`not have understood Igarashi to be implemented in a manner that omitted isolation
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`regions or structures (such as STI) because: (i) the transistors commonly used by
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`then were too small for spacing alone to be a functional alternative to isolation
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`regions or structures (such as STI); and (ii) Igarashi expressly discloses the use of
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`isolation regions and such isolation regions would have been obvious in view of
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`Woerlee. Ex. 1002, ¶¶66-67; Ex. 1024, 111:18-25 (admitting that using spacing
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`rather than isolation “would not be a typical solution” for memory cells in the 2003
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`timeframe).
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`20. Accordingly, Patent Owner’s interpretation of an “active region” is
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`inappropriately narrow, forecloses substantial portions of the technical field, and is
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`purely designed to escape the overwhelming prior art.
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`II.
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`Igarashi and Woerlee Disclose the Claimed “Active Region”
`21. Patent Owner again incorrectly argues that the Fifth Embodiment
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`described in Igarashi, itself, does not teach STI regions forming an active region.
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`Response, 37. The Board has already rejected this argument: “[W]e find it is clear
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`from Igarashi that the disclosure of ‘active element region[s]’ discussed in
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`paragraph 68 with respect to the ‘First Embodiment’ is equally applicable to the
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`‘Fifth Embodiment’ upon which Petitioner primarily relies.” DI, 18-20.
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`A.
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`Patent Owner’s Imagined Inherency Argument Mischaracterizes my
`testimony
`22. Patent Owner attempts to mischaracterize my deposition testimony,
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`claiming that I have advanced a “new” inherency argument by suggesting that
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`isolation regions were present in that embodiment because they were necessary for
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`the device to work. Response, 12.
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`23. The Response asserts that “[Dr.] Shanfield testified that every
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`embodiment must be isolated using LOCOS or the trench method to ‘have a
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`functional integrated circuit.’ Ex.-2009, 98:10-13.” Response, 45. But in the
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`context of the surrounding testimony omitted from the Response (bracketed
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`below), it is clear that my testimony is directed to the understanding of one of
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`ordinary skill in the art when reading Igarashi and not inherency:
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`“[Someone of skill in the art, reading this, would understand that what
`Igarashi means is, I'm going to describe the method for manufacturing
`the semiconductor device of the first embodiment. But the following
`description of the manufacturing method -- the major process for
`forming the silicon nitride film -- will be described and other processes
`will be described without referring to the drawings, and the process is -
`-
`they describe, for example,
`the
`isolation applied
`to other
`embodiments. Clearly isolation is required in any embodiment.
`And so, for example, it says ‘Element isolation is performed using
`methods such as LOCOS or trench method.’]
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`“A person of skill in the art would understand that that applies to all
`the embodiments, because you wouldn't have a functional integrated
`circuit without it.”
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`Ex. 2009, 97:19-98:13; see also id., 99:6-21 (“Someone of skill in the art will
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`understand there has to be an isolation. LOCOS and the trench method were the
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`alternatives at the time, and, of course, [Igarashi’s] got to be referring to every
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`embodiment. It couldn’t be interpreted any other way.”)
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`24. Patent Owner also cites the following testimony to support its own
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`invented inherency argument: “And that’s understood to apply to all the
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`embodiments. There’s no way electrically it can be not isolated.’)” Response, 45,
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`citing Ex. 2009, 100:24-101:10 (emphasis by Patent Owner). But again, when my
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`testimony is taken in context, my response is clearly intended only to correct
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`Patent Owner’s misinterpretation of Igarashi: “[No, but it -- that's -- if you're
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`attempting to imply that it doesn't have isolation, then it's a misreading of the end
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`of paragraph 68. It says ‘Element isolation is performed using methods such as
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`LOCOS or the trench method.’] And that’s understood to apply to all the
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`embodiments. There’s no way electrically it can be not isolated.” Ex. 2009, 101:3-
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`7 (omitted testimony in brackets). In other words, and consistent with both the
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`Petition and my initial declaration, I am only confirming that a person of ordinary
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`skill, when reading Igarashi, would have understood that the disclosure of the
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`features in Igarashi that are common to different illustrations are applicable to the
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`embodiment shown in Figure 12 because the same reference numerals are used to
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`describe common features of Igarashi’s disclosure.
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`25. Moreover, inherency is irrelevant in this case because—putting aside
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`the fact that neither Petitioner nor I have ever raised an inherency argument in this
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`case—Igarashi expressly discloses an active region: “First, an insulating film for
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`isolating elements is formed on a silicon semiconductor substrate 1. Element
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`isolation is performed using methods such as the LOCOS method or the trench
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`method. Thereafter, ion implantation is performed to the active element region for
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`forming the well and controlling the threshold value.” Ex. 1002, ¶66, citing Ex.
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`1004, [0068] (emphasis added).
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`26. My initial declaration is also clear that a “POSITA would have
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`understood that the disclosure of the features in Igarashi common to different
`
`illustrations are applicable to the embodiment shown in Figure 12 because the
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`same reference numerals are used to describe common features of Igarashi’s
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`disclosure.” Ex. 1002, ¶60. For example, “semiconductor substrate 1” where the
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`active region is formed is a common feature between Figure 1 (Embodiment 1) and
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`Figure 12 (Embodiment 5). I note that Dr. Glew admitted that he used the same
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`approach to interpret the ’501 patent, admitting that he based his assessment of the
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`’501 patent’s first embodiment in the 501 patent’s third embodiment because “it
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`uses the same Item No. 2, which indicates to me that it is going to be substantially
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`similar to the other uses of Item 2.” Ex. 1024, 81:8-24. This uniform numbering
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`U.S. Patent 7,893,501
`IPR2017-01841
`Reply Declaration of Stanley R. Shanfield, Ph.D.
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`scheme for common features (which also includes elements numbered 2-6) is
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`undeniably evident when the two figures in Igarashi are viewed side by side.
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`
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`Figures 1 and 12 of Igarashi showing a uniform numbering scheme for common
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`features (Ex. 1004)
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`This same reasoning applies to common features, like the isolation regions, even if
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`they are not specifically shown in the figures. As noted in my initial declaration,
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`where features differ between figures, the differences are described in the
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`disclosure of Igarashi. Ex. 1002, ¶60; see also, Ex. 1024, 112:1-15 (confirming
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`that a POSITA at the relevant time would not rely on spacing the devices in Figure
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`12 of Igarashi so far apart that isolation would not be needed).
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`27. Moreover, my initial declaration showed that Igarashi’s isolation
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`region teachings were applicable to its Figure 12 embodiment. Specifically, I cite
`
`Figure 12, which shows the “semiconductor substrate 1.” Ex. 1002, ¶66. Then, I
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`explained that a POSITA would have understood that the semiconductor substrate
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`U.S. Patent 7,893,501
`IPR2017-01841
`Reply Declaration of Stanley R. Shanfield, Ph.D.
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`1 in Figure 12 has an active region because Igarashi expressly discloses an “active
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`element region” made of the semiconductor substrate 1. Ex. 1002, ¶66; Ex. 1010,
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`42-43.
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`28. Accordingly, both the Petition and I have been clear and consistent
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`throughout this proceeding: Igarashi discloses the “active region” of the challenged
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`claims in connection with its Fifth Embodiment. Moreover, as discussed below in
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`Section III.D, I also demonstrated it would have been obvious to form the active
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`region disclosed in Igarashi in semiconductor substrate 1 of Igarshi’s Fifth
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`Embodiment in view of the teachings of Woerlee.
`
`Igarashi Shows a MISFET that Includes an “Active Region”
`B.
`29. A person of ordinary skill would have viewed the region between the
`
`two STI in Igarashi where the two transistors are formed as an “active region”
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`formed between those two STI. As noted in the my initial declaration: “The use of
`
`the ‘trench method’ confirms the ’active element region’ (active region) is made of
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`the semiconductor substrate 1 because according to the trench method the active
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`region is formed in the substrate and defined by the STI regions. Ex. 1002 ¶66,
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`citing Ex, 1010, 42-43 (explaining that the manufacturing process for a MISFET
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`“starts with the definition of the active regions—these are the regions where
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`transistors will be constructed. All other areas of the die will be covered with a
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`U.S. Patent 7,893,501
`IPR2017-01841
`Reply Declaration of Stanley R. Shanfield, Ph.D.
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`thick layer of silicon dioxide (SiO2) called the field oxide. This oxide acts as the
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`insulator between neighboring devices, and it is either grown (as in the process of
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`Figure 2-1) or deposited in etched trenches (Figure 2-2)—hence, the name trench
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`insulation.”) As discussed in Section II above with respect to Agata and Rashed
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`(and Patent Owner’s district court infringement contentions), it is visibly clear that
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`Igarashi discloses the claimed “active region” of the ’501 patent.
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`30. As discussed below, I was asked during deposition whether this active
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`region would be considered one active region or two active regions.
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`31.
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`In either view, Igarashi’s disclosure meets the claim limitations
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`because the MISFETs in either case include an active region bounded by STI.
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`Under the first view, each MISFET includes an active region because each
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`transistor is formed in the active region between the STI. There is nothing that
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`precludes multiple transistors, each with their own channel, from being formed in
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`the active region, nor does the claim require that each transistor have its own active
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`region that is separated from other active regions by isolation regions. See Section
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`II, above; Ex. 1025. I note that Dr. Glew admitted that the term “includes” in
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`claim 1 means “that it has at least these features.” Ex. 1024, 94:20-95:7. Under
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`U.S. Patent 7,893,501
`IPR2017-01841
`Reply Declaration of Stanley R. Shanfield, Ph.D.
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`the second view, each transistor includes an active region because there are two
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`transistors and two active regions.
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`32. Patent Owner’s (and Dr. Glew’s) arguments against Igarashi’s “active
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`region” are internally inconsistent. For example, in its Response, Patent Owner
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`first argues that the entire region bounded by isolation regions is not the formation
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`region for any transistors. Response, 17-18 (“In the Petitions’ modified-Igarashi
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`Fig. 12, the entire region of the substrate bounded by the alleged isolation region is
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`not the formation region for any MISFET. Ex.-2007, ¶145.”) Yet, in the very next
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`sentence, Patent Owner concedes that this region is the formation region for at
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`least two transistors. Response, 18 (“It is undisputed that there are at least two
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`transistors in Igarashi’s Fig. 12.”).
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`33. PO’s attempt to argue that Igarashi’s Figure 12 embodiment somehow
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`does not have an active region because it is a memory device also fails. Response,
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`33-34. When asked to provide examples of known devices having “active
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`regions,” Dr. Glew admitted that there were various types of devices—including
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`logic and memory devices—that would have “active regions.” Ex. 1024, 97:21-
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`98:7 (“Q. Could you provide some examples of the types of devices you're familiar
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`with from that timeframe that had active regions? A. Starting at the bottom of
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`Paragraph 30 and paragraphs 63 through 66 I describe a number of references that
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`U.S. Patent 7,893,501
`IPR2017-01841
`Reply Declaration of Stanley R. Shanfield, Ph.D.
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`use this term consistent with my understanding. Each of these references describes
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`various types of devices that would have such regions. One could generally
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`characterize and say logic and memory devices, as well as other types
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`additionally.”) Dr. Glew also confirmed in his declaration, that Igarashi’s Fifth
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`Embodiment shown in Figure 12 “comprises a portion of a memory cell”—
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`precisely the type of device that Dr. Glew would expect to have an “active region.”
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`Ex. 2007, ¶¶91-92; see also, Ex. 1024, 111:11-17 (“Q. You state in Paragraph 92
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`that Igarashi's fifth embodiment comprises a portion of a memory cell formed by
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`two interconnected MOS transistors. Is that still your testimony? A. Yes, I
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`understand that this is what I believe Igarashi to be.”)
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`Patent Owner’s Attacks on my Testimony are Purely a Distraction
`C.
`34. Patent Owner desperately attacks my deposition testimony in its
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`Response for allegedly not answering the question of whether Igarashi shows one
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`active region or two active regions. Specifically, Patent Owner claims that
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`“Petitioner’s expert could not answer a simple question—was it his position that
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`there is one active region or two in the Petitions’ modified-Igarashi Fig. 12.”
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`Response, 13-14. However, I repeatedly tried to explain how this was not a
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`distinction relevant to the challenged claims or my analysis. When Patent Owner
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`persisted in trying to get me to say it was one active region or two, I testified
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`U.S. Patent 7,893,501
`IPR2017-01841
`Reply Declaration of Stanley R. Shanfield, Ph.D.
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`truthfully that this was not a question that made sense technically. I was not
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`unable or unwilling to answer the question. I repeatedly and patiently answered
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`Patent Owner’s questions over two full days of depositi
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