`
`I IIIII IIIIIIII Ill lllll lllll lllll lllll lllll lllll lllll lllll 111111111111111111
`
`US008618607B 1
`
`(10)Patent No.:US 8,618,607 Bl
`
`c12) United States Patent
`(45)Date of Patent:
`Dec. 31, 2013
`
`
`Rashed et al.
`
`(58)Field of Classification Search
`
`(54)SEMICONDUCTOR DEVICES FORMED ON A
`
`USPC ................. 257/204, 359, 369, 379, 532, 536,
`
`
`
`
`
`CONTINUOUS ACTIVE REGION WITH AN
`
`
`257/E21.564, 568, 602, 656, 23.144, 152,
`
`ISOLATING CONDUCTIVE STRUCTURE
`
`
`257/27.024, 26, 81, 97, 98, 107, 29.226,
`
`POSITIONED BETWEEN SUCH
`257/276
`
`SEMICONDUCTOR DEVICES, AND
`
`
`See application file for complete search history.
`METHODS OF MAKING SAME
`
`
`
`
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`(56)
`(75)Inventors: Mahbub Rashed, Santa Clara, CA (US);
`
`
`
`David Doman, Austin, TX (US); Marc
`
`
`Tarabbia, Pleasant Valley, NY (US);
`5,536,955 A * 7/1996 Ali ................................ 257/204
`
`
`
`Irene Lin, Los Altos Hills, CA (US);
`
`
`
`6,147,857 A * 11/2000 Worley et al. .............. 361/301.2
`Jeff Kim, San Jose, CA (US); Chinh
`
`
`
`6,558,998 B2 * 5/2003 Belleville et al. ............. 438/210
`
`
`Nguyen, Austin, TX (US); Steve Soss,
`
`
`
`
`7,189,602 B2 * 3/2007 Jiang et al. ....... 438/142
`
`Cornwall, NY (US); Scott Johnson,
`
`
`
`
`7,282,803 B2 * 10/2007 Cathelin et al. ............... 257 /7 58
`
`Wappingers Falls, NY (US); Subramani
`
`
`
`7,960,269 B2 * 6/2011 Lo et al ......................... 438/598
`
`
`
`8,421,158 B2 * 4/2013 Lin ............................... 257 /379
`
`Kengeri, San Jose, CA (US); Suresh
`
`
`
`
`8,453,094 B2 * 5/2013 Kornachuk et al. ........... 716/126
`
`
`Venkatesan, Malta, NY (US)
`
`
`
`8,471,391 B2 * 6/2013 Fox et al. ...................... 257 /776
`
`
`
`
`8,492,900 B2 * 7/2013 Lin et al. ....................... 257 /773
`
`
`
`
`2002/0063291 Al* 5/2002 Brown et al. ....... 257 /359
`
`
`
`2009/0101940 Al* 4/2009 Barrows et al. ............... 257 /204
`
`(73)Assignee: GLOBALFOUNDRIES Inc., Grand
`
`
`
`Cayman (KY)
`
`* cited by examiner
`( *) Notice: Subject to any disclaimer, the term ofthis
`
`
`
`- Michael Lebentritt
`
`Primary Examiner
`
`
`
`
`patent is extended or adjusted under 35
`
`
`(74)Attorney, Agent, or Firm - Williams, Morgan &
`
`
`U.S.C. 154(b) by O days.
`
`Amerson, P.C.
`
`(21)Appl. No.: 13/539,830
`
`(57)
`
`ABSTRACT
`
`(22)Filed:Jul. 2, 2012
`
`(2006.01)
`
`One illustrative device disclosed herein includes a continuous
`
`
`
`
`
`
`
`
`
`
`
`active region defined in a semiconducting substrate, first and
`
`
`second transistors formed in and above the continuous active
`
`
`
`
`region, each of the first and second transistors comprising a
`(51) Int. Cl.
`
`
`
`
`plurality of doped regions formed in the continuous active
`HOJL21/02
`
`
`
`
`
`region, a conductive isolating electrode positioned above the
`(52) U.S. Cl.
`
`
`
`
`
`
`continuous active region between the first and second tran­
`USPC .... 257/359; 257/369; 257/379; 257/E21.602;
`
`
`
`
`
`sistors and a power rail conductively coupled to the conduc­
`
`257/E21.656; 257/E23.144; 257/E23.152;
`tive isolating electrode.
`
`
`257/E27.029; 257/E27.081; 257/E29.226;
`257/E29.276
`
`
`
`
`36 Claims, 23 Drawing Sheets
`
`140H
`
`Metal 1
`
`183
`
`175
`
`I 120P2
`
`130A 120P3
`
`112P
`
`TSMC 1026
`TSMC v. GODO KAISHA
`IPR2017-01841
`
`

`

`U.S. Patent Dec. 31, 2013 Sheet 1
`of 23
`
`
`
`US 8,618,607 Bl
`
`20P1 20P2
`
`
`
`20P3 20P4
`
`30
`
`/ /�30
`' 12PB
`
`12PA
`
`12NA
`
`\
`
`'32P I 32P
`
`32N 32N
`
`/
`I
`I
`
`32P
`30, ..
`12NB
`
`I
`I
`I
`I
`I
`I
`I I I
`I
`I I I
`I
`•
`..
`114 I 22N3
`I
`22N4 I
`I I
`I
`I
`I
`I
`�I 1 ..
`�I
`
`I
`I
`
`14
`
`I
`I
`I
`I
`I
`+ ..
`/ I
`! I 22N1 22N2
`14
`I
`I
`1 ..
`I
`\
`\
`Cell 2
`Cell 1
`Art) Figure 1
`(Prior
`
`I
`
`I
`
`I
`
`I
`
`I
`
`I
`
`\
`
`

`

`U.S. Patent Dec. 31, 2013 Sheet 2 of 23
`
`
`
`US 8,618,607 Bl
`
`40H
`
`52H
`
`(
`I
`
`20P1
`12P. ·�
`
`20P2
`
`22N1
`
`14
`
`22N2
`
`52L/
`
`Art) Figure 2
`(Prior
`
`

`

`U.S. Patent Dec. 31, 2013
`Sheet 3 of 23
`
`
`
`US 8,618,607 Bl
`
`100·�.,.
`'····�
`120P1 120P2
`
`113.
`
`120P3 120P4
`
`'
`
`� 150PG
`
`130 ...
`132P
`
`112N
`
`\
`\
`
`�.
`
`142
`
`112P
`
`132P
`
`/� 112N
`
`132N
`
`1131
`
`150NG
`
`A
`+
`I
`/
`,/
`
`122N1 122N2
`
`t A
`/ /
`122N3 122N4
`
`Figure 3A
`
`

`

`U.S. Patent
`Dec. 31, 2013 Sheet 4 of 23
`
`
`
`US 8,618,607 Bl
`
`/140H
`
`�130
`120P3
`
`122N3
`
`113
`
`I
`I
`
`120P2
`
`113\
`
`142
`
`122N2
`
`113.
`
`150NG //
`
`Figure 38
`
`150PG
`
`120,.
`
`/140H
`
`122
`Figure 3C
`
`

`

`U.S. Patent Dec. 31, 2013
`
`
`Sheet 5 of 23
`
`
`
`US 8,618,607 Bl
`
`144 150PG
`144
`I
`
`/140H
`//
`
`120P2�"
`/�
`
`113'
`
`�'
`
`142
`
`/� 112N
`/
`I
`
`146 150NG
`
`146
`
`Figure 4A
`
`

`

`U.S. Patent Dec. 31, 2013
`
`
`Sheet 6 of 23
`
`
`
`US 8,618,607 Bl
`
`144 150PG
`
`140H
`/
`
`1200
`
`/130
`//120P3
`JI/
`
`120P2--
`
`,"'-
`
`148
`
`/-112N
`
`I 1 1220
`
`\
`
`146 150NG
`
`Figure 48
`
`

`

`U.S. Patent Dec. 31, 2013
`Sheet 7 of 23
`
`
`
`US 8,618,607 Bl
`
`150PG
`
`/140H
`
`
`
`1200 1200
`
`I
`I
`
`I
`I
`
`/112P
`
`1220 1220
`
`I
`I
`I
`
`146//150NG
`
`Figure 4C
`
`

`

`U.S. Patent
`
`
`Dec. 31, 2013 Sheet 8 of 23
`
`
`
`US 8,618,607 Bl
`
`190P(CA)
`190P(CA) 192P(CB)
`/140H
`
`/
`
`,-­'
`
`131P
`
`120S 120S 131P ·1200
`
`I
`
`1131 175
`\
`131 N 122D,\
`
`75
`122S 122S 131N
`/ 1220
`/112N
`
`/
`
`.�
`/�---...
`
`113/ 122N2/
`
`AL
`
`�.
`'·122N3
`
`_jA
`
`\
`\
`
`190N(CA)
`192N(CB) 190N(CA)
`
`I
`
`Figure SA
`
`

`

`U.S. Patent
`Dec. 31, 2013 Sheet 9 of 23
`
`
`
`US 8,618,607 Bl
`
`192N (CB)
`
`179
`
`177
`
`180
`
`Figure SA-A
`View "A-A"
`
`113
`
`

`

`U.S. Patent
`Dec. 31, 2013 Sheet 10 of 23
`
`
`
`US 8,618,607 Bl
`
`190N (CA)
`
`177
`
`182
`
`181
`
`180
`
`150NG
`
`Figure 5A-B
`View "B-B"
`
`113
`
`

`

`U.S. Patent
`Dec. 31, 2013 Sheet 11 of 23
`
`
`
`US 8,618,607 Bl
`
`182
`190N (C
`181
`
`180
`
`177
`
`90N (CA)
`
`175
`
`175
`
`150NG
`
`Figure 5A-C
`View "C-C"
`
`112N
`
`

`

`U.S. Patent Dec. 31, 2013 Sheet 12 of 23
`
`
`
`US 8,618,607 Bl
`
`184
`
`192P (CB)
`
`181
`
`180
`
`120P2
`
`1308
`130A 120P3
`
`Figure 58 112P
`
`

`

`U.S. Patent Dec. 31, 2013 Sheet 13 of 23
`
`
`
`US 8,618,607 Bl
`
`184
`
`181
`
`180
`
`[[]
`
`122N2
`
`130A 122N3
`
`Figure 5C 112N
`
`

`

`U.S. Patent Dec. 31, 2013 Sheet 14 of 23
`
`
`
`US 8,618,607 Bl
`
`140H
`
`Metal 1
`
`182
`
`180
`
`175
`
`120P2
`
`130A 120P3
`
`Figure 5D
`
`112P
`
`

`

`U.S. Patent
`Dec. 31, 2013 Sheet 15 of 23
`
`
`
`US 8,618,607 Bl
`
`140L
`
`Metal 1
`
`184
`
`183
`
`182
`
`175
`
`150NG
`
`122N2
`
`130A 122N3
`
`Figure SE
`
`112N
`
`

`

`U.S. Patent Dec. 31, 2013 Sheet 16 of 23
`
`
`
`US 8,618,607 Bl
`
`180
`
`120P2 120S
`
`1200 130A 120P3
`
`Figure 6A 112P
`
`

`

`
`U.S. Patent Dec. 31, 2013 Sheet 17 of
`23
`
`US 8,618,607 Bl
`
`182
`190N (C
`
`180
`
`122N2 122S
`
`1220
`
`130A 122N3
`
`Figure 68
`
`112N
`
`

`

`U.S. Patent Dec. 31, 2013 Sheet 18 of 23
`
`
`
`US 8,618,607 Bl
`
`140H
`
`Metal 1
`
`180
`
`175
`
`120P2
`
`120S
`
`Figure 6C
`
`112P
`
`

`

`U.S. Patent Dec. 31, 2013 Sheet 19 of 23
`
`
`
`US 8,618,607 Bl
`
`140L
`
`Metal 1
`
`180
`
`175
`
`120P2
`
`122S
`
`Figure 6D
`
`112N
`
`

`

`U.S. Patent Dec. 31, 2013 Sheet 20 of 23
`
`
`
`US 8,618,607 Bl
`
`182
`
`180
`
`120P2 1200
`
`1200
`
`Figure 7A
`
`112P
`
`

`

`U.S. Patent Dec. 31, 2013
`Sheet 21 of 23
`
`
`
`US 8,618,607 Bl
`
`192N (CB)
`
`180
`
`175
`
`122N2 1220
`
`1220
`
`130A 122N3
`
`Figure 78
`
`112N
`
`

`

`U.S. Patent Dec. 31, 2013 Sheet 22 of 23
`
`
`
`US 8,618,607 Bl
`
`140H
`
`Metal 1
`
`182
`
`175
`
`180
`
`175
`
`120P2
`
`1200
`
`120P3
`
`Figure 7C
`
`112P
`
`

`

`U.S. Patent Dec. 31, 2013 Sheet 23 of 23
`
`
`
`US 8,618,607 Bl
`
`140L
`
`Metal 1
`
`182
`
`181
`
`175
`
`1220
`
`Figure 7D
`
`112N
`
`

`

`
`
`US 8,618,607 Bl
`
`1
`
`BACKGROUND OF THE INVENTION
`
`2
`dummy gate structures that are provided in an attempt to
`
`
`
`SEMICONDUCTOR DEVICES FORMED ON A
`
`
`
`
`
`improve dimensional accuracy when forming the gate struc­
`
`CONTINUOUS ACTIVE REGION WITH AN
`
`tures 30 for the device 10.
`
`ISOLATING CONDUCTIVE STRUCTURE
`FIG. 2 depicts another illustrative prior art device 50. The
`
`
`
`POSITIONED BETWEEN SUCH
`
`
`
`device comprises illustrative PFET devices 20Pl and 20P2
`
`
`SEMICONDUCTOR DEVICES, AND
`
`formed above spaced apart active regions. The device 50 also
`METHODS OF MAKING SAME
`
`
`
`includes illustrative NFET transistors that are
`22Nl, 22N2
`
`
`also formed above spaced apart active regions. FIG. 2 depicts
`
`
`an illustrative relatively high voltage power rail 40H that is
`
`
`
`
`
`10 conductively coupled to the illustrative source regions (''S")
`1. Field of the Invention
`
`
`
`contacts of the PFET devices 20Pl, 20P2 via illustrative 52H.
`Generally, the present disclosure relates to the manufacture
`
`
`
`
`
`
`
`relatively low voltage Also depicted in FIG. 2 is an illustrative
`
`
`
`of sophisticated semiconductor devices, and, more specifi­
`
`
`power rail 40L that is conductively coupled to the source
`
`
`
`
`cally, to a plurality of semiconductor devices formed in and
`
`
`regions of the NFET devices 22Nl, 22N2 via illustrative
`
`
`
`above a continuous active region and a conductive isolating
`15 contacts
`52L.
`
`
`
`
`
`structure formed above the active region between the devices.
`With each new technology generation, all dimensions of
`
`
`
`
`2. Description of the Related Art
`
`
`
`the integrated circuit product are typically reduced. For
`The fabrication of advanced integrated circuits, such as
`
`
`
`
`
`
`
`example, as device dimensions are reduced, the lateral spac­
`
`
`
`
`CPU's, storage devices, ASIC's (application specific inte­
`
`
`
`ing 39 (see FIG. 1) between adjacent active regions, e.g., the
`
`
`
`
`
`grated circuits) and the like, requires the formation of a large 20
`
`
`
`
`
`the active regions lateral spacing 39 between 12PA and 12PB,
`
`
`
`number of circuit elements in a given chip area according to
`
`
`
`
`also decreases. In some cases, the lateral spacing 39 may be as
`
`
`
`
`a specified circuit layout. Field effect transistors (FETs) rep­
`
`
`
`little as about 40 nm. As this lateral spacing decreases, there
`
`
`
`resent one important type of circuit element that substantially
`
`
`
`
`is an increased risk of creating short circuits between the two
`
`
`
`
`determines performance of the integrated circuits. Field
`
`
`
`
`adjacent cells. Of course, one way to rectify this problem
`
`
`
`
`effect transistors are typically either NFET devices or PFET 25
`
`
`would be to simply increase the spacing between adjacent
`
`
`
`
`devices. During the fabrication of complex integrated cir­
`
`
`
`
`active regions. However, such an approach would be very
`
`
`
`
`cuits, millions of transistors, e.g., NFET transistors and/or
`costly in terms of the plot space on the device that is lost and
`
`
`
`PFET transistors, are formed on a substrate including a crys­
`
`
`
`
`would run counter to the trend in integrated circuit products of
`
`
`
`
`talline semiconductor layer. A field effect transistor, irrespec­
`
`
`
`
`reducing the size of such products. Other techniques have
`
`
`tive of whether an NFET transistor or a PFET transistor is 30
`
`
`
`
`been tried to alleviate this problem, e.g., a so-called Rx-tuck
`
`
`
`
`
`considered, typically comprises so-called PN junctions that
`
`
`process, but such processes also tend to consume excessive
`
`
`
`
`are formed by an interface ofhighly doped regions, referred to
`
`
`amounts of chip plot space and may result in considerable
`
`
`as drain and source regions, with a slightly doped or non­
`device performance degradation.
`doped region, referred to as a channel region, disposed
`
`
`The present disclosure is directed to a plurality of semi-
`
`
`
`
`
`between the highly doped source/drain regions. The channel
`
`
`
`
`35 conductor devices formed in and above a continuous active
`
`
`
`length of a transistor is generally considered to be the lateral
`
`
`region and a conductive isolating structure formed above the
`
`
`distance between the source/drain regions.
`
`
`
`
`
`active region between the devices that may avoid, or at least
`
`
`
`As device dimensions have continued to shrink over recent
`
`
`
`reduce, the effects of one or more of the problems identified
`
`years, it is becoming more challenging to accurately and
`
`
`
`above.
`repeatedly manufacture integrated circuit products that meet 40
`
`
`
`
`
`
`performance criteria established for such integrated circuit
`SUMMARY OF THE INVENTION
`
`
`
`
`products. Typically, semiconductor devices are formed on
`
`
`discrete islands of semiconducting substrate, i.e., active
`The following presents a simplified summary of the inven­
`
`
`
`
`
`
`regions that are defined in the substrate by isolation struc­
`
`
`
`tion in order to provide a basic understanding of some aspects
`
`
`
`
`prior 45 tures. For example, FIGS. an illustrative 1 and 2 depict
`
`
`
`of the invention. This summary is not an exhaustive overview
`
`
`
`
`cells ("Cell art device 10 comprised of first and second 1" and
`
`
`
`of the invention. It is not intended to identify key or critical
`"Cell 2"). The cells are intended to be representative in nature.
`
`
`
`
`elements of the invention or to delineate the scope of the
`
`
`For example, in one illustrative example, Cell 1 may be a
`
`
`
`invention. Its sole purpose is to present some concepts in a
`
`NAND circuit and Cell 2 may also be a NAND circuit. In
`
`
`
`simplified form as a prelude to the more detailed description
`
`
`
`another example, inverter Cell 1 may be an and Cell 2 may be 50
`
`
`that is discussed later.
`a flip-flop.
`Generally, the present disclosure is directed to a device that
`
`
`
`
`
`
`
`
`
`comprises a plurality of semiconductor devices formed in and
`
`
`
`With continuing reference to FIGS. 1 and 2, a plurality of
`
`
`
`above a continuous active region and a conductive isolating
`12PA, 12PB, 12NA and 12NB are
`
`
`spaced apart active regions
`
`
`
`
`
`structure formed above the active region between the devices,
`defined in a semiconducting substrate by one or more isola­
`
`
`
`
`
`
`
`and various methods of making such a device. One illustrative
`tion structures. A plurality of PFET devices 20Pl-2 are 55
`
`
`
`
`
`
`
`device disclosed herein includes a continuous active region
`of formed in and above the active region 12PA and a plurality
`
`
`
`
`
`
`
`defined in a semiconducting substrate, first and second tran­
`PFET devices 20P3-4 are formed in and above the active
`
`
`
`
`
`
`sistors formed in and above the continuous active region, each
`source/ P-doped region 12PB. The PFET devices comprise
`
`
`
`
`
`
`
`of the first and second transistors comprising a plurality of
`drain regions 32P, while the NFET devices 22Nl-4 comprise
`
`
`
`
`
`
`active region, a con­formed in the continuous example,60 doped regions N-doped source/drain regions 32N. In the depicted
`
`
`
`
`
`
`
`
`
`
`
`the various PFET and NFET devices share a common elec­ductive isolating electrode positioned above the continuous
`
`
`
`
`
`
`
`and a the first and second transistors region between active active trode structure 30 that extends across the separated
`
`
`
`
`
`
`regions and the isolation region therebetween. For example, power rail conductively coupled to the conductive isolating
`
`
` electrode. PFET transistor 20Pl and NFET transistor 22Nl share a
`
`first includes device disclosed herein illustrative Another common gate electrode structure 30 that extends across both 65
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`in a semicon­active regions defined region and second continuous of the active regions 12PA, 12NA and the isolation
`
`
`
`
`
`
`
`
`
`
`formed in and second PFET transistors substrate, first between those two active regions. The structures ducting 14 may be
`
`

`

`
`
`US 8,618,607 Bl
`
`3
`
`4
`
`
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`and above the first continuous active region, and first and and devices are schematically depicted in the drawings for
`
`
`
`
`
`
`
`
`
`
`
`purposes of explanation only and so as to not obscure the
`
`second NFET transistors formed in and above the second
`
`
`
`present disclosure with details that are well known to those
`
`
`
`
`continuous active region. This embodiment of the device
`
`
`
`
`skilled in the art. Nevertheless, the attached drawings are
`
`
`
`
`
`further includes a first conductive isolating electrode posi­
`
`
`
`
`
`included to describe and explain illustrative examples of the
`
`
`
`
`
`tioned above the first continuous active region between the
`
`
`
`
`present disclosure. The words and phrases used herein should
`
`
`
`first and second PFET transistors, a first power rail conduc­
`
`
`
`be understood and interpreted to have a meaning consistent
`
`
`
`
`tively coupled to the first conductive isolating electrode,
`
`
`with the understanding of those words and phrases by those
`
`
`
`
`wherein the first power rail is adapted to be at a logically high
`
`
`
`
`skilled in the relevant art. No special definition of a term or
`
`
`
`
`
`voltage level, a second conductive isolating electrode posi­
`
`
`
`
`
`10 phrase, i.e., a definition that is different from the ordinary and
`
`
`
`
`
`tioned above the second continuous active region between the
`
`
`
`
`customary meaning as understood by those skilled in the art,
`
`
`first and second NFET transistors and a second power rail
`
`
`
`is intended to be implied by consistent usage of the term or
`
`
`
`
`conductively coupled to the second conductive isolating elec­
`
`
`phrase herein. To the extent that a term or phrase is intended
`
`
`
`trode, wherein the second power rail is adapted to be at a
`
`
`
`to have a special meaning, i.e., a meaning other than that
`
`
`logically low voltage level.
`
`
`
`
`
`15 understood by skilled artisans, such a special definition will
`
`
`be expressly set forth in the specification in a definitional
`
`
`
`manner that directly and unequivocally provides the special
`
`definition for the term or phrase.
`
`
`
`The disclosure may be understood by reference to the
`
`
`
`The present disclosure is directed to a device that com-
`
`
`
`following description taken in conjunction with the accom­
`
`
`
`
`20 prises a plurality of semiconductor devices formed in and
`
`
`
`
`
`panying drawings, in which like reference numerals identify
`
`
`
`
`above a continuous active region and a conductive isolating
`
`like elements, and in which:
`
`
`
`
`structure formed above the active region between the devices,
`
`
`
`
`prior examples of various FIGS. 1 and 2 depict illustrative
`
`
`
`and various methods of making such a device. As will be
`
`
`
`art semiconductor devices formed in a semiconducting sub­
`
`
`
`readily apparent to those skilled in the art upon a complete
`strate;
`
`
`
`
`25 reading of the present application, the presently disclosed
`
`
`FIGS. 3A-3C are schematic depictions of illustrative
`
`
`
`
`subject matter may be used with a variety of different devices
`
`
`
`embodiments of semiconductor devices formed on continu­
`
`
`
`and technologies, e.g., NFET, PFET, CMOS, etc., and it may
`
`
`
`
`ous active regions that employ illustrative examples of the
`
`
`
`
`
`be readily employed on a variety of integrated circuit prod­
`
`
`
`
`isolating electrode structures disclosed herein;
`
`
`
`ucts, including, but not limited to, ASIC's, logic devices,
`
`
`FIGS. 4A-4C are schematic depictions of illustrative
`
`
`
`draw­to the attached 30 memory devices, etc. With reference
`
`
`
`
`examples of various possible configurations of illustrative
`
`
`
`
`ings, various illustrative embodiments of the devices and
`
`
`
`semiconductor devices disclosed herein;
`
`
`
`methods disclosed herein will now be described in more
`
`FIGS. S A-SE are plan and cross-sectional views depicting
`detail.
`
`
`
`semiconductor of illustrative various possible configu rations
`
`drawings that explain FIG. 3A-3C are various schematic
`
`
`
`
`
`devices disclosed herein;
`35
`
`
`
`
`
`
`certain aspects of the various devices disclose herein. As
`
`
`views depicting FIGS. 6A-6D are various cross-sectional
`
`
`a first shown in FIG. 3A, an illustrative device 100 comprises
`
`
`
`
`another possible configuration of illustrative semiconductor
`
`
`
`active continuous active region 112P and a second continuous
`
`
`
`devices disclosed herein; and
`
`
`region 112N formed in a semiconducting substrate. The
`
`
`views depicting FIGS. 7A-7D are various cross-sectional
`
`
`in the semiconducting active regions 112P, 112N are defined
`
`
`yet another possible configuration ofillustrative semiconduc­
`
`
`
`
`
`
`40 substrate by isolation structures 113 that may be formed using
`
`
`tor devices disclosed herein.
`
`
`
`traditional techniques. The substrate may take the form of a
`
`
`
`
`
`While the subject matter disclosed herein is susceptible to
`
`
`
`silicon-on-insulator (SOI) substrate that is comprised of a
`
`
`
`
`various modifications and alternative forms, specific embodi­
`
`
`
`bulk substrate, a buried insulation layer (a so-called BOX
`
`
`ments thereof have been shown by way of example in the
`
`
`
`
`layer) and an active layer positioned above the box layer. In
`
`
`
`drawings and are herein described in detail. It should be
`
`
`
`45 such an embodiment, the active regions 112P, 112N would be
`
`
`
`
`understood, however, that the description herein of specific
`
`
`
`formed in the active layer. The substrate may also be in bulk
`
`
`
`embodiments is not intended to limit the invention to the
`
`
`form. The substrate may also be made of materials other than
`
`
`
`
`particular forms disclosed, but on the contrary, the intention is
`
`
`
`silicon. Thus, the terms substrate or semiconducting substrate
`
`
`
`to cover all modifications, equivalents, and alternatives fall­
`
`as used herein and in the appended claims should not be
`
`
`
`
`ing within the spirit and scope of the invention as defined by
`
`
`
`
`50 considered as limited to any particular configuration or mate­
`
`the appended claims.
`rial.
`of PFET With continuing reference to FIG. 3A, a plurality
`
`
`
`
`
`devices are formed in and above the active region
`120Pl-4
`
`
`
`
`
`
`
`are formed in ofNFET devices Various illustrative embodiments of the invention are 112P and a plurality 122Nl-4
`
`
`
`
`
`
`
`
`
`described below. In the interest of clarity, not all features of an 55 and above the active region 112N. The PFET devices 120 and
`
`
`
`
`
`
`
`mate­actual implementation are described in this specification. It the NFET devices 122 may be formed using traditional
`
`
`
`
`
`
`will of course be appreciated that in the development of any rials and techniques. For example, the PFET devices 120 may
`
`
`
`
`
`
`
`
`
`P-doped such actual embodiment, numerous implementation-specific be comprised of various P-doped regions 132P, e.g.,
`
`
`
`
`
`
`
`decisions must be made to achieve the developers' specific source/drain regions, and the NFET devices 122 may be
`
`
`
`
`
`
`
`
`goals, such as compliance with system-related and business­60 comprised of various N-doped regions 132N. In the depicted
`
`
`
`
`
`a related constraints, which will vary from one implementation example, the device 100 is a CMOS device that comprises
`
`
`
`to another. Moreover, it will be appreciated
`
`
`by the plurality that such a devel­ of common gate structures 130 that are shared
`
`
`
`opment effort might be complex
`
`
`various and time-consuming, but PFET devices 120 and NFET devices 122. The com-
`
`
`
`
`
`above both of the would nevertheless be a routine undertaking for those of mon gate structures 130 are positioned
`
`
`
`
`
`
`
`ordinary skill in the art having the benefit of this disclosure. active regions 112P, 112N and they each span the isolation
`65
`
`
`
`The present subject
`
`
`
`
`
`material matter will now be described with positioned between the active regions 112P, 112N. In
`
`
`reference to the attached figures. Various structures, systems other applications, the device 100 may not have this illustra-
`
`
`
`
`
`DETAILED DESCRIPTION
`
`

`

`
`
`US 8,618,607 Bl
`
`6
`5
`
`
`
`
`
`electrodes 150PG and 150NG formed on number of isolating tive common gate structure As will be appre­configu ration.
`
`
`
`
`
`
`
`ciated by one skilled in the art after a complete reading of the the device 100, nor the number of transistors that may be
`
`
`
`
`
`
`
`present application, the gate structures 130 may be formed associated with each of the isolating electrodes 150PG and
`
`
`
`
`
`
`
`
`using a variety of different materials and by performing a 150NG. Moreover, the number of transistors associated with
`
`
`
`
`
`
`variety of known techniques. For example, the gate insulation each of the isolating electrodes 150PG and 150NG need not
`5
`
`
`
`
`
`
`layer in such a gate structure 130 may be comprised of a be the same for either of the active regions 112P or 112N, and
`
`
`
`
`
`
`
`
`
`
`
`
`variety of different insulating materials, e.g., silicon dioxide, it need not be uniform within either of the active regions 112P,
`
`
`
`
`
`
`
`
`
`
`a so-called high-k insulating material (k value greater than 112N. For example, the devices 100 disclosed herein may be
`
`
`
`
`
`
`
`10). The gate electrode in such a gate structure 130 may be employed in situations wherein there are hundreds if not
`
`
`
`
`
`
`
`comprised of polysilicon or it may contain at least one metal 10 thousands of transistors formed in each of the active regions
`
`
`
`
`
`
`
`layer. The gate structures 130 of the transistor 100 may be 112P, 112N and hundreds of isolating electrodes 150PG and
`
`
`
`
`
`
`made using so-called "gate first" or "gate last" techniques. 150NG. FIG. 3C is a simplistic line-based drawing indicating
`
`
`
`
`
`
`
`
`
`Thus, the presently disclosed inventions should not be con­one example of a device 100 comprised of fourteen PFET
`
`
`
`
`
`
`
`
`sidered as limited to any particular materials of construction devices 120, five isolating electrodes 150PG that are coupled
`
`
`
`
`for the gate structures 13 0 nor the manner in which such a gate 15 to the power rail 140H, fourteen NFET devices 122 and five
`
`structure 130 is formed.
`
`
`
`isolating electrodes 150NG that are coupled to the power rail
`
`
`
`
`
`
`
`
`
`Still with continuing reference to FIG. 3A, the device 100 140L. Thus, the presently disclosed inventions should not be
`
`
`
`
`
`
`
`
`further comprises an isolating electrode 150PG that is con­considered as limited to any particular number or arrange­
`
`
`
`
`
`
`
`
`ductively coupled to a schematically depicted power rail ment of transistor devices or any particular number or
`
`
`
`
`
`
`
`
`140H at a logically high voltage, e.g., V dd· The device also 20 arrangement of the isolating electrodes 150PG, 150NG.
`
`
`
`
`
`
`
`
`includes an isolating electrode 150NG that is conductively FIG. 4A-4C depict various illustrative examples that sche­
`
`
`
`
`
`
`
`coupled to a power rail 140L that is at a logically low voltage, matically depict how the device 100 may be configured in
`
`
`
`
`
`
`
`
`
`
`e.g., ground. Of course, the absolute magnitude of the volt­various situations. FIG. 4A depicts the illustrative example
`
`
`
`
`
`
`ages on the power rails 140H, 140L may vary depending upon wherein the isolating electrodes 150PG, 150NG are posi­
`
`
`
`
`
`
`
`
`
`the particular application, but the voltage on the power rail 25 tioned between source regions ("S") of the respective transis­
`
`
`
`
`
`
`
`
`140H will be relatively higher than the voltage on the power tors. The drain regions ("D") of the various transistors are also
`
`
`
`
`
`rail 140L. In the illustrative example shown in FIG. 3A, the depicted in FIG. 4A. More specifically, in FIG. 4A, the iso­
`
`
`
`
`
`
`
`
`isolating electrodes 150PG, 150NG are separated by a dis­lating electrode 150PG is positioned between the source
`
`
`
`
`
`
`tance 142. In the depicted embodiment, the isolating elec­regions of the PFET devices 120P2 and 120P3, while the
`
`
`
`
`
`
`
`
`trode 150PG spans across the entirety of the active region isolating electrode 150NG is positioned between the source
`30
`
`
`
`
`
`
`112P, while the isolating electrode 150NG spans across the regions of the NFET devices 122N2 and 122N3. In this illus-
`
`
`
`
`
`
`
`
`entirety of the active region 112N. In one illustrative embodi­trative example, the source regions of the PFET devices
`
`
`
`
`
`ment, the isolating electrodes 150PG and 150NG have the 120P2-3 are coupled to the power rail 140H by schematically
`
`
`
`
`
`
`
`
`same structure and configuration as the gate structures 130, depicted conductive structures 144, while the source regions
`
`
`
`
`
`and they may be initially formed at the same time the gate 35 of the NFET devices 122N2-3 are coupled to the power rail
`
`
`
`
`
`
`
`
`
`structures 130 are formed. In other cases, the isolating elec­140L by schematically depicted conductive structures 146.
`
`
`
`
`
`
`
`trodes 150PG and 150NG may be comprised of different FIG. 48 depicts the illustrative example wherein the iso-
`
`
`
`
`
`
`
`
`materials, may be a different physical size and/or may be lating electrodes 150PG, 150NG are positioned between a
`
`
`
`
`
`
`
`
`formed at different times as compared to the gate structures source region (''S") on one adjacent transistor and a drain
`
`
`
`
`
`
`
`130. In one illustrative embodiment, the isolating electrodes region ("D") on the other adjacent transistor. More specifi­
`40
`
`
`
`
`
`150PG and 150NG and the gate structures 130 are all initially cally, in FIG. 48, the isolating electrode 150PG is positioned
`
`
`
`
`
`
`
`
`
`formed as elongated continuous line-type structures. There­between the source region of the PFET device 120P2 and the
`
`
`
`
`
`after, the isolating electrodes 150PG and 150NG are defined drain region of the PFET device 120P3, while the isolating
`
`
`
`
`
`
`
`
`
`
`
`by performing another etching process. The isolating elec­electrode 150NG is positioned between the source region of
`
`
`
`
`
`
`trodes 150PG and 150NG may be conductively coupled to the 45 the NFET device 122N2 and the drain region of the NFET
`
`
`
`
`
`
`
`
`power rails 140H, 140L, respectively, by any of a variety of device 122N3. In this illustrative example, the source region
`
`
`
`
`
`
`
`different conductive structures that are formed in a layer of of the PFET device 120P2 is conductively coupled to the
`
`
`
`
`
`
`
`
`insulating material positioned above the substrate. The iso­power rail 140H by schematically depicted conductive struc­
`
`
`
`
`
`
`lating electrodes 150PG and 150NG each have a long axis tures 144, while the source region of the NFET device 122N2
`
`
`
`
`
`and, in one embodiment, the long axis of the isolating elec-50 is coupled to the power rail 140L by schematically depicted
`
`
`
`
`
`
`trade 150PG is substantially aligned with the long axis of the conductive structures 146. The drain region of the PFET
`
`
`isolating electrode 150NG.
`
`
`
`device 120P3 and the drain region of the NFET device 122N3
`
`
`
`
`FIG. 38 depicts one illustrative embodiment
`
`
`are conductively of an illustra­ coupled to one another via a conductive
`
`
`tive unit cell lOOA of the device
`strap 148 and illustrative 100. In this example, the unit contacts.
`
`FIG. 4C depicts 120P2 and 120P3 that 55 the illustrative example wherein the iso-
`cell lOOA comprises PFET transistors
`
`
`
`
`
`
`
`are positioned on opposite
`
`
`lating sides of the isolating electrode electrodes 150PG, 150NG are positioned between
`
`
`
`
`150PG and NFET transistors
`
`
`drain regions 122N2 and 122N3 that are ("D") of the respective transistors. More spe­
`
`
`
`positioned on opposite
`
`
`cifically, sides of the isolating electrode in FIG. 4C, the isolating electrode 150PG is posi­
`
`
`
`
`150NG. Stated another way, the isolating
`
`
`
`tioned electrode 150PG is between the drain regions of the PFET devices 120P2
`
`
`
`
`
`
`positioned above a space between the adjacent doped regions 60 and 120P3, while the isolating electrode 150NG is positioned
`
`
`
`
`
`of the transistors
`
`
`
`between 120P2 and 120P3, while the isolating elec­ the drain regions of the NFET devices 122N2 and
`
`trode 150NG is positioned above a space between
`
`
`122N3. In this illustrative the adja­ example, only the isolating elec­
`
`
`
`cent doped regions of the transistors
`
`trodes 122N2 and 122N3. Of 150PG, 150NG are coupled to the power rails 140H,
`
`
`
`course, as will be appreciated by one skilled
`
`
`140L, respectively. in the art after a In this example, the drain region of the
`
`
`
`
`
`
`
`complete reading of the present application, the inventions 65 PFET device 120P3 and the drain region of the NFET device
`
`
`
`
`
`
`
`
`
`
`disclosed herein are not limited in terms of how many tran­122N3 are conductively coupled to one another via a conduc­
`
`
`
`
`
`
`sistors may be formed in the active regions 112P, 112N, the tive strap 148 and illustrative contacts, while the drain region
`
`

`

`
`
`US 8,618,607 Bl
`
`8
`
`7
`material that may be selectively etched with respect to the
`
`
`
`of the NFET of the PFET device 120P2 and the drain region
`
`
`the insulating layers 180, 182. In one illustrative example,
`
`
`
`
`via a device 122N2 are conductively coupled to one another
`
`
`
`
`
`of silicon diox­insulating layers 180, 182 may be comprised
`
`
`contacts. The various conductive strap 149 and illustrative
`
`
`
`of silicon ide and the insulating layer 181 may be comprised
`
`conductive structures
`
`144, 146, 148, 149 and the depicted
`
`
`
`
`nitride. The thickness of the various layers ofinsulating mate­
`
`
`
`
`they or material, contacts may be of any desired configu ration
`
`
`
`rial may vary depending upon the particular application and
`
`
`
`may be formed in one or more layers of insulating materials
`
`
`they may be formed by performing a variety of known tech­
`
`
`positioned above the substrate, and they may be formed using
`
`
`
`niques, e.g., chemical vapor deposition (CVD), atomic layer
`
`
`a variety of different techniques.
`
`
`
`deposition (ALD), or plasma enhanced versions of those pro-
`
`
`illustrative With reference to FIGS. SA-SE, further
`
`
`
`
`10 cesses. The various conductive structures, such as the power
`
`
`
`
`embodiments of various inventions disclosed herein will be
`
`
`
`rails 140H, 140L and the previously described contacts 190P,
`
`
`
`view of one further described. FIG. SA is a schematic plan
`
`
`of 192P, 190N and 192N, may be comprised of a variety
`
`
`illustrative embod