throbber
United States Patent
`Mundtet al.
`
`{15
`
`[11] Patent Number:
`
`[45] Date of Patent:
`
`4,578,128
`Mar, 25, 1986
`
`[54] PROCESS FOR FORMING RETROGRADE
`DOPANTDISTRIBUTIONS UTILIZING
`SIMULTANEOUS OUTDIFFUSION OF
`DOPANTS
`
`[75]
`
`Inventors: Randall S. Mundt; Ray E. Wyatt,
`both of Colorado Springs, Colo.
`[73] Assignee: NCR Corporation, Dayton, Ohio
`[21] Appl. No.: 677,636
`
`Dec. 3, 1984
`[22] Filed:
`[51]
`Int. Ch4 oo. eeee HOIL 21/20; HOIL 21/225
`[52] U.S. Che cessssssesssssseccesssseeeesseeseee 148/191; 29/571;
`29/576 B; 29/576 W; 148/187; 148/175;
`156/643; 357/42; 357/50
`[58] Field of Search .......0 29/571, 576 B, 576 W;
`148/187, 191, 175; 156/643; 357/42, 50
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`1/1967 Takagi et al... 148/191
`3,298,880
`»» 148/191
`1/1972 Thire ..........6
`3,635,773
`
`3,767,487 10/1973 Steinmaier........
`3,921,283 11/1975 Shappir ............
`
`
`148/191 X
`6/1977 Vora......
`4,032,372
`4,411,058 10/1983 Chen ...cccececesseeereeeenenerereeies 29/571
`
`8/1984 MOomMoOe .....ccecsecrerenerereees 29/571 X
`4,463,493
`
`4,466,171
`4,516,316
`4,535,529
`
`8/1984 Jochem......cceeeceeees 29/571 X
`
`5/1985 Haskell oo...
`sssseeseereeee 29/576 B
`8/1985 Jochems..........eee: 29/571
`
`OTHER PUBLICATIONS
`
`Chen, “Quadruple-Weill CMOS for VLSI Technol-
`ogy”, IEEE Transactions on Electron Devices, vol.
`ED-31, No. 7, Jul. 1984, pp. 910-919.
`Manoliu et al., “High-Density and Reduced Latchup
`Susceptibility CMOS Technology for VLIS”, IEEE
`Electron Device Letters, vol. EDL-4, No.7, Jul. 1983,
`pp. 233-235.
`
`Primary Examiner—William G. Saba
`Attorney, Agent, or Firm—Wilbert Hawk, Jr.; Casimer
`K.Salys
`
`ABSTRACT
`[57]
`A retrograde dopantdistribution is provided in a semi-
`conductor substrate by the combined use of indiffusion
`and surface outdiffusion and without the use of high
`energy implants or buried epitaxial layers. The retro-
`grade dopantdistribution is provided both in the n-well
`and the p-well regions to a depth sufficient to accommo-
`date deep trench isolation structures.
`
`8 Claims, 8 Drawing Figures
`
`
`
`IP Bridge Exhibit 2014
`IP Bridge Exhibit 2014
`TSMC v. Godo Kaisha IP Bridge 1
`TSMCv. Godo Kaisha IP Bridge 1
`IPR2017-01841
`IPR2017-01841
`
`

`

`U.S. Patent Mar. 25, 1986
`
`Sheetlof3
`
`4,578,128
`
`FIG.1
`
`PRIOR ART
`
`
`
`FIG.2
`
`PRIOR ART
`
`
`
`

`

`U.S. Patent Mar.25,1986
`
` Sheet2of3
`
`4,578,128
`
`FIG. 4
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`37
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`36
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`54
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`53
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`FIG.5 ©
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`605
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`64
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`60
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`53
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`54
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`FIG.6
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`,
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`bbb MUN |
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`5X 108 om2
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`

`

`U.S. Patent Mar. 25, 1986
`
`Sheet3 of3
`
`4,578,128
`
` FIG.8
`
`

`

`1
`
`4,578,128
`
`PROCESS FOR FORMING RETROGRADE
`DOPANT DISTRIBUTIONS UTILIZING
`SIMULTANEOUS OUTDIFFUSION OF DOPANTS
`
`BACKGROUNDOF THE INVENTION
`
`The present invention relates to a simplified process
`for forming retrograde dopant distributions in inte-
`grated circuit structures, that is, dopant distributions
`which increase in a vertically inward or downward
`direction from the surface of a layer or body such as a
`semiconductor substrate. As used here in reference to
`the present invention, the word “retrograde” also con-
`notes a controlled dopant profile.
`The potential advantages of a retrograde dopant dis-
`tribution in semiconductorsubstrates are several, partic-
`ularly in CMOSintegrated circuit structures. The ad-
`vantages are well-known and include the potential for
`increased device packing density and decreased suscep-
`tibility to latchup.It is believed there are available basi-
`cally three approaches for forming a retrograde dopant
`profile. The techniques, namely, high energy implants
`(greater than about 200 keV), buried epitaxial layers,
`and outdiffusion, can be used separately or in combina-
`tion.
`An example of retrograde processing techniques is
`disclosed in Manoliuet al, “High-Density and Reduced
`Latchup Susceptibility of CMOS Technology for
`VLSI”, IEEE Electron Device Letters, Vol. EDL-4, No.
`7, July, 1983, pp. 233-235. Manoliu etal. uses the com-
`bination of a first implant in a doped substrate and a
`later implant in an undoped epitaxial layer. The well
`formation process is concluded with an anneal cycle.
`The specific CMOSstructure and epitaxial buried layer
`retrograde p-well structure reportedly increases circuit
`density by reducing the minimum n,—p+ spacing
`while decreasing latchup susceptibility.
`Chen, “Quadruple-Well CMOS for VLSI Technol-
`ogy”, IEEE Transactions on Electron Devices, Vol. ED-
`31, No. 7, July 1984, pp. 910-919, describes a process
`for forming a retrograde, quadruple-well CMOSstruc-
`ture. The n-well and p-well retrograde doping profiles
`each require multiple doping steps. Essentially,
`the
`structure is a two-well structure in which deep n-type
`and p-type wells are separated by respective shallow
`n-type and p-type wells or channel stops. The shallow
`wells are implanted through a peripheral field oxide
`during the deep well implantation. Overall, the Chen
`processinvolves, first, forming deep-well windowsin a
`planar field oxide. The p-well region is masked and a
`high energy phosphorus implant at 290 keV is done in
`the presence of the mask to define the deep n-well and
`the adjacent shallow n-type channel stop under the
`oxide. The n-well is then counter-doped with boron for
`threshold voltage adjustment.
`After the two-implant-step formation of the retro-
`grade n-well, the n-well is masked and a multiple dop-
`ing sequence is applied to provide the p-well retrograde
`profile. Initially, a 120 keV boron implant is used to
`form a relatively deep p-well, and the adjacent shallow
`p-type channel stop under the oxide. Phosphorus coun-
`terdoping adjusts the n-channel
`threshold voltage.
`Then, a deep, high energy 340 keV boron implant pro-
`vides the deep retrograde p-well profile which is used
`to eliminate latchup. The counter-doping aspects of the
`process i.e., the combination of high energy implants
`and opposite conductivity low energy counter-doping,
`
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`are also disclosed in Chen, U.S. Pat. No. 4,411,058,
`issued Oct. 25, 1983.
`The outdiffusion of semiconductor dopants from the
`surfaces of silicon, mentioned above,
`is another well-
`known phenomenon,onethat in the past has produced
`undesirable results. For example, outdiffusion from the
`front and rear major surfaces of semiconductor wafers
`leads to both macro-outdoping and micro-autodoping.
`Various process techniques are used to eliminate or
`decrease the effects of outdiffusion, including two-step
`processing using process interruption and/or high and
`low temperatures, and sealing of wafer surfaces with a
`mask suchassilicon,silicon dioxide or silicon nitride.
`Recently, outdiffusion has been used advantageously
`to provide a retrograde dopant distribution, but the
`process techniques for implementing the outdiffusion-
`caused retrograde dopant distribution typically are
`complex. For example, Steinmaier, U.S. Pat. No.
`3,767,487 relates to the use of outdiffusion techniques to
`form selected, isolated retrograde surface-adjacent re-
`gions which are used as isolation wells for MOS or
`bi-polar devices. Referring to FIG. 1, the MOSinte-
`grated circuit process disclosed in the Steinmaier °487
`patent involves forming a five-micron thick n-type epi-
`taxial layer 11 on a p-type semiconductor 10; forming a
`thermal oxide masking layer 12 over the epitaxial layer
`having an aperture 13 which defines the p-well orisola-
`tion region; depositing a shallow p-well 14 in the sur-
`face of the epitaxial layer at the masked apertures using
`an oxidizing atmosphere to re-cover (not shown) the
`exposed substrate surface regions; etching the oxide
`mask to reexpose the epitaxial layer over part of the
`deposited impurity region beneath the masked win-
`dows; and outdiffusing the boron via the mask apertures
`13 in a vacuum ampul containing silicon to provide the
`retrograde concentration in region 14. In particular, the
`vertical retrograde dopant concentration in region 14,
`that is, the relatively low surface concentration there,
`provides a high breakdown voltage for the NMOS
`device whichis subsequently formed in the p-well 14. In
`addition, in the surface region 16 surrounding the well
`14, the mask prevents outdiffusion, thereby providing a
`surface region 16 of relatively high doping concentra-
`tion surrounding the retrograde well 14. This horizontal
`dopant concentration gradient is used to prevent short
`circuits between the epitaxial layer 11 and the subse-
`quently formed NMOSdevice.
`Asis evident from the above description, in regard to
`small geometry, high density structures, the Steinmaier
`°487 retrograde p-well fabrication process suffers from
`several disadvantages in addition to complexity. The
`shallow retrograde p-well 14 does not appear to be
`capable of providing the desirable retrograde dopant
`gradient along the deep isolation trenches which are
`used in some CMOSstructures. The adjacent n-well 17
`is capped duringthe outdiffusion step and does not have
`a retrograde dopant concentration gradient. Further-
`more, the lateral dopant concentration gradient at the
`periphery of the p-well 14 quite obviously limits the
`minimum dimension of, and spacing between,the wells.
`In short, the complex processing of the Steinmaier ’487
`patent is tailored to provide a p-well-only retrograde
`gradient and a lateral doping gradient that are inconsis-
`tent with small geometry, high density integrated cir-
`cuits.
`Shappir, U.S. Pat. No. 3,921,283 uses surface outdif-
`fusion in the fabrication of dielectrically isolated MOS-
`FETsemiconductordevices. Referring to FIG. 2, in the
`
`

`

`3
`illustrated process an n-type bulk substrate 20 is masked
`using an oxide 2i-nitride 22 composite. Initially,
`the
`composite mask is used to etch trenches which are then
`filled with thermal oxide to provide a trenchisolation
`structure for the NMOSactive area 24 and the PMOS
`active area 25. Next, the mask 21-22 is removed from
`the NMOSdevice active area. The NMOSp-well 26 is
`then formed using both the trench oxide 23 and the
`mask 20-21 over the PMOSdevice 25 as implant/dop-
`ing masks. The maskis retained over the n-well for the
`PMOSdevice active area and the semiconductorinte-
`grated circuit structure is heated in the presence of
`silicon powder to simultaneously indiffuse and outdif-
`fuse boron p-well 26 to provide a retrograde dopant
`distribution in the p-well. There is no disclosure of
`forming a retrograde profile in n-well 28 or of doping
`this in combination with the retrograde p-well. In par-
`ticular, there is no teaching of an a single mask, inte-
`grated, epitaxial process particularly suited for decreas-
`ing latchup susceptibility.
`Vora, U.S. Pat. No. 4,032,372, issued June 28, 1977,
`forms bipolar and field effect transistors in individual,
`outdiffused, retrograde n-type wells or pockets which
`are formed in a semiconductor substrate. Initially, the
`surface region of the starting bulk substrate is doped
`with both arsenic and phosphorus to respective n+
`concentrations of about 102° and 102! atoms/cc. A three
`micron thick p-type epitaxial layer is then formed over
`the substrate, and an oxide layer which serves as an
`. outdiffusion cap (and subsequently as thefield isolation
`oxide) is formed on the outer surface of the epitaxial
`- layer. Then, the arsenic and phosphorusare outdiffused
`until the much faster diffusing phosphorus reaches the
`outer surface of the oxide capped epi
`layer, thereby
`forming an n-type phosphorus pocket which encloses
`‘an arsenic buried region within the p-type epi/bulk
`~ substrate.
`The resulting retrograde vertical concentration gra-
`dient provides a relatively heavily doped bottom region
`for bipolar collector and subcollector structures, and a
`-relatively lightly doped upper region for optimizedfield
`effect
`transistors. However,
`the vertical
`retrograde
`isolation wells or pockets of the Vora ’372 patent re-
`quire a relatively complex fabrication sequence involv-
`ing the above-described two implantsteps and the oxide
`capping layer,
`in addition to the epitaxial
`layer. The
`phosphorus and the arsenic outdiffusion heating step
`also establishes a lateral dopant concentration gradient
`that would undesirably increase the effective lateral
`dimensions and design spacing of the isolation pockets.
`The design spacing is increased still further for arsenic
`concentrations greater than about 10?! atoms/cc due to
`lateral spreading of the arsenic along the interface of the
`epitaxial layer and substrate, and requires. the use of
`arsenic concentrations less than 102! atoms/cc, or pro-
`cess compensation. Foremost, the process yields a retro-
`grade distribution in only one of the two impurity re-
`gions. Because of these aspects, the Vora ’372 retro-
`grade process is believed to be limited to the specific
`disclosure of combined bipolar/field effect device fabri-
`cation, and to integrated circuit structures which re-
`quire the specific combination of bipolar and FET
`structures at the expense of device close packing.
`In view of the above discussion,it is a primary object
`of the present invention to implement a retrograde dop-
`ant distribution using simple process techniques.
`It is another object to provide the above-described
`retrograde dopant distribution using process techniques
`
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`4
`which are readily incorporated into existing semicon-
`ductor fabrication processes.
`It is still another object to provide a process for form-
`ing a retrograde dopantdistribution, the steps of which
`are readily incorporated into standard CMOS fabrica-
`tion sequences to provide advantages such as those
`listed in the Manoliu et al. article referenced above,
`including decreased susceptibility to latchup, and to do
`so for both p and n channel MOSdevices without high
`energy implants, buried layers or complex processing.
`In addition, in regard to integrated circuit structures
`using trench dielectric isolation, it is an object to de-
`crease susceptibility to inversion along the trench walls
`and to do so without high energy implants, buried lay-
`ers or complex processing.
`SUMMARYOF THE INVENTION
`
`In one aspect, the process of the present invention
`which has the above advantages involves: providing a
`semiconductor substrate of n-type conductivity; form-
`ing a p-type epitaxial surface layer; selectively forming
`a low energy, surface-adjacent n-type implant layer in a
`mask defined n-well region; and uncovering the struc-
`ture and heating the structure to simultaneously effect a
`selected extent of indiffusion and outdiffusion to form a
`retrograde vertical dopant concentration gradientin the
`n-well and to define an adjacent p-well which also has a
`retrograde vertical dopant concentration gradient.
`In an exemplary working embodiment, the present
`invention involves: providing a substrate doped with
`n-type dopant such as antimony to about 6 10!8&cm~—3,
`forming an epitaxial silicon layer approximately five
`microns thick doped with p-impurities such as boron to
`a concentration of 2x 10!6 cm—3; selectively masking
`the epitaxial layer to expose n-well regions, depositing a
`surface adjacent n-type region using an implant energy
`of about 150 keV and a dose of 5X 10/3 cm—?; removing
`the photoresist; and heating the structure in argon ambi-
`ent at atmospheric pressure for 10 hours at 1150° C. to
`form an n-well having a surface concentration of about
`51014 atoms per cm?, a concentration of about
`81015 atoms per cm? at one micron depth, and an
`adjacent p-well having a surface concentration of about
`81014 atoms per cm} and a concentration of about
`9x 1015 atoms per cm} at one micron, and junction
`depths of about 3.5 microns.
`These characteristics are provided without the use of
`an oxide outdiffusion mask. Also, these characteristics
`are provided along with a constant horizontal dopant
`concentration, a deep retrograde vertical gradient in
`both impurity type wells and with a junction depth
`whichis suitable for accommodating deep trench isola-
`tion structures. All of these characteristics are accom-
`plished consistent with the object of not using high
`energy implants or buried layers.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The above and other aspects of the present invention
`are discussed in detail with regard to the following
`drawings in which:
`FIGS. 1 and 2 are schematic cross-sectional represen-
`tations of stages of prior art techniques for forming
`retrograde substrate dopant concentrations;
`FIGS. 3-7 are schematic cross-sectional representa-
`tions of a portion of a CMOSintegrated circuit during
`fabrication thereof and in particular showing the se-
`quence of forming the retrograde dopant distribution
`used therein; and
`
`

`

`4,578,128
`
`5
`FIG. 8 is a schematic cross-sectional representation
`of a portion of a CMOSintegrated circuit which incor-
`poratesthe retrograde dopantdistribution of the present
`invention.
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`
`FIG. 8 illustrates one example of a CMOSintegrated
`circuit structure 50 which can be made using the dual-
`well approach ofthe present invention. Theillustrated
`structure includes a PMOS FET 51P formed in an n-
`well 52N and an NMOS FET51N formedin a p-well
`52P. The complementary integrated structure 50 is
`formed in n-type epitaxial layer 53 formed on aninte-
`grated circuit semiconductorsubstrate 54 using VLSI
`process techniques. The transistors 51P and 51N in-
`clude source and drain diffusions 55P and 55N in an
`LDD(lightly doped drain-source) configuration, all of
`which are self-aligned with the silicon gates 57P and
`57N, as well as gate sidewall oxide spacers 58P and
`58N,interlevel dielectric layer 59 and aluminum inter-
`connects 61. The PMOS FET51P and the NMOS FET
`52Nareelectrically isolated from adjacent devices and
`adjacent active regions, such as one another,
`in the
`n-type epitaxial region 53 by trench dielectric isolation
`structures 60.
`In accordance with the present invention, an indiffu-
`sion-outdiffusion process is used to form the n-well 52N
`and p-well 52P and to form a retrograde.vertical dopant
`profile for such wells, in which profile the doping level
`at a depth within the substrate, indicated by line 63
`(FIG. 7), exceeds the doping level at the substrate sur-
`face 64. The retrograde profile provides the desired
`device isolation and the desired trench sidewall doping
`characteristics without the use of high energy implants
`or buried epitaxial layers. The process used to form the
`retrograde profile, described below,
`is
`relatively
`straightforward in that no oxide outdiffusion mask or
`cap is necessary, there is no horizontal dopant gradient,
`and the process is readily implemented as shown with
`trench dielectric isolation structures. Quite obviously,
`the illustrated structure 50 is only one of the possible
`applications among the various NMOS, PMOS, CMOS,
`bipolar and other applications which benefit from a
`retrograde doping profile with or without substrate-
`adjacent opposite-conductivity regions and wells and
`with or without trench dielectric isolation structures.
`As will be equally obvious to those of usual skill in the
`art from the discussion below,the invention is applica-
`ble to, and readily integrated into, processes for forming
`such other structures.
`The optimized retrograde dopant gradientfabrication
`sequence for CMOSwell applicationsstarts as shownin
`FIG. 3 and is precisely accomplished through a se-
`quenceofepitaxial silicon growth, ion implantation and
`a thermaldiffusion, which includessurface outdiffusion.
`The starting structure typically is the n+ bulk silicon
`substrate of <100> or other orientation which has a
`resistivity of about 0.007 to 0.02 ohm centimeters. In a
`particular working embodimentused to form the retro-
`grade dopant distribution dimensions and values shown
`in FIG.7, the starting structure is an n+ substrate 54
`doped with antimony or other n-type impurity species
`to a concentration of about 10!8 to 1019 atoms per cubic
`centimeter (atoms/cc). Referring to FIG. 3,
`initially
`there is formed on the substrate 54 an epitaxial mono-
`crystalline silicon layer 53, typically about five microns
`thick, which is doped with boron or other p-type impu-
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`rities to a concentration ofabout 10!6 to 10!7 atoms/cc.
`The epi layer 53 can be formed, for example, by a stan-
`dard non-selective process such as(eliminate) chemical
`vapor deposition using, e.g., silane or silicon tetrachlo-
`ride. Although selectivity is unnecessary for epitaxial
`deposition on the semiconductor substrate 54, as an
`alternative epitaxial growth process, one ofthe recently
`developed selective processes can be used which pro-
`vides excellent planarity and crystallinity in addition to
`selectivity. One example ofa suitable selective epitaxial
`growth technique uses SiH2Clo-H2 systems, typically
`with about one volume percent HCI and exemplary
`temperature and pressure of 1,000° C. and 50 Torr,
`respectively.
`The epitaxial layer 53 is doped either duringorafter
`deposition, preferably during deposition by adding the
`appropriate dopant containing gas compound to the
`reactant gas system.
`Referring further to FIG. 3, next the dielectric isola-
`tion trenches are formed. First
`the substrate 53 is
`masked using any of a number of materials including
`silicon nitride, silicon dioxide and combinationsthereof,
`or the exemplary photoresist mask 31. In addition, a
`mask composition suitable for X-ray or ion beam expo-
`sure can be used. Using photo-resist, a layer thereofis
`formed onthe substrate, then is exposed and developed
`to produce the etch mask 31 having openings 32—32
`which correspond to the desired trench locations.
`Next, the trenches are etched to a typical depth of
`about one to six microns, preferably using an aniso-
`tropic etch process such as anisotropic plasma etching
`or reactive ion etching (RIE). This produces a substrate
`surface topology which includes the generally horizon-
`tal substrate outer surface 64 and the generally vertical
`sidewalls 34—34 and the horizontal bottom walls 35 of
`the trench. One preferred etch process is reactive ion
`etching using a fluorine etchant gas such as nitrogen
`trifluoride (NF3). In such an anisotropic reactive ion
`etching process, the mechanical componentor ion bom-
`bardment component dominates the chemical reaction
`component and provides the vertical sidewalls which
`are desirable in order to provide minimum lateral width
`in the subsequently formeddielectric isolation structure
`60 (FIG. 5).
`Referring now to FIG.4, after the trench etching
`process,
`the trench mask 31 is removed, such as by
`plasma ashing, and insulator layer 36 is formed on the
`substrate surface topography and in the trench. In a
`working embodiment, the dielectric layer 36 is silicon
`dioxide glass which is formed to a thickness greater
`than the trench depth by low temperature, low pressure
`chemical vapor deposition using the reactant gasessi-
`lane and oxygen at a temperature of about 500° to 900°
`C. and a pressure of about 0.1 to 1 Torr. After the oxide
`formation, the upper surface 37 is chemically etched or
`mechanically polished back to the planar substrate
`outer surface 64. In the event the oxide deposition has
`produceda substantially non-planar outer oxide surface
`37, planarization techniques can be applied. One suit-
`able technique involves the spin-on application of a
`relatively low viscosity organic layer (not shown) on
`surface 37. The spun material is caused to flow to a
`relatively smooth surface by the centrifugal force of the
`application or by a subsequent low temperature bake.
`Reactive ion etching, which etches the organic material
`and the oxide at approximately the same rate, is then
`used to clear the organic layer from the upper surface
`and thereby replicate the surface smoothness of the
`
`

`

`7
`organic coating in the outer surface 64 of the epitaxial
`silicon layer 53 and the trench dielectric oxide structure
`60. Of course, if the planarization enhancement is not
`necessary, the oxide 1s simply etched back to the epitax-
`ial silicon. In either case, the resultant doped epi layer
`53/isolation trench 60 structure is complete, as shown in
`FIG. 5, and ready for the retrograde dual-well forma-
`tion.
`
`the unpatterned
`Next, and referring to FIG. 6,
`trench-isolated epi layer 53 of FIG. 5 is patterned by
`forming a mask 41 which is the complement of the
`subsequently formed n-well 52N (FIG. 7). The mask 41
`can be formed using conventional ultraviolet photo-
`lithographic techniques. As mentioned, a typical pro-
`cess involves the formation of a photoresist layer, selec-
`tive exposureto ultraviolet radiation in the presence of
`a mask, followed by developing of the photoresist and
`dissolving of selected regions. Of course, other masking
`techniques such as electron beam or X-ray techniques
`can be used.
`Referring further to FIG. 6, next the n-well layer 52N
`(FIG. 7) is formed byinitially depositing a layer 42 of
`donor impurities in the exposed epitaxial layer 53 in the
`presence of mask 41. Preferably, this deposition/forma-
`tion step is done using ion implantation, although fur-
`nace diffusion can be used if mask 41 is of the appropri-
`ate composition. One suitable sequence for the above-
`described doping levels and dimensions uses ion implan-
`tation for forming the n— phosphorus surface-adjacent
`well layer 52N (FIG. 7), and involves implantation of
`phosphorus ions at 150 keV and a dose of 5x 1013
`atoms/cc as indicated schematically at 43. Other n-type
`species such as arsenic or antimony can be used. How-
`ever, the relatively low mobility of these two impurities
`would slow diffusion within the wafer and the required
`indiffusion and outdiffusion would therefore require
`longer heating times and/or higher heating tempera-
`tures.
`
`:
`
`Next, and referring to FIG. 7, the photoresist mask 41
`is removed, for example, by plasma ashing. With the
`.- surface 64 of the substrate epitaxial layer 53 exposed,
`- the integrated circuit structure is then heated, typically
`using a furnace diffusion cycle to simultaneously outdif-
`fuse and indiffuse the n-type and p-type dopants to
`provide the desired retrograde dopant profile. For ex-
`ample, for the above-disclosed parameters, heating in an
`ambient of argon at atmospheric pressure (or in a vac-
`uum under appropriate other parameters) at a tempera-
`ture of 1150° C. for 10 hours provides the retrograde
`n-well 52N having a surface concentration of about
`5X1014 atoms/cc, a concentration of about 8x 1015
`atoms/cc at a depth of one micron (line 63) and a junc-
`tion depth of about 3.5 microns(line 65); and an adja-
`cent retrograde p-well having a surface concentration
`of about 81014 atoms/cc, and a concentration of
`9x 1015 atoms/cc at a depth of one micron.
`In one form, the present invention involves: provid-
`ing a substrate 54 doped n+ using an n-type dopant such
`as antimony to 6X 10!8 atoms/cm}; forming a p~ epitax-
`ial silicon layer 53 approximately 5.5 microns thick
`doped with p-impurities such as boron to a concentra-
`tion of 2 10!6 atoms/cm3; forming trench isolation
`structures 60 in the substrate about two microns deep
`defining the p-well and n-well regions; masking the
`epitaxial layer to expose n-well regions 52N; depositing
`a surface-adjacent n-region 42 (FIG. 6) using a low
`implant energy of about 150 keV and a dose of 5x 10}3
`cm —?; removing the mask; and heating the structure in
`
`_ 0
`
`— 5
`
`20
`
`25
`
`30
`
`40
`
`45
`
`50
`
`65
`
`4,578,128
`
`8
`argon ambient for 10 hours at 1150° C. to form an n-well
`52N having a surface concentration of about 4.7 1014
`atoms/cc, a concentration of about 8 x 10!5 atoms/cc at
`one micron depth, and an adjacent p-well 52P having a
`surface concentration of about 8.4 10!4atoms/cc and a
`concentration of about 9.3 10!5 atoms/cc at one mi-
`cron, and well junction depths of about 3.5 microns.
`Thoseofskill in the art will understand that the above
`parameters and doping distributions are exemplary and
`will be readily altered to satisfy particular process
`needs. Furthermore, depending upon the subsequent
`high temperature processing requirements,
`the initial
`dopant concentration profile and outdiffusion heat
`treatment can be altered to accommodate subsequent
`high temperature processing.
`the structure
`According to the FIG. 8 example,
`shownin FIG.7 is then provided the gate electrodes 57,
`the LDD source-drain diffusions 55, sidewall oxides 58,
`interlevel dielectric layers 59 and metallization 61,
`along with other conductors as required and a final
`passivation coating. The reader wili note that FIG. 7
`(and FIGS. 3-6)is positioned to clearly show the n-well
`implant and full trenches 60 adjacent the n-well 52N,
`whereas FIG. 8 is translated slightly to show the com-
`plete NMOS FET. Theresult is a slightly different
`perspective of the samestructure. Of course, alternative
`structures and process techniques will be used. The
`purpose hereisillustration, to provide one example of
`the use of the dual retrograde p- and n-wells. As one
`alternative, the retrograde wells can be formed without
`trench isolation where trenches are not needed. As
`anotheralternative, bipolar devices, or combinations of
`bipolar and MOSFET devices, can be formed in the
`wells.
`Asstill another alternative, the described process for
`forming retrograde wells is suited for combination with
`the vertical sidewall
`trench isolation technique de-
`scribed in co-pending U.S. application Ser. No. 667,181,
`filed on Nov. 1, 1984, in the names of Rogers, Mundt
`and Kaya, which application is assigned in common
`with the present application. The Rogerset al. applica-
`tion is incorporated by reference. The Rogers et al.
`processis tailored to provide high quality, vertical side-
`wall trench isolation structures. The vertical sidewall
`profile, of course, is highly desirable vis-a-vis the nor-
`mal slanting sidewall profile in order to minimize the
`lateral dimensions of the channel stop and the overall
`trench isolation structure. Using the Rogers et al. pro-
`cess, the trench dielectric 60 is a composite structure
`comprising, for example, in order from the substrate
`trench wall, a stress relief thermal oxide layer 300 to
`1,000 Angstroms thick; a chemical vapor-deposited
`polycrystalline silicon (poly) etch stop layer 1,000 to
`3,000 Angstroms thick; a chemical vapor-deposited
`silicon nitride, oxidation-and dopant-blocking layer
`1,000 to 3,000 Angstromsthick; and a chemical vapor-
`deposited silicon oxide isolation layer containing ap-
`proximately 3 to 9 weight percent dopant such as phos-
`phorus or boron. As deposited, the CVD silicon oxide
`dielectric fills the trench and covers the substrate. This
`oxideisolation layer is melted and reflowed at a temper-
`ature of about 950° to 1150° C. in steam or nitrogen
`ambient for a period of approximately 30 minutes to
`four hours, depending upon the thickness of the dielec-
`tric isolation layer and the dimensions of the trench.
`The oxide dielectric isolation layer is then etched back
`by an anisotropic etching process such as reactive ion
`etching using CHF3 etchant gas. During this oxide etch-
`
`

`

`4,578,128
`
`_— 0
`
`15
`
`20
`
`10
`9
`providing a substrate of n-conductivity type;
`back, the nitride layer is removed outside the trench
`forming on the substrate a p-type epitaxial layer;
`regions and the polysilicon etch-stop layer protects the
`forming trench dielectric isolation structures in the
`underlyingsilicon substrate. Subsequently, the dopantis
`epitaxial layer defining and dielectrically isolating
`outgassed from the oxide trench isolation dielectric, for
`at least first and second device regionsin the layer;
`example, by heating the structure at 1000° to 1200° C.in
`forming a mask on the epitaxial layer exposingafirst
`a nitrogen ambientfor twoto eight hours. The polysili-
`device region adjacent a covered second device
`con layer is then removed from the active regions, out-
`region;
`side the trench structure. During the two thermal pro-
`lightly n-type doping the surface region of the epitax-
`cessing steps—the reflow step and the outgassing
`ial layer in the first device region;
`step—the nitride blocks oxidation and doping of the
`removing the mask; and
`underlying structure,
`including the silicon substrate
`heating the structure for a predetermined time and
`structures for fabricating.
`temperature so that a combination of outdiffusion
`Having thus described the preferred and alternative
`and indiffusion forms a retrograde dopant distribu-
`embodiments of the present outdiffusion process for
`tion of n-type conductivity in the first device re-
`forming a retrograde dopant distribution, what
`is
`gion and a retrograde dopantdistribution of p-type
`claimedis:
`conductivity in the adjacent second device region.
`1. A process for forming a vertical retrograde dopant
`6. A process for forming a vertical retrograde dopant
`distribution in a semiconductor device, comprising:
`concentration in a semiconductor substrate comprising:
`providing a substrate of a first conductivity type;
`providing a substrate of n-conductivity type and con-
`forming on the substrate an epitaxial
`layer of the
`centration about 6

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