21.3
`
`A Shallow Trench Isolation with SiN Guard-Ring
`for Sub-Quarter Micron CMOS Technologies
`
`Takashi Ogura, Toyoji Yamamoto, Yukishige Saito,
`Yoshihiro Hayashi and Tohru Mogami
`
`Silicon Systems Research Laboratories, NEC Corporation
`1120 Shimokuzawa, Sagamihara, Kanagawa 229—11,]apan
`
`Abstract
`to
`important
`Shallow trench isolation (STI) technology is
`realize high~speed and high—packing—density CMOS—LSIs. A
`new SiN guardrring on the upper edge of filled Sl02 for steep~
`sidewall STI is proposed and evaluated to improve the reverse
`narrow channel effect and device reliability. Good isolation
`characteristics and sufficient
`improvement of the reverse
`narrow channel effect are achieved for STI with SiN guard—
`ring structure.
`
`Introduction
`For sub—quarter micron CMOS, a new isolation technology is
`necessary for
`realizing high—perforrnance CMOS devices,
`because of LOCOS isolation limitation STI technology has
`been studied extensively for solving this problem[1]. In STI
`technology, the surface planarization for trench—filled SiOz is
`the key issue to realize good isolation characteristics. However,
`SiOz upper edge is greatly etched after CMP process, because
`of pretreatment for gate oxidation. Furthermore,
`for scaled
`CMOS, steeprsidewall trench should be used for advanced STI
`structure, shown in Fig.1. However, “hump” in sub—threshold
`characteristics can be generated for steepesidewall STI because
`of electric field concentration at the trench edge, as reported in
`ref. [2]. Therefore, in the steep—sidewall STI for scaled CMOS,
`the filled SiO; surface in trench should be a little higher than
`the active area surface[3].
`In this paper, we present a new STI technology using SiN
`guard—ring and the electrical properties of STI with this new
`guard—ring are discussed.
`
`SiN Guard-Ring Fabrication Process
`Fig.2 illustrates the process flow for STI with SiN guard—ring.
`The etching of trench with the steep—sidewall, SiOz filling and
`CMP planarization were canied out after SiN pad fabrication.
`Next, after removing pad SiOQ and SiN by wet etching, refilled
`SiN film was deposited. Filled SiO; surface in this stage is
`50nm higher than the active area surface; this can eliminate
`electric field concentration at the trench edge. Finally, after
`SiN etching on the active area, SiN guard~ring was formed at
`the active area edge.
`Fig.3 shows cross-sectional TEM image
`at the active edge after gate oxidation and deposition of poly—Si
`film. In Fig.3(a), oxide etching at STI upper edge is suppressed
`by SiN guard-ring, although SiOz sink was caused by wet
`etching for conventional structure ( Fig.3(b)).
`
`Results and Discussion
`A. Device characteristics
`Isolation characteristics are shown in Fig.4. Punch—through
`voltage for SiN guard—ring STI is comparable with that for
`conventional STI. The IG‘VG characteristics are shown for 2cm
`perimeter NMOS and PMOS capacitors utilized SiN guard
`
`ring structure with 5.9nm gate oxide in Fig.5. No leakage
`current increase observed for N/P—MOS capacitors, although
`gate oxide thinning may be generated at the active edge by SiN
`guard‘n'ng. The narrow channel characteristics of various
`structures are shown in Fig.6. VT lowering for MOSFETs with
`the SiN guard—ring STI
`is
`smaller
`than those with the
`conventional STI and is comparable with that for tapered
`(=75° ) sidewall STI MOSFETS; this is due to a little elevation
`of SiN film near the active area surface and completely filled
`insulators in STI. The sub—threshold characteristics of N/P—
`
`MOSFETs with the SiN guard—ring STI and conventional STI
`structure are shown in Fig.7. No hump characteristics are
`observed for
`the SiN guard-ring STI,
`although hurrip
`characteristics are observed for the conventional STI. This
`
`indicates that SiN guard—ring STI
`transistor action suppression.
`
`is useful
`
`for
`
`side—wall
`
`8. Device reliability
`SiN guard—ring fabrication process is worried about MOSFET
`performance and reliability degradation by SiN film etcheback
`process.
`Interface state density (Dir)
`for NMOSFET was
`evaluated by the measurement of chargeepumping current
`Shown in Table l. Dit value for N/P—MOSFET with the SiN
`guard—ring
`STI
`are
`comparable with
`those with
`the
`conventional STI. This result indicates MOSFETs do not have
`
`any damage by SiN etch-back process. Furthermore, hot—
`carrier degradation is the next issue for SiN guardering STI
`because of high mechanical stressing by SiN film. Hot-carrier
`effects were evaluated for various NMOSFETs, shown in Fig.9.
`Lifetime plot for various devices have the same line;
`this
`means SiN guard—ring has no mechanical damage.
`
`Conclusion
`
`A new SiN guard—ring structure for steep—sidewall STI is
`proposed and evaluated. Good isolation characteristics and
`sufficient improvement of the reverse narrow channel effect
`are achieved for the SiN guard~ring STI. Furthermore, it was
`confirmed that no device degradation,
`including hot—carrier
`effects, is achieved for MOSFET with the SiN guard—ring STI.
`Therefore. this new STI technology is promising for the future
`scaled CMOS—LSIS.
`
`Acknowledgment
`The authors would like to thank T. Kunio and H. Abe for
`
`as well
`through this work,
`their encouragement
`Kawaguchi and H. Abiko for their helpful suggestion.
`
`as H.
`
`References
`
`[1] H. Kawaguchi et 31., Symp. on VLSI Tech. Dig, p125 (1997)
`[2] K. Ishimaru et al., Symp, on VLSI Tech. Dig., p97 (1994)
`[3] AH. Perera et a1., IEDM Tech. Dig, p679 (1995)
`
`21 0
`
`0-7803-4700-6/98/$10.00 © 1998 |EEE
`
`1998 Symposium on VLSI Technology Digest of Technical Papers
`
`TSMC 1015
`TSMC 1015
`
`

`

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`(a) SiO2 filling and
`CMP planarization
`
`(b) Pad oxide and SiN
`removal
`
`(c) SiN deposition
`
`TI
`
`(d) SiN etch—back,
`gate oxidation and
`poly—Si deposition
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`Isolation Space (um)
`Fig.1 The relationship between
`15
`isolation space and trench depth for E
`typical trench sidewall angle. More
`g 10
`than 80° sidewall angle is required
`LE
`5 _
`when isolation space is reduced
`>
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`down to 0.1 ,u m with 0.3 u m trench
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`depth.
`9
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`
`10°
`'
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`Space (u m)
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`Fig.4 Punch-through characteristics.
`
`10‘
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`PMOSFET
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`sub.
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`O Steep (Conv.)
`X Tapered (Com)
`
`101
`
`104°
`1042
`10-14
`10
`
`-10
`
`NMOSFET
`
`o
`Ve (V)
`Fig.5 The IGNG Characteristics of
`0_2 MOS capacitor.
`l
`104
`PMOSFET
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`Gate Voltage (V)
`we
`Fig.7 The sub-threshold Characteristics of
`Channel Width 01 m)
`wide channel MOSFETs (WG/LG=10,u iii/0.4
`Fig.6 Threshold voltage (VT) of MOSFETS
`A m) at VD= $0.1V. Solid and dotted lines
`with whom channel width at VD=i 1.5V.
`indicate SiN guard~ring structure and
`conventional one res ectivel ,
`VT is normalized at lO,u m Channel width.
`9 ’
`‘p
`3'
`Table 1 Comparison of interface state
`1 O
`w=o.33um.1odm
`density (Dh) between MOSFETs with
`SiN guard—ring:y STI and those with
`SiN guard-ring a
`o
`conventional ST].
`Cm“
`A
`°
`
`(b) CODVentlonal
`Fig.3 Cross sectional TEM
`image_
`100
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`(A) D- of the active lane
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`NMOSFET
`4.6E+11
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`72
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`
`
`(a) n*/p diodes
`(h) an diodes
`— SiN guard-ring
`
`NMOSFET
`3.4F.+06
`Fig.8 Histograms of leakage current for diodes.
`Reverse bias is 5V. Area and perimeter of diodes
`
`are 001ng and 100cm, respectively
`
`A107
`8
`53
`a, 105
`
`
`
`Com.
`3.9E+11
`71 M
`
`8.3F,+06
`
`
`
`
`
`l
`Unit 2 cm ' eV
`
`1
`
`a: 103
`‘J
`
`101
`
`.
`107
`
`.
`.
`‘IO5
`106
`ISUB / W (Alum)
`
`.
`104
`
`Fig.9 Lifetime plot of narrow
`and wide channel NMOSFETs.
`
`1998 Symposium on VLSI Technology Digest of Technical Papers
`
`21 1
`
`