5,960,270
`[11] Patent Number:
`[19]
`Unlted States Patent
`
`Misra et al.
`[45] Date of Patent:
`Sep. 28, 1999
`
`U5005960270A
`
`[54] METHOD FOR FORMING AN MOS
`TRANSISTOR HAVING A METALLIC GATE
`ELECTRODE THAT IS FORMED AFTER
`
`SOURCE AND DRAIN REGIONS
`_
`Inventors: Veena Mlsra; Suresh Venkatesan;
`Christopher C. Hobbs; Brad Smith;
`Jefi'rey S. Cope; Earnest B. Wilson,
`all Of AuStm’ TeX'
`.MtlI.Sh b
`.
`0 0m 3’ nc ’
`C aum urg’
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`[75]
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`73As
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`Slgnee
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`[
`
`111.
`
`.
`[21] Appl‘ No“ 08/907’990
`[22]
`Filed;
`Aug 11, 1997
`
`6
`
`Int. Cl.
`[51]
`[52] U.S. Cl.
`
`................................................. .. H01L 21/336
`........................ .. 438/197; 438/585; 438/586;
`438/595; 438/596
`[58] Field of Search ................................... .. 438/197, 585,
`438/586, 595, 596
`
`[56]
`
`REfEI‘enCES CitEd
`US HUENTDOCUMENTS
`
`............................ .. 437/40
`2/1995 Witek et al.
`5,393,681
`
`.. 437/41
`7/1995 Chau et a1.
`5,434,093
`........................... .. 437/40
`9/1995 Grlvna et al.
`5,447,874
`2/1998 MOSlehl
`.................................. .. 437/40
`5,716,861
`Primary Examiner—John F. Niebling
`Assistant Examiner—Lynne A. Gurley
`Attorney) Agent) 0,, Firm_Keith E. Witek
`
`ABSTRACT
`[57]
`Amethod for forming a metal gate MOS transistor begins by
`’
`’
`forming source and drain electrodes (26 28 and/or 118)
`Within a substrate (12 or 102). These source and drain
`regions (26, 28, and 118) are self-aligned to a
`lithographically-patterned feature (24 or 108). After forma-
`tion of the source and drain regions, the features (24 and 108
`are processed to fill these features with a metallic gate layer
`(23a or 123a). This metal
`layer (23a or 123a) is then
`chemically mechanically polished (CMPed) to form a metal-
`lic plug region (28b or 128b) Within the features (24 or 108).
`The plug region (28b or 128b) is formed in either an inlaid
`or dual inlaid manner wherein this metallic plug region (28b
`or 128b) is self-aligned to the previously formed source and
`drain regions and preferably functions as a metal MOS gate
`mgmn
`
`5,391,510
`
`2/1995 Hsu et a1.
`
`............................... .. 437/44
`
`43 Claims, 8 Drawing Sheets
`
`10
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`
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`
`69/21
`3t.
`k,
`
`
`
`
`
`
`
`TSMC 1005
`TSMC 1005
`
`

`

`US. Patent
`
`Sep.28, 1999
`
`Sheet 1 0f8
`
`5,960,270
`
`10
`
`\‘
`
`18
`
`
`
`
`FIG.2
`
`FIG. 3
`
`

`

`US. Patent
`
`Sep.28, 1999
`
`Sheet 2 0f 8
`
`5,960,270
`
`8
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`US. Patent
`
`Sep.28, 1999
`
`Sheet 3 0f8
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`5,960,270
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`

`

`US. Patent
`
`Sep.28, 1999
`
`Sheet 4 0f 8
`
`5,960,270
`
`100
`
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`
`105
`
`
`
`

`

`US. Patent
`
`Sep.28, 1999
`
`Sheet 5 0f8
`
`5,960,270
`
`100
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`
`112
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`
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`114
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`118
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`1_03
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`

`

`US. Patent
`
`Sep.28, 1999
`
`Sheet 6 0f8
`
`5,960,270
`
`100
`
`11112
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`
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`100
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`
`‘1-
`
`

`

`US. Patent
`
`Sep.28, 1999
`
`Sheet 7 0f 8
`
`5,960,270
`
`
`
`1_22
`
`129
`112
`112
`100
`
`
`III/IIIIII/IAVVVIIIIIIII/I/A
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`
`

`

`US. Patent
`
`Sep.28, 1999
`
`Sheet 8 0f 8
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`5,960,270
`
`100\‘ 131b
`
`112 131C 129 112
`
`131b
`
`
`
`f
`
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`
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`118
`Jig
`
`

`

`5,960,270
`
`1
`METHOD FOR FORMING AN MOS
`TRANSISTOR HAVING A METALLIC GATE
`ELECTRODE THAT IS FORMED AFTER
`THE FORMATION OF SELF-ALIGNED
`SOURCE AND DRAIN REGIONS
`
`FIELD OF THE INVENTION
`
`The present invention relates generally to semiconductor
`manufacturing, and more particularly to, forming a metal
`gate MOS transistor wherein self-aligned high temperature
`source and drain regions are formed before the formation of
`the metal gate.
`
`BACKGROUND OF THE INVENTION
`
`industry, metal-oxide-
`(IC)
`In the integrated circuit
`semiconductor (MOS)
`transistors have typically been
`formed utilizing polysilicon gate electrodes. Polysilicon
`material
`is typically preferred for use as an MOS gate
`electrode due to its thermal resistive properties (i.e., poly-
`silicon can better withstand subsequent high temperature
`processing). Polysilicon’s robustness during high tempera-
`ture processing allows polysilicon to be high-temperature
`annealed along with source and drain regions. Furthermore,
`polysilicon’s ability to block the ion implantation of dopant
`atoms into a channel region is advantageous. Due to the ion
`implantation blocking potential of polysilicon, polysilicon
`allows for the easy formation of self-aligned source and
`drain structures after gate patterning is completed.
`However, polysilicon gate electrodes suffer from several
`disadvantages. First, polysilicon requires the ion implanta-
`tion of different dopant atoms for p-channel transistors and
`n-channel transistors formed in a surface CMOS process.
`These different dopant atom species of the polysilicon gate
`electrodes are required in order to get the p-channel and
`n-channel transistors of a CMOS process to have compatible
`threshold voltages (V). Furthermore, most MOS transistors
`formed using a polysilicon gate technology require a thresh-
`old (Vt) adjust implant into the MOS channel region. This
`threshold adjust implant is of a high enough doping con-
`centration to adversely impact
`the mobility of carriers
`through the channel region. Polysilicon gate electrodes are
`semiconductor materials that suffer from higher resistivities
`than most metal materials. Therefore, polysilicon materials
`operate at a much slower speed than metallic materials. To
`compensate for this higher resistance, polysilicon materials
`require extensive and expensive silicide processing in order
`to increase their speed of operation to acceptable levels.
`Furthermore, polysilicon materials suffer from a polysilicon
`depletion phenomenon whereby the effective gate oxide
`thickness (EOT) of polysilicon transistors is increased by
`polysilicon depletion. Also, polysilicon gate electrodes are
`sometimes disadvantageous due to lack of threshold voltage
`control when utilized in fully depleted silicon-on-insulator
`(SOI) structures.
`Therefore, a need exists in the industry for a metal gate
`process which can replace polysilicon gate devices.
`However, metal gates cannot withstand the higher tempera-
`tures and oxidation ambients which can be withstood by
`conventional polysilicon gate electrodes. In addition, metal
`films cannot effectively block ion implantation of dopant
`atoms into a channel region whereby self-aligned source and
`drain electrodes cannot be readily formed using conven-
`tional implant processing when a metal gate is used. In
`addition, some metal films will not adequately adhere to
`surrounding layers when these metal materials are patterned
`to small geometries. Some metal films are difficult to litho-
`
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`2
`graphically pattern and etch via conventional processing due
`to the fact that the etching of these metal films may signifi-
`cantly damage underlying oxides thereby affecting device
`performance. Furthermore, through subsequent thermal pro-
`cessing of the integrated circuit (IC), instability and degra-
`dation of the gate oxide may occur due to chemical inter-
`action between the metal and oxide at the metal-gate-to-
`gate-oxide interface.
`Therefore, a need exists for a process which can be
`utilized to form a self-aligned MOS transistor having metal
`gate electrodes.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`in cross-sectional diagrams, a
`1—7 illustrate,
`FIGS.
`method for forming a self-aligned metal gate MOS transistor
`in accordance with the present invention.
`FIGS. 8 and 9 illustrate, in cross-sectional diagrams, a
`method for forming a self-aligned metal gate transistor and
`integrated metallic interconnect structures using a dual
`inlaid process in accordance with the present invention.
`FIGS. 10—18 illustrate, in cross-sectional diagrams, an
`alternate embodiment for forming a metal gate MOS tran-
`sistor in accordance with the present invention.
`FIGS. 19—22 illustrate, in cross-sectional diagrams, an
`alternate embodiment for forming a metal gate MOS tran-
`sistor and integrated metallic interconnect structures in the
`same layer in accordance with the present invention.
`It will be appreciated that for simplicity and clarity of
`illustration, elements illustrated in the drawings have not
`necessarily been drawn to scale. For example, the dimen-
`sions of some of the elements are exaggerated relative to
`other elements for clarity. Further, where considered
`appropriate, reference numerals have been repeated among
`the drawings to indicate corresponding or analogous ele-
`ments.
`
`DESCRIPTION OF A PREFERRED
`EMBODIMENT
`
`Generally, the present invention is a process for forming
`a metal-gated metal-oxide semiconductor (MOS) transistor
`which contains self-aligned source and drain electrodes that
`are formed before forming the metal gate. In a first embodi-
`ment (see FIGS. 1—7), an opening feature is used to define
`locations of a source and drain regions wherein the source
`and drain regions are formed by thermally driving dopant
`atoms out from silicide regions (the silicide regions being
`segmented into source and drain segments in a self-aligned
`manner by the opening). These source and drain electrodes
`are therefore formed self-aligned to the opening by thermal
`diffusion whereby the opening can be subsequently filled
`with the metal gate electrode which is then self-aligned to
`the thermally diffused source and drain regions. Since the
`source and drain regions are thermally driven and thermally
`activated before formation of the metal gate, adverse thermal
`processing of the metal gate can be avoided.
`In an alternate embodiment, a polysilicon or amorphous
`silicon dummy/temporary gate electrode is formed (see
`FIGS. 10—18). This temporary gate electrode is used as a
`mask for implanting self-aligned source and drain electrodes
`into the substrate. After the formation of these source and
`
`drain electrodes, a dielectric region is deposited and chemi-
`cally mechanically polished (CMP) to expose a top portion
`of the temporary polysilicon gate electrode. The polysilicon
`dummy gate electrode structure is then removed to form a
`void where the polysilicon gate once was located. This void
`
`

`

`5,960,270
`
`3
`is then filled with a metal material gate region wherein the
`metal gate is aligned to the source and drain region by virtue
`of being formed in a location previously occupied by the
`self-aligned polysilicon dummy gate.
`In addition, the metal gate processes taught herein can
`form self-aligned MOS transistors which are interconnected
`at the gate level using a novel dual inlaid process (see FIGS.
`8—9). The novel dual inlaid structure has a bottom/lower
`dual inlaid region which forms the metallic gate electrodes
`of the MOS transistors (i.e., it does not form inter-metallic
`interconnects/contacts as are common in the prior art, but
`forms a gate electrode isolated from electrical contact by a
`gate dielectric). The dual inlaid structure also has an upper
`interconnect dual
`inlaid trench region connected to the
`underlying dual inlaid gate region for connecting the under-
`lying metallic gate electrode to another active electric device
`or gate electrode on the integrated circuit (IC).
`Additionally, the metal gate processing taught herein can
`also be used to form self-aligned MOS transistors and an
`interconnect layer within the same dielectric material using
`a novel
`two-pattern process (see FIGS. 19—22).
`In this
`embodiment, the gate and interconnect layers are formed
`simultaneously, although patterned separately, because both
`are metal-filled inlaid structures.
`
`Since many metal materials are mid-gap work function
`materials, the same metal gate material can function as a
`gate electrode for both n-channel and p-channel transistors
`in a CMOS process without requiring adverse threshold
`voltage adjust
`implants and while maintaining threshold
`voltages (V) at compatible levels. These mid-gap metal
`gates also do not need both P and N dopants in different
`regions to support a CMOS gate function. The presence of
`metal gates allows the mobility of a channel region to be
`improved since the channel region will no longer need high
`dose threshold adjust implants and higher doping profiles in
`an MOS channel region. Metal gates are known to have
`greater conductivity than polysilicon electrodes and require
`no complicated silicide processing in order to perform at
`higher speeds of operation. Unlike polysilicon electrodes,
`metal electrodes do not suffer from polysilicon depletion
`which effects the effective gate oxide thickness (EOT) of an
`MOS transistor, thereby effecting the performance of the
`MOS device (i.e., thinner EOTs, while maybe resulting in
`greater leakage current, creates a faster-operating device). In
`addition, metal gate MOS devices are more advantageous
`for use as fully depleted silicon on insulator (SOI) devices
`since the threshold voltage of these devices can be more
`accurately controlled. In addition, metal gate electrodes are
`more compatible with high-k dielectrics than conventional
`polysilicon processing (high-k dielectrics being any dielec-
`tric with a dielectric constant greater than 5.0 and preferably
`greater than 20.0).
`Furthermore, the process taught herein avoids many of the
`conventional disadvantages associated with metal gate tech-
`nology. Since the metal gate is formed after the formation of
`high temperature source and drain regions, the limitation
`that metal gates cannot withstand high temperatures is not
`problematic when using the process taught herein.
`Furthermore, the prior art metal gate processes mostly result
`in non-self—aligned devices. However,
`the process taught
`herein results in fully self-aligned source and drain elec-
`trodes that are self-aligned to the subsequently formed metal
`gate. Even though metals, such as tungsten
`and molyb-
`denum (Mo), cannot effectively block the implanting of
`dopant atoms,
`the process taught herein still enables ion
`implanted formation of self-aligned source and drain
`regions. Since the metal gates taught herein are defined by
`
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`a chemical mechanical polishing (CMP) process, no difficult
`metal etch processing is utilized. Due to this lack of metal
`etch processing, damage of oxide regions is reduced
`whereby performance of the MOS transistor is increased.
`When using the process taught herein, elimination or reduc-
`tion of metal film delamination from adjacent oxide layers is
`achieved due to the formation of the metal gate into a
`semi-surrounding inlaid trench structure. Furthermore, the
`process taught herein eliminates the need to expose the
`metal-gate-to-gate-oxide interface to high temperatures
`whereby degradation of the gate oxide due to metal inter-
`action is reduced or eliminated.
`
`The present invention can be further understood with
`reference to FIGS. 1—22. FIGS. 1—7 illustrate a first metal
`gate embodiment, FIGS. 8 and 9 illustrate a second metal
`gate embodiment utilizing novel dual inlaid interconnect
`technology, and FIGS. 10—18 illustrate yet a third embodi-
`ment for forming a novel metal gate MOS transistor. FIGS.
`19—22 illustrate a fourth embodiment for forming both the
`self-aligned, inlaid metal gates and an inlaid interconnect at
`the same time.
`
`FIGS. 1—7 illustrate a metal gate MOS process used for
`forming a semiconductor device 10. Processing begins by
`providing a semiconductor substrate 12. Substrate 12 is
`preferably a silicon wafer, but may be one or more of a
`germanium substrate, a gallium arsenide substrate, a
`germanium-silicon substrate, a silicon on insulator substrate
`(SOI), epitaxial regions, indium phosphide substrates, other
`III-V compounds, silicon carbide substrates, or the like. Pad
`oxidation and nitride masking is utilized along with silicon
`etch processing to form trenches 14 in the substrate 12 of
`FIG. 1. These isolation trenches 14 are filled with a dielectric
`
`material in order to provide field isolation between active
`areas of the semiconductor device 10. In lieu of trench
`
`processing, local oxidation of silicon (LOCOS), polysilicon
`buffered LOCOS, or other field isolation schemes may be
`utilized in the embodiments taught herein.
`After formation of the trench regions 14, CMOS well
`processing is performed. FIG. 1 illustrates that one or more
`of a p-well and/or an n-well is formed in the substrate
`wherein, for simplicity of illustration, FIG. 1 illustrates only
`a single well region 16.
`After formation of the well regions, a selective growth
`process is used to selectively form a silicide region 18
`overlying the well region 16. It is important to note that this
`silicide region is formed over both p-wells and n-wells in the
`substrate 12 and is not formed over the trench regions 14. In
`a preferred form, layer 18 is one of either cobalt silicide
`(CoSiz) or nickel silicide (NiSi2) since these two silicide
`materials are superior materials when used for out-diffusing
`dopant atoms to form silicon PN junctions. However, tita-
`nium silicide or other known silicides may be used for form
`the region 18 in FIG. 1. Preferably, the thickness of silicide
`layer 18 is roughly 300—400 angstroms. Since the layer 18
`will subsequently be utilized to form both n-type source and
`drain regions and p-type source and drain regions via
`thermal diffusion, a double masking step and double ion
`implant process into different regions of the layer 18 is
`utilized to form both p-doped regions and an n-doped
`regions of layer 18. If only n-channel or p-channel transis-
`tors are formed on one IC, then insitu doping of the silicide
`layer 18 may be performed with one of either n-type
`impurities or p-type impurities. To form n-channel
`transistors, donor atoms such as phosphorus, arsenic, and/or
`antimony are ion implanted into the silicide layer 18. To
`form n-channel transistors, acceptor atoms such as boron,
`BF2, and/or indium are ion implanted into the silicide layer
`18.
`
`

`

`5,960,270
`
`5
`
`In order to from lightly doped drain (LDD) region in a
`self-aligned manner, various regions of the silicide layer 18
`may be implanted with two species, such as phosphorous
`and arsenic. This two-species doping will enable out-
`diffusion of both highly doped drain regions and lightly
`doped drain regions within the same thermal process due to
`differences in coefficients of diffusion for different dopant
`atoms. In summary, p-channel active areas in n-type wells
`contain a layer 18 that is ion implanted with p-type impu-
`rities (e.g., boron), an n-channel active areas within p-wells
`contain a layer 18 that is implanted with n-type impurities.
`Preferably, at this time in the process flow, a substantial
`portion of the ion implant dopant dose should be contained
`within the silicide region 18 (e.g.,
`the energy and does
`should be set so that not much dopants, if any, penetrates
`through the silicide to the underlying substrate). Depending
`upon the thickness of the silicide layer 18, ion implant beam
`energies between roughly 5 KeV and 30 KeV may be used
`to achieve this purpose.
`FIG. 2 illustrates that a thin plasma-enhanced nitride
`(PEN or like material) layer 20 is deposited overlying the
`trench isolation regions 14 and the silicide layer 18.
`Preferably, the plasma enhanced nitride layer is deposited to
`a thickness of roughly 500 angstroms. Plasma enhanced
`nitride layer 20 is provided for use as an etch stop layer when
`subsequently forming contact openings to source and drain
`electrodes of the MOS transistors. This etch stop therefore
`prevents over-etching of contact openings which could
`damage silicon/silicide contact regions. An oxide layer 22 is
`then deposited overlying a top portion of the plasma-
`enhanced nitride layer 20. It is important to note that the
`oxide 22 is preferably a low temperature oxide (LTO) due to
`the presence of the silicide layer 18. Furthermore, a low
`temperature oxide (LTO) layer 22 is preferred since a low
`temperature oxide will not result in substantial out diffusion
`of the dopant atoms contained within the doped silicide layer
`18. Typically, the oxide layer 22 is deposited to a final
`thickness of roughly 1,000—4,000 angstroms with roughly
`2,000 angstroms being preferred. In another form, the layer
`22 may be formed as a tetraethylorthosilicate (TEOS) layer
`or an ozone TEOS layer either alone or in combination with
`another material to form a composite dielectric 22.
`In FIG. 3, a photoresist mask (not specifically illustrated
`in FIG. 3) is deposited and developed over a top of the oxide
`layer 22. The photoresist mask is processed to form an
`opening 24. This opening 24 is extended into the oxide layer
`22 to form an opening 24 through the oxide layer 22 via an
`oxide etch process. Typically, this etch is performed using a
`CF4, Chlorine, and/or CHF3 plasma reactive ion etch (RIE)
`environments. In all cases, the oxide etch utilized to form the
`opening 24 will preferably use the plasma enhanced nitride
`(PEN) layer 20 as an etch stop. After deepening of the
`opening through the oxide 22, the exposed portion of the
`plasma enhanced nitride 20 within the opening 24 is
`removed by using a silicon nitride etch. Typically, an NF3
`plasma etch environment is used to reactive ion etch (RIE)
`exposed portions of the plasma enhanced nitride layer 20
`within the opening 24. After etching of the exposed portion
`of the plasma enhanced nitride (PEN) layer 20, an exposed
`portion of the silicide layer 18 within the opening 24 is
`etched away. Typically a brief wet etch ambient is used to
`remove exposed portions of the silicide region 18 in the
`opening 24. In a preferred form, piranha may be utilized to
`remove the exposed portions of the layer 18.
`In other
`embodiments, other wet etch technology and/or a dry etch
`process may be utilized to perform the etching of exposed
`portions of layer 18.
`
`6
`After completion of the etching illustrated in FIG. 3, the
`photoresist mask layer(not specifically illustrated in FIG. 3)
`is removed and an opening 24 remains in the structure 10.
`The opening 24 exposes a portion of the well region 16 as
`shown in FIG. 3. It is important to note that the opening 24
`has now segmented the layer 18 into two different
`physically-separated portions. A left portion of layer 18 in
`FIG. 3 will be utilized to form one source/drain electrode
`whereas a right portion of layer 18 in FIG. 3 will be utilized
`to form the other source/drain electrode for a same MOS
`transistor. These two source and drain electrodes are elec-
`
`trically disconnected by the opening in a preferred form, but
`may be connected if a MOS capacitor structures (e.g., a two
`terminal, and not a three terminal, device) is all that is
`desired.
`
`FIG. 4 illustrates that a thermal drive process is utilized to
`drive the dopant atoms out of the two silicide regions 18 in
`FIG. 4 to form respective source and drain electrodes 26 and
`28 within single crystalline silicon areas. This drive process
`is typically performed at a temperature between 800° C. and
`1000° C. for roughly 30 to 90 seconds. Notice that the source
`and drain electrodes 26 and 28 are formed fully self-aligned
`to the opening 24 of FIG. 4 since the opening defines the
`placement of the silicide region 18. The regions 26 and 28
`are typically driven downward to 1,500—2,000 angstroms in
`depth and will
`laterally diffuse roughly 1,000 to 1,500
`angstroms in distance. A doping concentration of the regions
`26 and 28 tends to be on the order of n><1019 to m><1020
`dopant atoms per centimeters cubed where n and m are any
`real numbers. As is clearly illustrated in FIG. 4, the silicide
`regions 18 remain as a portion of the source and drain
`electrodes whereby a conductivity of these silicon source/
`drain electrodes is improved.
`FIG. 5 illustrates that a sacrificial oxide 25 is thermally
`grown over a substrate surface which is exposed by the
`opening 24. The sacrificial thermal oxide 25 is typically
`grown to a thickness of roughly 100 angstroms. After
`formation of the sacrificial oxide 25, silicon nitride is
`deposited and reactive ion etched to form silicon nitride
`spacers 23 on top of the sacrificial oxide 25. The etch used
`to form silicon nitride spacers 23 is selective to the sacrificial
`oxide 25. After formation of the spacers 23, a threshold (Vt)
`adjust implant is performed at a low ion implant energy in
`order to form threshold adjust doped region 31 within the
`well region 16. Punchthrough avoidance ion implants may
`also be performed at
`this time. After formation of the
`threshold adjust region 31, an oxide etch is utilized to
`remove portions of the sacrificial oxide 25 which lie within
`an inner periphery of the spacer 23. Notice that the spacers
`23 provides a necessary offset not only to compensate for
`lateral diffusion of the source and drain regions 26 and 28,
`but to electrically isolate subsequent gate electrode forma-
`tions from the silicide regions 18 whereby Miller effects may
`be reduced. While nitride spacers formed by deposition may
`be replaced or composited with a sidewall thermal growth,
`some silicides do not oxidize effectively and may at least
`some deposition process to obtain adequate source/drain to
`gate isolation.
`After formation of the spacers 23 and the etching of the
`sacrificial oxide layer 25, thermal gate oxidation to form a
`thermal gate oxide 27 is performed. In addition, the oxide 27
`may be formed as a composite dielectric consisting of a
`thermally grown layer and a deposited oxide layer which
`may be optionally nitrided and/or fiuorinated. Also,
`the
`composite-deposited oxide portion may be replaced with a
`deposited nitride layer and/or a high-k dielectric material
`such as a metal oxide. After formation of the gate oxide 27,
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`5,960,270
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`7
`a metal deposition process is utilized to form a metal layer
`28a in FIG. 6. Preferably, layer 28a is made of one or more
`of molybdenum (Mo),
`tungsten (W),
`tungsten silicide
`(WSiz), nickel silicide (NiSi2), titanium nitride (TiN), com-
`posites thereof, or like materials. The thickness of layer 28a
`should be thick enough to adequately fill the opening 24 of
`FIG. 5.
`
`FIG. 7 illustrates that a chemical mechanical polish
`(CMP) process, a resist etch-back (REB), and/or a blanket
`etch-back process is used to remove an upper portion of
`layer 28a. The chemical mechanical polishing (CMP) or
`planarization process of FIG. 7 results in the formation of a
`metal plug 28b by removing top portions of the layer 28a.
`This metal plug 28b substantially or entirely fills the opening
`24 illustrated in FIG. 5. The metal region 28b functions as
`a metallic gate electrode for the semiconductor device 10. It
`is important to note that the metal electrode 28b is self-
`aligned to the source and drain electrodes 26 and 28 illus-
`trated in FIG. 7 by virtue of being formed within the
`self-aligning opening 24. Also, a photoresist mask and
`oxide/plasma enhanced nitride etch process is utilized to
`subsequently form source and drain contacts to the source
`and drains of FIG. 7 (not specifically illustrated). These
`source/drain contacts may be formed after metal gate for-
`mation or may be formed concurrent with the metal gate
`formation whereby the source/drain contacts are made of the
`same material as the metallic gate in an inlaid or dual inlaid
`manner (see FIGS. 8—9).
`It
`is important to note that the metal material 28b is
`preferably a material having a mid-gap work function
`wherein the threshold voltages (V,) of both p-type and
`n-type transistors on the same substrate are compatible.
`Furthermore, due to the presence of a metal gate,
`the
`threshold adjust region 31 may either be avoided or reduced
`in doping concentration whereby high mobilities through the
`channel regions can be achieved. The metallic gate electrode
`28b has a higher conductivity than conventional polysilicon
`gate electrodes. Furthermore, the metallic electrode 28b of
`FIG. 7 will not suffer from polysilicon depletion whereby
`the effective thickness of the oxide 27 is not adversely
`affected. Furthermore, the metal gate 28b allows the gate
`oxide 27 to be formed as a tantalum pentoxide (TazOs) layer,
`titanium oxide (TiOz) layer, other high-k dielectrics, or
`composites thereof which is not easily integrated into a
`process flow which uses polysilicon gate electrodes.
`Furthermore, the substrate 12 of FIG. 7 may be provided as
`a silicon on insulator (SOI) substrate whereby the control of
`threshold voltages can be accurately achieved using the
`metallic gate 28b taught herein.
`It is important to note that the metal gate 28b in the
`process of FIGS. 1—7 need not be exposed to any high
`temperature processing whereby the metal gate will not be
`substantially damaged. Even though films, such as tungsten
`(W) and molybdenum (Mo), cannot adequately block ion
`implantation of source and drain atoms, this ion implanta-
`tion blocking property of the gate electrode is not needed
`when utilizing the self-aligned process taught herein (i.e.,
`the source and drain electrodes in FIGS. 1—7 need no gate
`electrode ion implant blocking properties in order to be
`properly formed). Furthermore, metallic adhesion of the
`metal gate 28b to surrounding oxides is improved over prior
`art devices, and no difficult metallic etch processing is
`needed in the device of FIG. 7. Also, the structure of FIG.
`7 will avoid or significantly reduce any metal-to-gate-oxide
`interaction which could substantially degrade MOS transis-
`tor performance. These advantages are also present in the
`other embodiments taught herein in FIGS. 8—18.
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`8
`FIGS. 8—9 illustrate a method which may be utilized to
`form a metal gate MOS transistor utilizing dual
`inlaid
`interconnect structures. FIG. 8 illustrates a semiconductor
`device 11 having regions 12—26 which are identical or
`substantially similar to similarly numbered elements in
`FIGS. 1—7. Due to the similarities of these elements to
`previously-discussed elements,
`these elements 12—26 in
`FIGS. 8—18 are not further discussed hereinbelow. FIG. 8
`
`illustrates that a plasma enhanced nitride (PEN) or like etch
`stop layer 30 is formed overlying the low temperature oxide
`(LTD) 22 previously taught. Another low temperature oxide
`or TEOS layer 32 is then deposited overlying the etch stop
`layer 30.
`A first photoresist mask (not specifically illustrated in
`FIG. 8) is used to form an opening 34 through the layer 32.
`This opening 34 is then extended through exposed portions
`of the etch stop 30 using a second plasma etch environment.
`The etch of layer 32 is preferably performed selective to the
`etch stop layer 30, and the etch of layer 30 is preferentially
`performed substantially selective to layer 22. A width
`dimension X of the opening 34 through the layers 32 and 30
`is illustrated in FIG. 8. In one embodiment, the photoresist
`used to form X is removed and a photoresist having the
`dimension Y is formed and the openings 36 (in layer 32) and
`the deepening of the layer 34 (into layer 22) are performed
`together in FIG. 9. In another embodiment, the photoresist
`used to define the feature X in FIG. 7 may be used to etch
`through the layer 30 and 22 to fully deepen the opening 34
`through the layer 22 before patterning the photoresist to the
`dimension Y. In either process, a “via first” inlaid trench
`process is shown in the embodiment of FIGS. 8—9. After
`formation of the opening 34, the photoresist layer used to
`pattern 34 is stripped from the surface of structure 11 and a
`second photoresist mask is utilized to define a second
`opening having a width dimension Y as illustrated in FIG. 8.
`FIG. 9 illustrates that the photoresist mask which contains
`the opening dimension Y is utilized to etch a wider opening
`having a dimension Y through the layers 32 and 30 above the
`opening having the dimension X. In addition, the opening 34
`is either previously etched as discussed with respect to FIG.
`8 through layer 22 or is now deepened to penetrate through
`the layer 22 and expose the plasma enhanced nitride (PEN)
`layer 20. A nitride etch is then utilized to remove portions of
`the nitride layer 20 and the nitride layer 30 which are
`exposed within the dual inlaid openings. It is important to
`note that the etch used to from the gate opening X in FIG.
`8—9 is also used to form dual inlaid source and drain contacts
`
`to regions 26 and 28 (these additional openings are not
`specifically illustrated in FIGS. 8—9 for simplicity).
`In
`essence, the dual inlaid gate 34 of FIG. 9 may be coupled to
`another gate and/or one or more source and drain electrodes
`of another device on the IC via the interconnect portion 36
`of FIG. 9. After removal of the layer 20 within the opening
`34, a wet silicide etch proce