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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria1 Virginia 22313- 1450
`wwwnsptogov
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`APPLICATION NO.
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` F ING DATE
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`FIRST NAMED INVENTOR
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`ATTORNEY DOCKET NO.
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`
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`CONF {MATION NO.
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`12/ 170, 191
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`07/09/2008
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`Masafumi Tsutsui
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`079195—0566
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`1644
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`05/10/2010
`7590
`53080
`MCDERMOTT WILMEMERY LLP
`600 13TH STREET, NW
`WASHINGTON, DC 20005-3096
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`WEISS, HOWARD
`PAPER NUMBER
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`ART UNIT
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`2814
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`MAIL DATE
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`05/10/2010
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`DELIVERY MODE
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`PAPER
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`Please find below and/or attached an Office communication concerning this application or proceeding.
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`The time period for reply, if any, is set in the attached communication.
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`PTOL—90A (Rev. 04/07)
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`IP Bridge Exhibit 2018
`IP Bridge Exhibit 2018
`TSMC v. Godo Kaisha IP Bridge 1
`TSMC v. Godo Kaisha IP Bridge 1
`IPR2017-01841
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`IPR2017-01841
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`

`

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`Office Action Summary
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`Application No.
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`Applicant(s)
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`12/170,191
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`Examiner
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`HOWARD WEISS
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`TSUTSUI ET AL.
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`Art Unit
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`2814 -
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`-- The MAILING DA TE of this communication appears on the cover sheet with the correspondence address --
`Period for Reply
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`A SHORTENED STATUTORY PERIOD FOR REPLY IS SET TO EXPIRE 3 MONTH(S) OR THIRTY (30) DAYS,
`WHICHEVER IS LONGER, FROM THE MAILING DATE OF THIS COMMUNICATION.
`Extensions of time may be available under the provisions of 37 CFR 1.136(a).
`In no event however may a reply be timely filed
`after SIX (6) MONTHS from the mailing date of this communication.
`If NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHS from the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
`Any reply received by the Office later than three months after the mailing date of this communication, even if timely filed, may reduce any
`earned patent term adjustment. See 37 CFR 1.704(b).
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`Status
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`1)IXI Responsive to communication(s) filed on 29 March 2010.
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`2a)I:I This action is FINAL.
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`2b)IZI This action is non-final.
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`3)I:I Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
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`closed in accordance with the practice under EX parte Quayle, 1935 CD. 11, 453 O.G. 213.
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`Disposition of Claims
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`4)IZI Claim(s) 15-36 is/are pending in the application.
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`4a) Of the above Claim(s)
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`is/are withdrawn from consideration.
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`5)I:I Claim(s) _ is/are allowed.
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`6)IXI Claim(s)fl is/are rejected.
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`7)I:I Claim(s) _ is/are objected to.
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`8)I:I Claim(s) _ are subject to restriction and/or election requirement.
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`Application Papers
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`9)I:I The specification is objected to by the Examiner.
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`10)I:I The drawing(s) filed on
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`is/are: a)I:I accepted or b)I:I objected to by the Examiner.
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`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
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`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121(d).
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`11)I:I The oath or declaration is objected to by the Examiner. Note the attached Office Action or form PTO-152.
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`Priority under 35 U.S.C. § 119
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`12)I:I Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)—(d) or (f).
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`a)I:I All
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`b)I:I Some * c)I:I None of:
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`1.I:I Certified copies of the priority documents have been received.
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`2.I:I Certified copies of the priority documents have been received in Application No.
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`3.I:I Copies of the certified copies of the priority documents have been received in this National Stage
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`application from the International Bureau (PCT Rule 17.2(a)).
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`* See the attached detailed Office action for a list of the certified copies not received.
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`Attachment(s)
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`4) D Interview Summary (PTO-413)
`1) D Notice of References Cited (PTO-892)
`Paper No(s)/Mai| Date. _
`2) D Notice of Draftsperson‘s Patent Drawing Review (PTO-948)
`5) I:I Notice of Informal Patent Application
`3) IZI Information Disclosure Statement(s) (PTO/SB/08)
`Paper No(s)/Mai| Date 1/22/2010. 6) D Other:
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`U.S. Patent and Trademark Office
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`PTOL-326 (Rev. 08-06)
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`Office Action Summary
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`Part of Paper No./Mai| Date 20100506
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`

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`Application/Control Number: 12/170,191
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`Page 2
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`Art Unit: 2814
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`Attorney's Docket Number: 079195-0566
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`Filing Date: 7/9/2008
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`Continuing Data: Continuation of 10/859,219 (6/3/2004 now U.S. Patent No. 7,205,615)
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`which is a continuation of 11/730,988 (4/5/2007 now U.S. Patent No.
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`7,417,289); RCE established 3/29/2010
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`Claimed Foreign Priority Date: 6/16/2003 (JPX)
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`Applicant(s): Tsutsui et al. (Umimoto, Akamatsu)
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`Continued Examination Under 37 CFR 1.114
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`Examiner: Howard Weiss
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`1 .
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`A request for continued examination under 37 CFR 1.114, including the fee set forth
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`in 37 CFR 1.17(e), was filed in this application after final rejection. Since this
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`application is eligible for continued examination under 37 CFR 1.114, and the fee set
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`forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action
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`has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on
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`3/29/2010 has been entered.
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`Claim Rejections - 35 USC § 103
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`. The following is a quotation of 35 U.S.C.103(a) which forms the basis for all
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`obviousness rejections set forth in this Office action:
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`(a) A patent may not be obtained though the invention is not identically disclosed or described as set
`forth in section 102 of this title,
`if the differences between the subject matter sought to be patented
`and the prior art are such that the subject matter as a whole would have been obvious at the time
`the invention was made to a person having ordinary skill
`in the art to which said subject matter
`pertains. Patentability shall not be negatived by the manner in which the invention was made.
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`This application currently names joint inventors.
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`In considering patentability of the
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`claims under 35 U.S.C. 103(a), the examiner presumes that the subject matter of the
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`various claims was commonly owned at the time any inventions covered therein
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`were made absent any evidence to the contrary. Applicant
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`is advised of the
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`obligation under 37 CFR 1.56 to point out the inventor and invention dates of each
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`claim that was not commonly owned at the time a later invention was made in order
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`

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`Application/Control Number: 12/170,191
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`Page 3
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`Art Unit: 2814
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`for the examiner to consider the applicability of 35 U.S.C. 103(c) and potential 35
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`U.S.C. 102(e), (f) or (g) prior art under 35 U.S.C. 103(a).
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`3. Claims 15 to 21 and 23 to 34 and 36 are rejected under 35 U.S.C. 103(a) as being
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`unpatentable over Xiang et al. (US. Patent No. 6,437,404) and Matsuda et al. (US.
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`Patent No. 6,870,230).
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`Xiang et al. show most aspects of the instant
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`invention (e.g. Figures 1
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`to 11)
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`including:
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`> MISFET 10 with an active region in a semiconductor substrate 110 and defined
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`between isolation regions 60,62 with said isolation regions’
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`lower surfaces
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`located in and in contact with the semiconductor substrate
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`a gate insulating film 58 made of the material claimed (Column 3 Lines 53 to 55)
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`a gate electrode 56 made of polysilicon or metal (Column 3 Lines 50 to 53)
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`source/drain regions 20,22 formed on both sides of said gate electrode and
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`comprising extended impurity regions 50,52, main impurity regions 64,66 and
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`silicide layers 26,28
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`a silicon nitride film 80,82 formed over the side surface but not on an upper
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`surface of the gate electrode and over and in contact with the source drain
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`regions
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`interlevel insulating film 86 formed on said silicon nitride film and sidewalls 70,72
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`formed on said gate electrode’s side surfaces
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`Xiang et al. do not show the main impurity regions being heavily doped and the
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`extended impurity regions being lightly doped and in contact with the main impurity
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`regions,
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`the gate insulating film formed only under a lower surface of the gate
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`electrode, a thin film interposed between the silicon nitride film and the source drain
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`regions, a contact plug that passes through the interlevel
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`insulating film and the
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`silicon nitride film in contact with the source/drain regions.
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`Application/Control Number: 12/170,191
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`Page 4
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`Art Unit: 2814
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`Matsuda et al. teach (e.g. Figures 2, 3 and 9) to form main impurity regions 12 being
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`heavily
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`doped and the extended impurity regions 7 being lightly doped and in
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`contact with the main impurity regions, to form a gate insulating film 3 only under a
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`lower surface of the gate electrode 6a, to form a thin film 8a between a silicon nitride
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`film 9a and the source/drain regions 7,12 and to provide a contact plug 16a to pass
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`through a interlevel
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`insulating film 13 and the silicon nitride film contacting the
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`source/drain regions to suppress the variation in the width of the sidewalls (Column
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`11 Lines 49 to 51). It would have been obvious to a person of ordinary skill in the art
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`at the time of invention to form a gate insulating film only under a lower surface of
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`the gate electrode,
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`to form a thin film between a silicon nitride film and the
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`source/drain regions and to provide a contact plug to pass through a interlevel
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`insulating film and the silicon nitride film to contact the source/drain regions as
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`taught by Matsuda et al. in the device of Xiang et al. to suppress the variation in the
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`width of the sidewalls.
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`In reference to the claim language pertaining to the ability of the silicon nitride film to
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`generate stress in the channel
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`region substantially parallel
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`to the gate length
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`direction, the claiming of a new use, new function, or unknown property which is
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`inherently present in the prior art does not necessarily make the claim patentable. In
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`re Best, 195 USPQ 430, 433 (CCPA 1977) and In re Swinehart, 439 F. 2d 210, 169
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`USPQ 226 (CCPA 1971); please see MPEP § 2112. Since Xiang et al. show all the
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`features of the claimed invention, the ability of the silicon nitride film to generate
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`stress in the channel region substantially parallel to the gate length direction is an
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`inherent property of Xiang et al. and Matsuda et al.’s invention.
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`4. Claims 22 and 35 are rejected under 35 U.S.C. 103(a) as being unpatentable over
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`Xiang et al. and Matsuda et al., as applied to Claim 15 above, and in further view of
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`Tatsuta (US. Patent No. 5,023,676).
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`Application/Control Number: 12/170,191
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`Page 5
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`Art Unit: 2814
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`Xiang et al. and Matsuda et al. show most aspects of the instant
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`invention
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`(Paragraph 3) except for the principle surface of the substrate being substantially in
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`the {100} plane and the gate length direction is substantially a <011> direction and
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`the silicon nitride film directly in contact with the side surfaces of the gate electrode.
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`Tatsuta teaches (e.g. Figure 3 and Column 1 Lines 44 to 66) to have the principle
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`surface of the substrate 101 to be substantially a {100} plane and the gate length
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`direction 102 is substantially a <011> direction and to have a silicon nitride film 109
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`directly in contact with the side surfaces of the gate electrode 103 as a typical
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`arrangement for a MISFET and helps to increase the transistor speed (Column 2
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`Lines 29 to 46). It would have been obvious to a person of ordinary skill in the art at
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`the time of invention to have the principle surface of the substrate to be substantially
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`a {100} plane and the gate length direction is substantially a <011> direction and to
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`have a silicon nitride film directly in contact with the side surfaces of the gate
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`electrode as taught by Tatsuta in the device of Xiang et al. and Matsuda et al. as a
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`typical arrangement for a MISFET and helps to increase the transistor speed.
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`5. Applicant's arguments filed 3/29/2010 have been fully considered but they are not
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`Response to Arguments
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`persuasive. In reference to the presence of lightly and heavily doped regions in the
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`source/drain regions, this is taught by Matsuda et al. as the amended rejections
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`above state. In reference to the formation of the gate insulating layer in Xiang et al.,
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`this can be accomplished by various means known to one of ordinary skill in the art.
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`One way would be to selectively grow an gate insulating layer on the exposed
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`substrate surface in the gap before forming the gate electrode. Another is leave the
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`dummy gate oxide layer 132 in the gap and then form the gate electrode on top,
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`especially if the optional channel implantation step is skipped (see Column 6 Lines
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`46 to 52).
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`In view of these reasons and those set forth in the present office action,
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`the rejections of the stated claims stand.
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`

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`Application/Control Number: 12/170,191
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`Page 6
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`Art Unit: 2814
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`Conclusion
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`6. Papers related to this application may be submitted directly to Art Unit 2814 by
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`facsimile transmission. The faxing of such papers must conform with the notice
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`published in the Official Gazette, 1096 OG 30 (15 November 1989). The Art Unit
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`2814 Fax Center number is (5??) 2?3~83flfl. The Art Unit 2814 Fax Center is to be
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`used only for papers related to Art Unit 2814 applications.
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`7. Any inquiry concerning this communication or earlier communications from the
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`examiner should be directed to Howard Weiss at (571) 272-1720 and between the
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`hours of 7:00 AM to 3:00 PM (Eastern Standard Time) Monday through Friday or by
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`e-mail via Jed If attempts to reach the examiner by
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`telephone are unsuccessful,
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`the examiner’s supervisor, Wael Fahmy, can be
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`reached on (571) 272-1705.
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`8.
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`Information regarding the status of an application may be obtained from the Patent
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`Application Information Retrieval (PAIR) system. Status information for published
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`applications may be obtained from either Private PAIR or Public PAIR. Status
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`information for unpublished applications is available through Private PAIR only. For
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`more information about the PAIR system, see http://pair-direct.uspto.gov. Should
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`you have questions on access to the Private PAIR system, contact the Electronic
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`Business Center (EBC) at 866-217-9197 (toll-free).
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`