l|||||||||||||Ill|||l|||||||||||llll||l|||||||||l|||||||||l||||||||||||l|
`
`U3006201733B1
`
`(13) United States Patent
`Hiraki et al.
`
`US 6,201,733 B1
`(10} Patent No:
`Mar. 13, 2001
`{45} Date of Patent:
`
`(54) SEMICONDUCTOR INTEGRATED CIRCUIT
`DEVICE, MEMORY MODULE AND
`STORAGE DEVICE
`
`(75)
`
`Inventors: Mitsuru l-llraki, liodaira; Shojl
`Shukur’i. Koganei, both of (JP)
`
`(73) Assignee: Hitachi, Ltd., Tokyo (JP)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`USJC. 15403) by 0 days.
`
`(21) Appl. No.: 09r435,035
`
`(23)
`
`Filed:
`
`Nov. 5, 1999
`
`(30)
`
`Foreign Application Priority Data
`Nov. 11, 1998
`
`(JP)
`
`
`
`Ill-320962
`
`Int. CL?
`(51)
`(52) US. Cl.
`
`(58) Field of Search
`
`
`GllC 16ft”
`
`365l185118; 365,118.509;
`365118511; 3155:1353}. 365300
`365;"18518. 185.09,
`365.318511, 185.33, 200
`
`(56)
`
`References Cited
`
`US‘ PATENT DOCUMENTS
`5,ott_.130 *
`9.3199?
`I-Iiguchi
`5,694,359 * 12mm Park .... ..
`5,812,468 *
`9.!1998 Shirley
`
`365r‘185.21
`
`.. Sim/185.09
`
`355.9200
`
`6,003,133 " 131999 Mollgltnnni etal.
`6,023,?“ a mom on
`
`713;“200
`113:1
`
`* cited liy examiner
`
`Primary Examiner—Richard Elms
`Assistant Examiner—Hiram Nguyen
`(74) Attorney. Agent, or Firm—Antonelli, Terry, Stout &
`Kraus, LLP
`
`(57)
`
`ABSTRACI‘
`
`To improve the efficiency for repairing a defect of a large-
`scale integrated circuit, a semiconductor integrated circuit
`device is formed of, a central processing unit (10), an
`electrically reprogrammable nonvolatile memory (11) and a
`volatile memory (12, 13) while sharing a data bus (16), and
`utilizes stored information of the nonvolatile memory to
`repair a defect of the volatile memory. This volatile memory
`includes a volatile storage circuit (IZAR, l3AR) for latching
`repair information for repairing a defective normal memory
`cell with a redundancy memory cell. The nonvolatile
`memory reads out
`the repair information from itself in
`response to an instruction to initialize the semiconductor
`integrated circuit device.
`In response to the initializing
`instruction,
`the volatile storage circuit
`latches the repair
`infortnation from the nonvolatile memory. No fuse program
`circuit is not needed for the detect repair, and a de feet which
`occurs after a burn-in can be newly repaired so that the new
`defect can be repaired, even after the packaging over a
`Circui1511b31f3‘6«
`
`16 Claims, 22 Drawing Sheets
`
`'
`
`‘3
`
`1A
`r"
`
`ADDRESS BUS
`_|
`REPAIR ENFORMATION
`i5
`14 s
`
`
`DRAM
`‘2
`l
`l
`_.= 1‘ AB FLASH MEMORY
`2
`saw
`
`11
`N BlTS
`.
`13AB N BIT“
`
`
`ADDRESS
`2
`11
`'~
`“not
`ADD 5
`
`B FFER 113m
`if
`BUFF R
`
`
`
`
`
`
`
`iSAC I H 13KB
`
`
`
`
`JJI'IOHIONOSIHVdWOO
`
`
`
`
`
`1'6
`DATA BUS (N BITS}
`
`1r
`NTF'IL BUS
`
`_.
`
`I
`
`'-'
`
`NVIDIA 1008
`
`1
`
`NVIDIA 1008
`
`

`

`US. Patent
`
`Mar. 13, 2001
`
`Sheet 1 0f 22
`
`US 6,201,733 B1
`
`OE.
`
`
`x”
`
`
`
`
`CO
`M
`PAWSON
`CHOU”
`
`
`mammmmmooq
`
`Fmmwmmoi
`
`mmmmam
`
`I.
`
`|;A
`
`
`FGE
`-Eezonémomgmime
`
`
`DDRESS
`0MPAHBO
`IRCUH
`
`
`C C
`
`_mmmjmzqmmmzmm
`
`
`
`2
`
`

`

`US. Patent
`
`Mar. 13, 2001
`
`Sheet 2 of 22
`
`US 6,201,733 Bl
`
`
`REPAIR INFORMATION (N BITS)
`
`REPAIR INFORMATION FOR SRAII
`REPAIR INFORMATION FOR DRAM
`
`
`
`
`
`I A80 IRE_D—ADB
`IRE_SI A83 I A32 I A31
`I
`SRANI DEFECT ADDRESS
`I
`DRAM DEFECT ADDRESS
`
`SRAM REPAIR
`ENABLE
`
`DRAM REPAIR
`ENABLE
`
`POWER ON
`
`RELEASE OF RESET
`
`RESET 5
`WLLD
`YSLO
`16 IDATA BUS)
`12AR (REPAIR ADDRESS REGISTER]
`
`I
`
`HIGH ISELECTI
`ON {SELECT}
`
`REPAIR
`INFORMATION
`
`INDETERMINATION
`
`M
`
`H
`13AR (REPAIR ADDRESS REGISTER);
`I
`:mfiqfig'gwfiffiglq
`
`.
`'
`
`IN DETERMINATION
`
`IR
`
`'
`
`IN DETERMINATION
`
`3
`
`

`

`US. Patent
`
`Mar. 13, 2001
`
`Sheet 3 0f 22
`
`US 6,201,733 B1
`
`FIG- 404)
`
`FIG. 4(3)
`
`PROBE INSPECTION 1
`
`81
`
`
`
`REPAIRING OF DEFECT
`
`32
`
`PROBE INSPECTION 2
`
`’33
`
`PACKAGING
`
`~34
`
`
`
`
`
`
`
`
` BURN-IN
`
`
`
`
`
`SS
`
`36
`
`SCREENING 1
`
`SCREENING
`
`REPAIRING OF DEFECT “’57
`
`SHIPPING
`
`SCREENING 2
`
`SB
`
`ASSEMBLE ° USE
`
`SHIPPING
`
`39
`
`ASSEMBLE - USE
`
`S10
`
`IT
`
`REPAIRING OF DEFECT “311
`
`4
`
`

`

`US. Patent
`
`M
`
`mm
`
`US 6,201,733 B1
`
`
`
`mo”.oznzmmom2
`
`-I'llllll-b
`
`
`
`IIIII1WIIIIIllllllllllllllllllllllllllllllllllfflflfiflflfi?IlLHHHHHflFiiJI..95IEDE1llllrlLllllllllflflflflflflfl.lllllllJflHflflflflwllllI.mn._§mHmV\mEmag;
`
`
`
`
`
`
`
`flIlllllllllllllllllIlllllllllllllIllllllfluflflflflflflllllIlillliiIIIIIII.
`
`
`%OZEE...._w>m.dQEIH
`
`
`m0235;.mSmj0200mm
`.lllllplllb N2mmnmonhxwE9:
`_z_mmomm302E;95TEE
`65E5E02%5.58
`
`«mi62E;Em:Em:
`
`IIIIJ
`
`32«we
`
`(I'll.VIIII-
`
`5
`
`

`

`US. Patent
`
`Mar. 13, 2001
`
`Sheet 5 0f22
`
`US 6,201,733 B1
`
`FIG. 6
`
`WORD LINE
`
`WL
`
`1' """"""""""" '1
`
`BL
`
`
`
`5
`: PL
`
`BIT
`LINE
`
`FIG. 8
`
`
`
`BIT LINE
`
`BIT LINE
`
`6
`
`

`

`US. Patent
`
`Mar. 13, 2001
`
`Sheet 6 of 22
`
`US 6,201,733 B1
`
`
`
`
`
`
`
`7
`
`

`

`US. Patent
`
`Mar. 13, 2001
`
`Sheet 7 0f 22
`
`US 6,201,733 Bl
`
`FIG. 9
`
`
`
`
`
`FIG. 10
`
`
`
`SOURCE LiNE
`
`BIT LINE
`
`8
`
`

`

`US. Patent
`
`Mar. 13, 2001
`
`Sheet 3 0f 22
`
`US 6,201,733 B1
`
`
`
`9
`
`

`

`US. Patent
`
`Mar. 13, 2001
`
`Sheet 9 0f22
`
`US 6,201,733 B1
`
`(PROGRAMMING
`STATE
`LOW THRESHOLD
`STATE
`
`(EHASE STATE
`HIGH THRESH LD
`STATE
`
`Ids
`
`1
`
`1
`
`NON-SELECT
`
`SELECT
`
`FIG. 13
`
`—‘IDV
`
`CG
`
`
`
`
`7"$
`[e— 30
`DR
`
`
`
`
`
`
`LOW THRESHOLD STATE
`
`HIGH THRESHOLD STATE
`
`LOGIC VALUE “0"
`
`LOGIC VALUE “1”
`
`1O
`
`10
`
`

`

`US. Patent
`
`Mar. 13, 2001
`
`Sheet 10 0f 22
`
`US 6,201,733 B1
`
`
`
`
`
`
`3
`
`54mm9
`
`
`
`I___39Imi
`{5LT\mmEa2mgwmmaoq
`
`CIRCUIT
`
`
`
`
`
`m:
`
`lull
`
`mammmwmamd.
`
`3GE
`
`
`
` mwzO_._.<EmOn_z_m_<mmm
`
`mmmmooq.
`
`mmnrsm
`
`
`
`
`
`
`11
`
`
`mam.55286%2Vmam53
`EU;2
`
`
`11
`
`
`
`
`

`

`US. Patent
`
`Mar. 13, 2001
`
`Sheet 11 of 22
`
`US 6,201,733 B1
`
`
`
`
`
`
`
`wwmmaoqFemmmoS.demwmmaoqPom.meEdmw>mO§mE193m
`
`
`
`
`
`
`
`msGE
`
`
`
`zO_._.<Emon_z_mEnmE
`
`
`
`
`
`
`
`zo_._.<2mon_z_mEammzo_._.<2mon_z_magmazo_._.<2mon_z_$.1me
`
`
`
`
`
`
`
`
`
`
`
`
`53%.mo“.24mmmon—>mO§w21min.mo;
`
`
`
`12
`
`
`
`gamma3%magmazémE95212d
`
`
`
`33%_BEEmaqummagma
`
`
`
`wmwanE.5me9
`
`12
`
`
`

`

`US. Patent
`
`Mar. 13, 2001
`
`Sheet 12 0f 22
`
`US 6,201,733 B1
`
`FIG. 16
`
`POWER ON
`
`RELEASE OF RESET
`
`'\
`RESETé
`HIGH (SELECT)
`wLI_0 i +—#~———~
`1
`ON (SELECT)
`YSLO I ..___.__._.. REPAIR
`:
`INFORMATION
`
`18 (DATA BUS):
`.
`12AR
`I
`(REPAIR ADDRESS REGISTER) ;
`;
`:
`
`ISAR
`(REPAIR ADDRESS REGISTER)
`
`HR
`
`INDETERMINATION
`
`W
`
`DRAM REpAm
`INFORMATION
`
`IN DETERMINATION
`WSRAM REPAIR
`INFORMATION
`
`IIAR
`
`:
`'
`
`W REPAIR
`INDETERMINATION
`'NFORMAT'ON
`
`13
`
`13
`
`

`

`US. Patent
`
`Mar. 13, 2001
`
`Sheet 13 of 22
`
`US 6,201,733 B1
`
`
`
`
`
`.2
`
` mam405.200
`3%2wmamE39.
`
`CONTROL CIRCUIT
`
`
`H.
`
`1.1
`
`N—
`
`wmmmooq
`
`mmuwsm
`
`E
`R PAIR
`AD
`HESS
`H
`ISTE
`HE
`
`D G
`
`CIRCUIT
`
`
`
`
`zo_._.<EmOu_z_EEmm
`
`3E
`
`
`
`
`
`14
`
`14
`
`

`

`US. Patent
`
`Mar. 13, 2001
`
`Sheet 14 Of 22
`
`US 6,201,733 Bl
`
`FIG. 18
`
`POWER ON
`:
`
`,
`gRUN STATE OF CPU
`
`I:>
`I
`RESETI
`RSTIT————I___
`
`I
`
`I
`
`I
`
`I
`
`I
`I
`
`I
`I
`I
`
`I
`I
`HIGH (SEL CT)
`0AA;
`“III 3m;
`«II—1U“ '
`OFF
`ON
`{AIONSELECU (SELECT)
`
`I
`
`E
`
`
`
`U
`
`OLKRI
`PWGI
`RBOI
`9531;
`mm 5
`I
`YSI_0§
`3
`
`-
`
`YSU
`
`16 (DATA BUS)
`
`12AR
`
`E
`
`I
`'
`I
`
`(REPAIR ADDRESS i
`I
`
`REGISTER
`
`SRAM REPAIR INFORMATION
`DRAM REPAIR INFORMATION
`INDETERMINATION
`
`DRAM REPAIR INFORMATION
`
`INDETERMINATION
`
`g
`
`SRAM REPAIR INFORMATION
`
`REGISTER
`
`INDETERMINATION
`
`15
`
`15
`
`

`

`US. Patent
`
`Mar. 13, 2001
`
`Sheet 15 0f 22
`
`US 6,201,733 B1
`
`tans.
`
`:SmE
`
`
`
`..E232 Egg
`
`mFGE
`
`Eu
`
`5%
`
`
`
`16
`
`16
`
`

`

`US. Patent
`
`Mar. 13, 2001
`
`Sheet 16 0f 22
`
`US 6,201,733 Bl
`
`VSS
`
`,_
`5
`8
`O
`l.-
`2
`'5
`
`O‘
`
`\I—
`:3
`0.
`z
`
`VDD
`
`INPUT/
`OUTPUT
`DATA
`
`VOLTAGE STEP-
`DOWN CIRCUIT
`31DR —
`U
`
`VOLTAGE THIMMING
`INFORMATION
`
`I
`
`FLASH MEMORY
`.0
`
`DATA Bus —
`
`17
`
`17
`
`

`

`US. Patent
`
`Mar.13,2001
`
`Sheet 12 0f 22
`
`US 6,201,733 BI
`
`31
`
`VGE1
`
`VQD
`
`REFERENCE
`VOLTAGE
`GENERATION
`
`CIRCUIT
`
`__ ' REGISTER VOLTAGE
`
`VOLTAGE TRIMMING
`
`
`
`‘5
`
`STEP-DOWN
`CIRCUIT
`
`18
`
`18
`
`

`

`US. Patent
`
`US 6,201,733 B1
`
`
`
`
`
`zgwflmmwmM023:ImmEmmEE
`
`EC
`
`DN.
`
`‘_
`
`._.20
`
`mw_bi$538amA20
`7;ma“a$5292TH:
`
`2"2m2u.mm5%mm
`3,__zoEEEomE>m$452,m$3mozmmmmm
`w.W:zoma
`
`40>
`
`19
`
`19
`
`

`

`US. Patent
`
`Mar. 13, 2001
`
`Sheet 19 0f 22
`
`US 6,201,733 Bl
`
`
`
`Q5 REF
`
`w I
`
`H
`
`REFRESH
`
`REFRESH
`
`l
`
`j
`
`l
`
`REFRESH
`PERIOD
`
`DATA
`
`HOLDING
`PERIOD
`
`I
`
`E
`
`‘
`
`REFRESH
`PERIOD
`
`20
`
`20
`
`

`

`US. Patent
`
`Mar. 13, 2001
`
`Sheet 20 0f 22
`
`US 6,201,733 Bl
`
`
`
`--
`
`<mmF
`
`mm_n=._n_s_<
`
`mwzmw
`
`mom?
`
`Han—.50
`
`mun—mam
`
`
`
`wsmFED9
`
`
`
`
`
`
`
`21
`
`21
`
`
`

`

`US. Patent
`
`Sheet 21 0f 22
`
`US 6,201,733 B1
`
`
`
`zo_22mon_z_mEnmm
`
`
`m.02.22:Emégaqmmag;62::32%n,25%2828;mEOEE
`225250
`
`
`
`
`zQEEmEz.zogfimomz
`
`ll|II
`
`mmGE
`
`Imemm52%
`
`
`
`20.238;mEnmE29.258;mEnmm
`
`
`
`
`
`
`
`2922.;szEEME
`
`
`
`
`
`
`
`magma24mmmagma52%$0szImam:
`
`
`
`m._m<2m_332m392mmEmmm
`
`
`
`mmmmogmmmmggmmwmanESwims
`
`
`
`
`
` samem8Eqmmm8
`
`
`
`E052Imam:mom
`
`24mm$0sz12E EEEEEEEEEEEEEEEEEEEEE
`
`SEE24mgHowmmm
`
`22
`
`22
`
`

`

`US. Patent
`
`Mar. 13, 2001
`
`Sheet 22 0f 22
`
`US 6,201,733 Bl
`
`FIG. 26
`
`
`
`23
`
`23
`
`

`

`US 6,201,733 Bl
`
`l
`SEMICONDUCTOR INTEGRATED CIRCUIT
`DEVICE, MEMORY MODULE AND
`S'IURAGE DEVICE
`
`BACKGROUND OF 'l‘HE 1N VEN'l'lON
`
`The present invention relates to a semiconductor inte-
`grated circuit device in which a volatile memory, such as a
`DRAM (Dynamic Random Access Memory) or a SRAM
`{Static Random Access Memory). and an electrically rewrit-
`able or reprogrammable nonvolatile memory, such as a flash
`memory, are packaged together with a control processing
`unit. such as a central processing unit, over a semiconductor
`substrate; and, more particularly, the invention relates to a
`repair technique which is effective when applied to an
`on-chip type large-scale integrated circuit, such as a DRAM-
`consolidated LSI {Large-Scale Integration), a DRAM-
`embedded LSI or a system LSI.
`Nowadays. the large scale of a semiconductor integrated
`circuit device is in the category of a system onchip, such as
`a DRAM—consolidated LS], a DRAM-embedded L8] or a
`system LSI.
`As a semiconductor integrated circuit device is provided
`with a larger scale, its internal defects can be less ignored.
`Especially. a memory, such as a DRAM, a SRAM or a flash
`memory, is expected to have a relatively small area, but a
`large storage capacity, so that
`it becomes susceptible to
`defects caused by the remarkably fine working during manu-
`facture and the resultant miniaturization of signals.
`Therefore, the application of a redundancy circuit technique
`to such semiconductor circuit devices is important so that an
`expected system operation can be achieved irrespective of
`the occurrence of more or less defects.
`
`til
`
`15
`
`25
`
`39
`
`35
`
`For enlarging the scale of a semiconductor integrated
`circuit device, it is frequently desirable to apply a trimming
`technique for achieving the desired circuit characteristics.
`By this trimming technique, an analog amount, such as an
`internal voltage or current, and a quasi-analog amount, such
`as the timing of a timing signal, can be sufficiently brought
`to a desired valtte irrespective of the manufacturing disper-
`sion of the semiconductor integrated circuit device.
`The redundancy circuit technique and the trimming tech-
`nique for a
`large-scale semiconductor integrated circuit
`device are well-known. One such technique is disclosed in
`Japanese Patent Laid-Open No. 334999f1995, and in corre-
`sponding US. Pat. No. 5,561,627, of Hitachi, Ltd, and is
`used in a program for providing defect repair information
`using the memory cells of an electrically reprogrammable
`nonvolatile memory, such as a flash memory.
`In this
`technique, repair information specifying a defective memory _
`cell in the nonvolatile memory is stored in the memory cell
`of the nonvolatile memory; the repair information is latched
`in an internal latch circuit at the time of initialization; and
`the latched repair information and an access address are
`:-‘JI
`compared so that
`the access is replaced, in the case of ‘
`coincidence, by the access to a redundant memory cell.
`On the other hand, another technique is disclosed in
`Japanese Patent Laid—Open No. 214496.!1998, and in corre—
`sponding US. Patent application Ser. No. U9r016300, of
`Hitachi, Ltd, and in which trimming information is stored
`for use in the storage region of a portion of a nonvolatile
`memory, such as a flash memory. In accordance with this
`technique, more specifically, there is provided a trimming
`circuit
`for
`finely adjusting the output clamp voltage of
`voltage clamp means for providing an operating power
`source for the flash memory so that the trimming informa-
`tion for determining the state of the timing circuit is pro-
`
`56
`
`'
`
`2
`grammed in the memory cells of the flash memory. The
`programmed trimming information is read out in a reset
`operation from the flash memory and is internally trans—
`ferred to a register. The state of the trimming circuit is
`determined by using the transferred trimming infomation.
`As a result, the clamp voltage to be outputted from voltage
`clamp means is trimmed to a value suitable for the operation
`of the flash memory, thereby compensating For the manu-
`facru ring dispersion of the semiconductor integrated circuit
`device.
`
`An example of a system LSI is described on pp. 34 to 38
`of "Electronic Materials“ {issued in January, 1998, by
`Kabushiki Gaisha Kogyo Chosakai), wherein, as seen in
`FIG. 4 thereof, a volatile memory, such as a flash memory,
`and a DRAM are consolidated together with a CPU (Central
`Processing Unit). The technique for forming the nonvolatile
`memory and the DRAM by a common process is already
`described in US. Pat. No. S,tl57,448. On the other hand,
`examples of a semiconductor integrated circuit device pack-
`aging a flash memory and a DRAM together with a CPU on
`one semiconductor substrate are described in Japanese
`Patent Laid—Open Nos. 52293r'1989 and 124381r1998.
`
`SUMMARY OI" THE lNVEN'l'lON
`
`Our preceding patent application has proposed the use of
`storage elements ofone flash memory For repairing a defect
`or to effect
`trimming within a closed range of the flash
`memory. In view of the large-scale integration represented
`by a system on-chip, we have investigated the elficient use
`of a nonvolatile memory, or one circuit module packaged in
`the largenscale integrated circuit device in relation to another
`circuit module. In the course of this investigation, we have
`considered the utilization of the stored information of the
`
`nonvolatile memory to repair a defect of a volatile memory,
`other than the nonvolatile memory itself we have recognized
`the following new problems in the investigation of such
`repair of a volatile memory.
`In order to provide the nonvolatile memory with the
`required repair information, more specifically, a procedure is
`needed to reflect
`the repair information on the volatile
`memory. This reflection of the information desirably should
`be realized at a high speed, even it' the amount of repair
`information increases, to cope with an increase in the defects
`in accordance with the construction of the volatile memory
`or the provision of a large storage capacity.
`In studies subsequent
`to that
`investigation, Japanese
`Patent Laid-Open No. 131897;“1994 has been found,
`in
`which it
`is proposed to use a programmable ROM for
`repairing a defect
`in the cache memory. However,
`the
`programmable ROM in this case is a dedicated circuit
`element belonging to a redundancy memory control circuit
`in the cache memory, but represents no more than a repairing
`technique in the closed range of the cache memory, and has
`failed to adequately address our aforementioned problems,
`even if it is resultantly compared.
`An object of the present invention is to provide a semi-
`conductor integrated circuit device which is capable of
`improving the changing efliciency of a coupling change,
`such as a defect repair, in a circuit having a large scale logic
`constntetion, in which a nonvolatile memory made acces~
`sible by a control processing device and a volatile memory
`are packaged.
`Moreover, an object of the present invention is to realise
`a cost by improving the yieid ol‘a semiconductor integrated
`circuit device which has been strictly demanded to have a
`lower cost because of its large-scale logic.
`
`24
`
`24
`
`

`

`US 6,201,733 B1
`
`3
`Another object of the present invention is to improve the
`usability of a memory module by consolidating the speci-
`fications of the defect repair of the memory module in a
`semiconductor integrated circuit device having a volatile
`memory, such as a DRAM or a SRAM, as the memory
`module.
`
`1?)
`
`15
`
`25
`
`39
`
`35
`
`Still another object of the present invention is to provide
`a data storage device in which there is stored design data to
`be used for designing a semiconductor integrated circuit
`device by using a computer.
`The foregoing and other objects and novel features of the
`invention will become more apparent froln the following
`description when taken with reference to the accompanying
`drawings.
`Representative aspects of the invention to be described
`herein will be briefly summarized in the following.
`A first semiconductor integrated circuit device (1A, 1C)
`accord ing to the invention comprises, over one sem iconduc-
`tor substrate: an electrically reprogrammahle nonvolatile
`memory (11) capable of being accessed by a control pro-
`cessing device (Ill), such as a central processing unit; and a
`volatile memory (12, 13) capable of being accessed by the
`control processing device, so that the stored information of
`the nonvolatile memory may be utilized for a connection
`change to effect a defect repair of the volatile memory.
`Specifically, the volatile memory includes: a plurality of first
`volatile memory cells, such as normal volatile memory cells,
`and a plurality of second volatile memory cells, such as
`redundancy volatile memory cells, and a volatile storage
`circuit (lZAR, BAR) for holding coupling control infor-
`mation for enabling the first volatile memory cells to be
`replaced by the second volatile memory cells. The nonvola-
`tile memory includes a plurality of nonvolatile memory
`cells, some of which are used for storing coupling control
`information, so that the coupling control infortnat ion is read
`out from the nonvolatile memory cells and outputted by the
`reading and setting operations of the coupling control
`information, such as an instruction to initialize the semicon-
`ductor integrated circuit device. The volatile storage circuit
`is caused to fetch and store the coupling control information
`from the nonvolatile memory by the reading and setting
`operations.
`A second semiconductor integrated circuit device (113)
`according to the invention additionally utilizes the stored
`information of a nonvolatile memory for repairing a defect
`ot‘the nonvolatile memory. Specifically, the volatile memory
`includes: a plurality of normal volatile memory cells and a
`plurality of redundancy volatile memory cells; and a volatile
`storage circuit (IZAR, BAR) for holding the repair infor-
`mation for repairing a defective normal volatile memory cell
`by replacing it with one of the redundancy volatile memory
`cells. The non-volatile memory includes:
`a plurality of
`normal nonvolatile memory cells and a plurality of redun-
`dancy nonvolatile memory cells; and a volatile storage
`:-‘JI
`circuit (UAR) for holding the repair information for repair- .
`ing a defective normal nonvolatile memory cell by replacing
`it with one of the redundancy nonvolatile memory cells.
`Some of the nonvolatile memory cells are memory cells for
`storing the information needed for repair of the volatile
`memory and the information needed for repair of the non-
`volatile memory. The repair information, as stored in some
`nonvolatile memory cells, is read out from the nonvolalile
`memory cells by executing reading and setting operations,
`such as an operation to initialize the semiconductor inte-
`grated circuit device, and is fed to and held in the volatile
`storage circuit
`in the volatile memory and the volatile
`storage circuit in the nonvolatile memory.
`
`_
`
`56
`
`25
`
`4
`According to the first and second semiconductor inte-
`grated circuit devices, the information for coupling control,
`such as defecl repair,
`is programmed in the nonvolatile
`memory in place of elements, such as the fuse elements, so
`that the fuse program circuit, the might otherwise be needed
`for using the fuse elements, can be eliminated. Accordingly,
`the use or step in the manufacture of an apparatus, which is
`liable to have a relatively high price, such as a laser cutting
`apparatus for cutting a fuse, can be eliminated to lower the
`cost of manufacture. When the fuse elements are provided,
`they need to be positioned at a relatively high layer portion
`over the semiconductor substrate so that they can be cut even
`in the presence of a layer which makes the fuse cutting
`diflicult, such as an aluminum wiring layer to be used for
`wiring the semiconductor integrated circuit device or a
`copper wiring provided to make the signal propagation delay
`time shorter. For this structural reason and for avoiding
`thermal damage to an insulating film or surface protecting
`film covering the semiconductor substrate surface by a laser
`beam used to cut the fuse, an opening for the laser exposure
`has to be formed in the insulating film or the surface
`protecting film over the fuse elements. Because such a
`complicated manufacturing process is required, the semi-
`conductor integrator] circuit device itself has a high price. In
`addition, when the fuse elements are provided, their size
`reduction is restricted by the need to provide openings for
`the laser exposure. so that the semiconductor substrate takes
`on a relatively large size. If the fuse program circuit is not
`used,
`the manufacturing process is simplified. When a
`nonvolatile memory is utilized for storing the coupling
`control information, it is possible to enjoy an advantage in
`the information can be reprogrammed at an arbitrary time
`and several times. This makes it possible to sulficiently cope
`with the coupling change for a defect which occurs at a
`relatively later step in the manufacturing process, such as the
`burn-in step in the manufacture of the semiconductor inte-
`grated circtlil device, or a coupling change for a defect
`which occurs after the packaging over the system or the
`circuit substrate has aged. As a result, a Circuit having a
`large-scale logic construction, in which a volatile memory is
`packaged together with a nonvolatile memory, can be suf-
`ficiently utilized because it can be changed after manufac-
`ture. Therefore, a cost reduction can be realized by improv«
`ing the yield of the semiconductor integrated circuit device
`having large—scale logic.
`The data input terminals of the individual volatile storage
`circuits (UAR, EAR, BAR) are coupled to a data bus (16)
`with which the individual data inputioutput terminals of the
`nonvolatile memory and the volatile memory are commonly
`connected, so that the coupling control information output-
`ted from the nonvolatile memory can be transmitted through
`the data bus to the corresponding volatile storage circuit by
`the operations to read out and set
`the coupling control
`information, such as the initialization produced by the
`control processing device, such as the central processing
`unit. As a result, the general-purlxtse utility of the nonvola-
`tile memory can be warranted with respect to access to the
`nonvolatile memory by the control processing device.
`If there is adopted a construction in which the volatile
`storage circuit in the volatile memory is connected with the
`data bus, no consideration need be given to the addition of
`special wiring lines for transmitting the coupling control
`information, such as the repair information, even when the
`number of volatile memories is increased.
`
`If the hit number of the entire coupling control informa-
`tion is less than that of the data bus, the coupling control
`information may be programmed in parallel
`in all
`the
`
`25
`
`

`

`US 6,201,733 B1
`
`5
`volatile storage circuits by connecting the signals lines of the
`data bus separately with the data input
`terminals of the
`individual volatile storage circuits.
`When the scale of the semiconductor integrated circuit
`device is large, the frequency of coupling changes against
`defects is accordingly increased to raise the probability of
`increasing the coupiing control information. When the data
`bus width, i.e., the bit number of the data bus is small for the
`increased coupling control information, the individual vola-
`tile storage circuits can be programmed in series with the
`coupling control information.
`in this case, when the cou-
`pling control
`information is consecutively read out
`in a
`plurality of divided cycles from the nonvolatile memory
`cells and outputted to the data bus in response to a setting
`operation instruction, such as an instruction to initialize the
`semiconductor integrated circuit (levice, the coupling con-
`trol information to be fed for each reading cycle through the
`data bus may be consecutively fetched and held for each of
`the reading cycles by the volatile storage circuit.
`Especially in view of the large-scale integration repre—
`sented by the system on-chip,
`the following items will
`become apparent. More specifically, in order that the non-
`volatile memory, or one circuit module or memory module
`packaged on the large-scale integrated circuit device, may be
`efficiently utilired in relation to another circuit module or
`memory module, the stored information of the nonvolatile
`memory is utilized for coupling control, such as a defect
`repair of a volatile memory other than the nonvolatile
`memory. In this case, the means for effecting transfer of the
`coupling control information through the data bus and the
`series internal
`transfer of the plurality of cycles of the
`coupling control information is excellent in that. when the
`information or an objective of the coupling control, such as
`a defect, increases with an increase in the capacity of the
`volatile memory, the process to reflect the control informa-
`tion on the individual volatile memories in accordance with
`an increase in the amount of control information can be
`
`realized at a high speed.
`In order to program the volatile storage circuit with the
`coupling control information using a simple construction,
`the volatile storage circuit may hold the coupling control
`information cutputted from the nonvolatile memory,
`in
`response to a first state indicating the reset period of a reset
`signal (RESET) instructing the initialization of the semicon-
`ductor integrated circuit device, and the control processing
`device may start a reset exceptional operation in response to
`the change of the reset signal from the first state to a second
`state indicating the release or end of reset. In this case, the
`reset signal has to be kept in the first state for the period
`necessary for programming the coupling control informa-
`tion.
`In other words, the reset release timing by the reset
`signal should not be premature.
`In order to provide a suficient time for programming of
`the coupling control
`informatiOn without any substantial
`restriction on the reset release timing of the reset signal,
`there can be provided a clock control circuit ('19, 20) which
`is initialized in response to the first state (or reset period) of
`the reset signal (RESET) instructing the initialization of the
`semiconductor integrated circuit device. In response to the
`change of the reset signal from the first state to the second
`state, the clock control circuit causes the volatile storage
`circuit to fetch and hold the coupling control information
`from the nonvolatile memory, and then the central process—
`ing unit is allevved to start the reset exceptional operation.
`Since the nonvolatile memory is reprogrammable,
`the
`coupling control information programmed in advance may
`
`1*?)
`
`15
`
`25
`
`39
`
`35
`
`:-‘JI
`‘
`
`56
`
`'
`
`6
`accordingly be erroneously programmed. In order to exclude
`this disadvantage as much as possible, it is advisable to
`allow the nonvolatile memory to be set by a mode bit (MBZ)
`to an operation mode to allow the reprogramming of the
`nonvolatile memory cells for storing the repair information
`and to an operation mode to inhibit the reprogramming.
`On the other hand. it is also possible to set by a mode bit
`(M131) an operation mode to allow the reprogramming of the
`nonvolatile memory cells by a write device connected to the
`outside of the semiconductor integrated circuit device, and
`an operation mode to allow the reprogramming of the
`nonvolatile memory cells in accordance with the execution
`of an instruction by the central processing unit. Then, the
`coupling control information can be programmed either on
`a packaged board (or on—board) or by the write device. In
`order to easily realize the coupling change corresponding to
`a defect which will occur after the packaging of the semi—
`conductor integrated circuit device. it is desired to support
`the on-board programming mode.
`In order to update the coupling control information, such
`as a demand for repairing a defect due to the on—board
`programming, the nonvolatile memory may store a diagnos-
`tic program. The diagnostic program causes the central
`processing unit
`to execute operations to detect a defect
`against the nonvolatile memory and the volatile memory and
`to program the repair
`information storing nonvolatile
`memory cells of the nonvolatile memory with the repair
`information for repairing a newly defective memory cell.
`A third semiconductor integrated circuit device (30)
`according to the present invention extends the information,
`as stored for use in the nonvolatile memory (11), to one other
`than the information used for
`the repair of a defect.
`Specifically,
`the semiconductor
`integrated circuit device
`(30) comprises, over one semiconductor substrate, while
`sharing a data bus (16): a control processing device, such as
`a central processing unit (10]; an electrically reprogram-
`mable nonvolatile memory {'11) which is able to be accessed
`by the control processing device; and a volatile memory (12,
`13) which is able to be accessed by the control processing
`device. The nonvolatile memory and the volatile memory
`individually include register means (llAR, IZAR, 13AR,
`AR, SlDR, 12DR, 13DR) having data input terminals con-
`nected with the data bus, so that their individual functions
`are partially determined according to the function control
`information set by the individually corresponding register
`means. The nonvolatile memory includes a plurality of
`nonvolatile memory cells, some of which are used for
`storing initialisation data containing the function control
`information. On the other hand, the nonvolatile memory has
`an operation mode to allow the reprogramming of the
`nonvolatile memory cells for storing initialization data and
`an operation mode to inhibit the reprogramming, so that the
`initialization data. are read out from the nonvolatile memory
`cells and outputted in response to an instruction to initialize
`the semiconductor integrated circuit device. In response to
`the instruction to initialize the semiconductor integrated
`circuit device,
`the register means fetches and holds the
`initialization data from the nonvolatile memory.
`In this third semiconductor integrated circuit device, in
`order to load each register means reliably with a large
`amount of initialization data in response to a
`reset
`instruction, there may be provided a clock control circuit
`which is initialized in response to the first state of the reset
`signal for instructing the initialization of the semiconductor
`integrated circuit device. In response to the state change of
`the reset signal from the first state to the second state, for
`example, this clock control circuit outputs a first timing
`
`26
`
`26
`
`

`

`US 6,201,733 Bl
`
`7
`signal having a plurality of phases shifted in activation
`timing from one another, and then outputs a second timing
`signal for causing the control processing device to start the
`reset exceptional operation. In response to the activation
`timing of the first timing signal having a plurality of phases,
`the nonvolatile memory reads the initialization data con—
`secutively in a plurality of divided cycles from the nonvola-
`tile memory cells and outputs them to the data bus. The
`register means performs an input setting operation to fetch
`and hold the data of the data bus consecutively for all
`reading cycles of the initialization data from the nonvolatile
`memory.
`The nonvolatile memory can utilize the information held
`by a corresponding one of the register means, as repair
`information for
`repairing defective normal nonvolatile
`memory cells by replacing them with redundancy nonvola-
`tile memory cells.
`The volatile memory can utilize the information held by
`the corresponding one of the register means, as repair
`information for repairing the defective normal volatile
`memory cells by replacing them with redundancy volatile
`memory cells.
`The volatile memory may be constructed to include
`dynamic memory cells as the volatile memory cells and to
`utilize the information held by the register means cone-
`sponding to the volatile memory, as the control information
`for specifying the refresh interval of the dynamic memory
`cells.
`
`I?)
`
`15
`
`25
`
`39
`
`35
`
`The volatile memory may also be constructed to utilize
`the information held by the corresponding one of the register
`means, as control information for specifying the timing of an
`internal control signal.
`In this third semiconductor integrated circuit device, like
`