_’/
`4213334)
`
`‘
`
`
`
`fisf'EJECTRUM
`
`
`E'MAII.
`PERVASIVE * ND PEESIIASIVE
`(
`
`
`
`
`
`
`Irr-
`\__f‘, i.
`u A“
`
`
`
`ENGINEERING
`PERIODICAL
`
`
`
` OCTOBER1992 @> THE INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS. INC.
`
`AMAZON 1012
`
`Page 1 of 7
`
`AMAZON 1012
`Page 1 of 7
`
`

`

`lEE
`
`
`
`
`SPECTBURL
`
` SPEClAL REPORT
`
`22 E-mail: pervasive and persuasive
`
`58 Fuzzy fundamentals
`By EARL COX
`Elna global network has the power to
`Applied where appropriate way logic
`5break through boundaries at time.
`
`can greatly simplify many .sgstems. But
`Edislance. and politics. Tetrla 3. Perry and
`
`:John A, Adam 22. Engineers using e-
`successlul implementation: require that
`the designer thoroughly understand the
`‘ imail collaborate on complex designs
`
`with colleagues they've never met. Tekla
`system dynamics. And it‘s a good idea
`
`to follow an orderly desigr: procedure.
`8. Perry 24. Fantasy games.
`personalized magazines, and even digital
`
`dating draw leisure-time users into the
`
`net. John A. Adam 29. E-mail networls
`
`
`are empowering democratic actions in
`
`governments at all sizes trom small US.
`
`towns to the lormer Soviet Union. rem
`
`
`62 Consolidating
`European Power
`By HENRI PERSDZ and
`JEAN REMONDEULAZ
`
`SPECIAL REPC‘iRT
`
`54s High-speed DRAMs
`A group oi industry experts reports that main-memory chips at last are catching up with
`microprocessors—in various ways. Richard Comedord and George E Watson 34. Fast
`computer memory, Ray N9 36. Fast DRAMs for sharper TV (see below). Hoeioi H.W.
`Setters 4|). A new era ol last dynamic RAMS. Fred Jones. Betty Prince, Roger Norwood. Joe
`Harrigan, Wilbur C. Vogtey. Charles A. Hart. and David Bonderant 43. A last path to one
`memory, Mitre Fannwatd and David Mooring so. A RAM link lor high speed. Stein Gjessing,
`David a Gustavsorr, David it James, Glen Stone, and Hans Wr'ggers 52. Fast interlaces tor
`DFtAMs Richard C. Foss, Betty Prince. Richard Rodgers, David B Gustavson, David It Janm,
`Glen Stone, and Stephen Kempainen 54.
`
`Energy interdependence between west
`and east Europe is expected to grow as
`plans go into reflect in increase the
`electric energy interchange Between the
`two regions Synchronization of the grids
`is a preferred option.
`
`'79 Howard S. Jones Jr.
`By JOHN A. ADAM
`Over a 37-year career. Howard S. Jones
`Jr's work on antenna design did much
`
`
`
`
`
`I
`
`to make us. Army missile technology
`possible. Now in semi-retirement. Jones
`does his utmost to encourage minority
`students to study engineering.
`
`3 t
`
`E
`
`_
`
`.IrmHair-II
`
`
`r...
`
`
`
`AMAZON 1012
`
`Page 2 of 7
`
`AMAZON 1012
`Page 2 of 7
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`

`

`66 The art of architectng
`complex projects
`By EBEHHARDT necnrrn
`
`
`
`—
`3 Newslog
`6 Forum
`7 Calendar
`8 Graphics
`11 Innovations
`
`" 12 Books
` 19 legal aspects
`74 Software reviews
`
`
`
`5
`
`
`
`78 EEs’ tools & toys
`90 Technically speaking
`
`92 Scanning THE INSTITUTE
`
`
`
`
`
`
` COVCI': Electronic messages travel over a global
`
`
`
`92 Coming in Spectrum
`
`network unbounded by time zones. distance or political
`entities in Gus Sauler‘s conceptual illustration. Wlttr email.
`an engineer can communicate with a colleague hallway
`around the world as easily as with a coworker down the
`traitThatechnclogy. still in its lnlancyis changing society
`astel'aswgfless- WSW“ W0" 9"“3”
`mm °" ‘1 .22‘
`
`
`
`
`
`
`
`
`
`
`
`
`How a system is created, designed. and
`
`
`built blends art and engineering. NASA's
`
`Deep Space Network is the product of
`such a process. Here, great antennas
`peer into space from its Canberra.
`Australia, station. The article describes
`the architecting process and provides
`additional calamities
`
`
`
`
`
`
`l
`
`SPECTRAL LlNEB
`
`
`
`
`
`
`21 Challenges to
`
`
`
`
`
`
`
`
`
`IEEE SPECTRUM (ISSN WQZSSHS published moome tu The
`Institute oi Electrical and Electronics Engineers Inc All rimts
`reserved. © 1992 try The Institute at Elachlcal and Electronics
`Engineerslnc.345East4itht.Newmm m1sz
`address:
`ITHIPLEE. Tater 236411, Fax: 2121057453. Ema‘l:
`leecspectrum.
`ANNUAL suascarmorvs. IEEE rrlemhcrs snoo included in
`dues Nonmernbers: 32995. Lhrariesdnslitutions: $139
`SINGLE comes. Members: so Nonmembers: srs
`By DONALD CHRISTlANSEN
`I
`.
`' mucous
`..
`-
`-.
`..
`-
`flcfiflgflm’m “"5 mm
`Screntrlrc management gives
`POSTMASTER:Pleasesendaddresscha1goslolEEESpocoum.
`ambiguous guidance today. Nevertheless
`
`
`on Coding Depamml. rare Service one; 445 Hoes Lane.
`managers have to select among
`amraai.nscamn.roeassSacmcrasspoana
`‘at
`..
`New m M and mm Mm m WWW
`traditional. perhaps outmoded. concepts
`
`5125634138
`MI W
`and contemporary techniques. perhaps
`
`
`:23“ 3,649
`cfifififlfi‘md:
`I
`fads. to develop a sell-consistent
`-
`par: rum rs a mem
`malahons,
`mean
`
`mm mm on
`management process
`. mamas
`d N .
`
`
`Association Publications
`
`
`
`EDIIDR AND PUBLISHER Donald Christiansen
`
`MANAGING EDIIDR: Allied Rosenblatt
`
`
`SENIOR TECHNICAL EDIFDR: Gadi Kaolin
`SEMOR EOIIORS: Trudy E. Bell. Richard
`Comedord. Tekla s Perry. Michael .I
`Riemnman. George F. llltatson
`SENIOR ASSOCIATE EDIIDRS' John A. Adam.
`Glenn Zorpette
`HEADQUARTERS: New tbrlr City 2127057555
`SURE/IDS: WW DC, John A. Adam.
`2025443790: SAN FHANCISCQ Tetrla 5.
`Perry. 415232-3606
`
`CORRESPONDENTS: Fred Guterl. Roger Milne
`(tendon); Bradlord Smith (Pa'is): .lohrr Blau
`(Dilssclrlorlt Robert llwsol (Born); John Mann
`(Barcelona): Stuart M. Damorot. Roger Schreltler
`(Tokyo): Kim Nair-Hieon (Seoul) Chris Brown
`(lanai: Peter Gwrme‘thoFonu): Tow
`Healy (Sydney. Illustrator Christopher Trump
`(brute); Axel de Tristan (Rio de Jaroiro):
`Kevin L. Sell (Houston)
`
`CHIEF COPY EDIIUR: Margaret Eastman
`COW EDITOR: Sally Cahur
`EDITORIAL RESEARCHER: Alan Gardner
`
`CONTRIBUTING EDITORS: Karl Esch, Ronald K
`Jurgen. Michael F. Weill
`EDITORIAL SUPPORT SERVICES:
`Rita Holland (Maria
`)
`EOIIDRML ASSIS
`: Rarnona Poser. Desks: Noel
`DESIGN CONSULMNI' Gus Sauter
`
`OPEMIIONS DIRECIDR‘ Fran Zapgulla
`BUSINESS MANAGER Robert T. Floss
`PRODUCTIONAND HUMITY CONTROL:
`Carol L. White (Director)
`EDITORIAL PRODUCHON'
`Marcia Meyers (Manager)
`Peter Rullett (lypographar)
`Mom's Khan (Technical Graphic Artist)
`ASSOCIATE PUBLISHER: \ttiliam ll. Saunders
`ADMINISTRARVE ASSISMNT Carmen Cruz
`MAIL UST SALES: Shelly Newman (MW).
`leelte Graciani
`ADVERTISING PRODUCROM
`
`Theresa Fitzpatrick (Manager). fiercest: Silvestrl
`MARKETING DIRECTOR Arthur C. Nico
`PROMOTION MANAGER: Robert [1 Moran
`RESEARCH MANAGER: Hendrik Prlns Manager)
`Carl leibman (Associate)
`I
`‘
`
`IMMUNE SEE/ICES Eric Sontag (ml-ism!)
`ADMINISTRATIVE ASSISMT ID THE EOIIOR
`
`AND PUBLISHER: Nancy T Hanonan
`
`
`Advisory Board
`CMMAM‘ GP. Hodn'gue
`Grates it Meander. a Leonard Carlson, Donald
`Flackenstoin. Ruben W, Lucky. Irene D. Peden. Gary
`
`R Spitch Jerome 1 Soran. volltam R Tacirabcny
`
`
`Editorial Board
`CHAIRMAN Donald Chr'otiansen
`Robert A Bell. Dennis Dodson. Kiell Carlson. W.
`BerradCarlson.JarnesE. Commitm-
`iee. Jacques .l. Glade Robot 5. Cooper. Malcolm
`R Ernie. RobertRDaridson.MmayEden.AlorHiltS.
`RobertR.Johnson.TedGleuislrItlchaal5EUm
`Tsugio Makimoto. Edith w. Marlin. Bruce c Mather.
`M. Granger Morgan. David It Ramon. Allred R.
`Potvin.W.DavidPricer.BeltyPriice.RibA.Flm
`Bruce l1 Shtiver. Stephen [1 Weinstein
`
`[SEE SPECTRUM OCTOBER 1952
`
`-——————————_
`
`AMAZON 1012
`
`Page 3 of 7
`
`AMAZON 1012
`Page 3 of 7
`
`

`

`
`
`Fast computer memories
`
`Designers are searching
`for new DRAM technologies
`to reduce memory access
`time and so unleash
`computer performance
`
`
`
`of chip makers. beta-ruse innovative architec-
`tures distinguish a variety of recent high-
`speed DRAMs. which go by such names as
`synchronous. cached, and Rambus DRAMs.
`The newcomers may be usefully surveyed
`froma system perspective. tosee how they
`may solve dedan Pl'OblemB. particularly with
`regard to main memory.
`in the familiar
`It'll! LIIE. Till now.
`stored-program computer described by von
`f the price-to—performance
`Neumann, the processor has been connect-
`ratio of computer systems
`ed directly to memory (as well as to
`is to keep improving. the
`input/output). From this model. a hierarchi-
`gap in speed between pro-
`cal memory system has evolved in which a
`cessors and memory must
`little. very fast memory is placed very close
`be closed. Processors per-
`to the processor and fed by lots of slower
`form at their peak only
`when the flow of instruc-
`memory farther away from the processor
`[Fig.1]. This hierarchy, which is used in al-
`tionsanddatah’ommemoryisfastandun-
`most all computer systems today. reflects
`faltering.
`one of computer design’s truisms. “fast
`An ever-flowing stream is particularly
`necessary to reduced~instruction-set com-
`memory is expensive and slow memory is
`M.Il
`puting (RISC) processors. which have be-
`Atthefiratlevelofthehierarchyare the
`come very poptdar chair; the last few years.
`processor's internal registers. Access to
`A heavily pipelined RISC processor can ex-
`these registers is very fastbecause they are
`ecute an instruction every clock cycle,
`on the processor chip. However, their num-
`demanding a lot of the memory syste.
`ber is limited by the available chip area. or
`Both superscalar processors. with their mul-
`“real estate.”
`tiple functional units. and rmrlliprocessor
`At the second level. between the proces-
`' machines make even greater demands on
`memory systems.
`sor and slower main memory. is a cache—a
`Nor is the centml processing unit (CPU)
`small, very fast memory. The cache is load-
`
`the only consumer of memory band-
`width. Computers now are expected to
`beeasiertouseandrnorecapablethan
`their predecessors. and seme of the
`new capabilities will require speedier
`memory. Examples include the rapid
`display of high-resolution graphics in
`true color. the recognition of speech
`
`they exploit a general characteristic of pro-
`grams: locality in sparse and time. Spatial lo—
`cality indicates that ii a location in memory
`is accessed. then others nearby will proba-
`bly be accessed soon;
`temporal locality
`means that if a location in memory is ac-
`cessed once. then it will probably be ac-
`cessed again soon.
`One problem with caches is that. in order
`to be effective. they require very fast We
`thatrunataboutthesamespeedastbepro—
`cessor; and wln'h static RAMS (SRAMs) can
`deliver the required speed. they are expen-
`sive. Also. caches must keep track of which
`memory blocks are in the cache and what
`their state is. and therefore require a spe-
`cial controller and a tag memory that add
`complty and take up precious board real
`estate. All the same, caches are popular.
`It is possible, too. to build systems with
`more than one level of caching. using on- and
`off-chip memory. Many modern processors
`have on-chip caches. for both program irr-
`structions and data. that are closer than an
`extemal cache and so faster to accesa. But
`like the number of registers. the whoa have
`to be small because chip real estate is limit-
`edandinmanysystemstheyaresup—
`plemented with an external cache. The in-
`ternal cache is referred to as first-levelcache
`and the external as second-level.
`The third level of the hierarchy is
`main memory itself. Main memory is
`used to store programs and data. and
`as a source of input and destination for
`output. Typically. this memory is much
`larger than cache and is constructed of
`DRAMs. which are slower than the
`SRAMs but also less expensive.
`The fourth level of the hierarchy is
`mass storage. Today magnetic-disk
`storage is ubiquitous. It is used to im-
`plement a technique called virtual
`memory. which fools the processor into
`thinking the main memory '3 much larg-
`erthanisthecase. Withvirnralmemory, the
`processor’s address space is divided into
`blocks of fixed size. calledpages. Pages are
`much larger than cache blocks. usually 4—
`8K bytes.
`Disk bears much the same relationship to
`main memory as main memory does to
`cache. Pages are called from disk and placed
`in main memory when they are needed or
`retrrmedtodislrwhentheyarenot. Aswith
`cache. the principle otlocality is basic. To
`maintainorderinthe system, amemory
`management unit (MMU) liceps track of
`which pages are in main memory and what
`
`
`
`Processors can perform
`their best only if
`the supply of instructions
`and data is fast
`'
`and
`
`
`back video and audio. and. ultimately,
`support of a virtual-reality environ-
`merit. The machines may also need
`buffer memory for messages moving
`over the multigimbit—per—second net-
`worksexpectedinthenearfuttne.
`These lofty llO ambitions all
`involve
`processing and moving large mounts of
`data. On topofevenfaster CPUs. they will
`strain bothrnemorycapacityandmemory
`bandwidth.ButtheaooepteddynarmcRAM
`(DRAhDarchitecnrresandsolutionshave
`beenpushedtotheiriimits.Abasicchange
`mar-chitectureseemstheonlywaytnob-
`tainanurgentlyneededincreaseinmemo-
`rrspeed-
`musedforchangehassmuamrmher
`
`Ray No Sun Microsystems Inc
`
`edwithcopiesofthoseblocksofdatastored
`inmain memory that the processorismost
`h'kelytowarrtfortheoperafionitiscurrently
`
`from lfitofia bytes.)
`lftheprocessorfindsthedataitwantsin
`thecache (referredtoasacanhe hit). then
`totheprocessoritwilllookasifmainmem-
`oryisasfastascache. Butifthe processor
`doesnotfindwhatitneedsinmchemcache
`miss),thentheblockcontainingthemiss-
`ingdatamusthebroughtinfrommainmem—
`ory, slowing down the system.
`Cadresusuallyprovideaspeedupbemuse
`
`001$9235B2I33m©1992 IEEE
`
`IEEE SPECIRUII OCIOBBR rssa
`
`AMAZON 1012
`
`Page 4 of 7
`
`AMAZON 1012
`Page 4 of 7
`
`

`

`
`
`units speed, is 5-10 timesthatof DRAM.
`Homenhecausethecharxeleaksaway
`fromtheDRAM cell's capacitor, it musthe
`restmedbyperiodicreh'eshhig.nlsqtl1ead
`ofreadmgaDRAMinvolvestransferringand
`sensingmeredribblesofchargeminceeaeh
`readoperadondisMrbsthecefloontentth,
`toqreqruresthatthedatareadberestored.
`For-fagiesereasoneDRAMsaremtespecni
`1y
`t.
`ADRAMisbuiltasasquareorrectangw
`lar array ofcells [Fig. 2]; to read or write
`data.theprocessorsendsanaddresstoflie
`DRAM, which typimlly it multiplexes, sup-
`flyimfirsttheruwaddressthentheoohnnn
`address. For currently available DRAMs.
`thetimeittakesarowaddresstoaecessa
`oeflisabmfldO—SOnsforacohlmnaddress.
`about 20-40 ns, andtheprecharge fimeis
`about30-50ns.’l'husthecyclefime(flne
`minimumamountof time between memo-
`ryaecessesbythepmeessor)isabout]10—
`150ns.lneontrast,thecellsinsmallCMOS
`SRAMsmaybeaccessedeverySns;larg-
`er SRAMs have a longer access time of
`about lfins.
`’lbraisetheiroperaling speed. DRAMs
`haveaspecialopemfingmodethatlakesad-
`vantage of their internal row-and-coiumn
`structure.lrnownaspagemode.lnthis
`mde,whenmentirerow(orachippage,
`Mmttobeeonfusedwiththevhmalmem-
`ory page)isreadintothesense amplifiers,
`lheuserwnkeeptherowactiveandmere—
`
`lychanaeoolmnnaddressestoaooessallthe
`data.Aslongastheaccessesremaininthe
`pm. the DRAM can work faster. For cur-
`remDRAMe,thepage—m0decycletime(or
`minimum time between column addresees)
`isabout_40-50 ms [Fig 3].
`SEEIII IPIIII III". A main memo-
`rysystemhasthreecrucial attributes: size,
`latency,andthrmrghput.Sizeisaffectedby
`density. orthenumberofbitsthatcanbe
`packedintnagivenareanhehighertheden-
`sity‘,thebetter. latencyishowlongittakes
`fordatatobedeliveredafterithasbeenre-
`matedandiscloselyrelatedtoaDRAM's
`access time; the shorter the latency. the
`fisstertheDRAMJhmugimtitisameasme
`oihowmmhdatamnbeddivemdinagiven
`periodoitime,andiscloselyrelatedtotbe
`DRAM cycle time; a higher throughput
`meansthataDRAMdeliversmomdataper
`timeinterval.WhilethedensityofDRAMs
`hasbeenmxadruplingmughlyeverythree
`years. neither theirseoessnortheircycle
`timeshaveimpmvedasrapidly.hnpmv'mg
`tbelatencyandthmughputofmammemo-
`ryisthefocusofattenh'onamongmemm‘y
`systemdesigners.
`Pagemodemay reducelatencyandin-
`creasethrwghput.butonlyifthereisabt
`of sequentiality in the memory reference
`stream;iornniltipmcessorsystems,thisis
`nothuefiacbeadoagoodjobofisolafing
`the processor from relatively sluggish main
`memory,butthereisonlysonmchamcbe
`
`.
`
`Soulcs. Toehitll Corporallun
`
`[ZJIuathicalDRAMJuchasfiMM-byébflmwrnm, fiendualmmoflny
`infiebwrightisamemdflmughpeiudsuommemwandwlmnaddnsscs. Theron:
`addmmmmdaminmmmbemdimthem-amflifierI/Omfimu which
`mmmmmmmmmmamemmnmdaamwfiz
`
`01
`
`02
`
`
`DJ
`
`04
`
`Level 1
`
`Level 2
`
`Level 4
`
`Level 3
`
`fljlnmosicmrterMbJatheW
`memory consists ofe hierarchy ofmedr'a.
`Passingfmntheloptobouamofflwm.
`ch}; thedensityoftlwmedium (theme:
`ofdafaitmn stonperunitam) increases,
`whileihspeedindelioefingdataaudilswst
`per bit decrease. Some new dynamic RAM
`(DRAM) technologies on» atsimphfiingflns
`Wacky by speeding upmar'n memory to the
`point wherethenesdfiirasepnmu, external
`cache is moot.
`
`their status is.
`As with a cache miss, performance falls
`off whenever a page is not in main memory
`when needed (a page fault). The penalty is,
`however. higher because mechanical disks
`are much slower than semiconductor main
`memory. Butdiskssmverycheaninterms
`of cost per hit, and can store vast amounts
`of data; hard disks today commonly store
`hundreds of megabytes, and the use of
`magneto-optical and optical discs capable of
`storms gigabytes is growing.
`Strictly speaking, there is a fifth level of
`storage. fordatathatwillnotbe usedforan
`extended period of lime or whose impor-
`tance demands its preservation. This ar-
`chival storage often consisls of magnetic
`tape; of course, removable magnetic and op-
`tical discs are also used for long-term stor-
`ageofpmgramsanddata. Thisstnragelevel
`has no impact onrun-fime system operation
`and so will be ignored for now.
`IIII MT. Main memory is almost always
`implemented using DRAMs. which in both
`speed and price lag behind the SRAMs
`generally used tor cache. DRAMs use one
`mnsistor-mpadtor pair. referred to as a cell,
`to store one bitd’iniomation, while SRAMs
`use a four- or six-transistor flip-flop to store
`eachbit. BemuseeachDRAMcellisvery
`small. DRAMscanbe made verydense; the
`demest DRAM now available is a 16M-bit
`part, whilethedensest SRAMisahoutth
`bits. The per~bit cost of SRAM. depending
`
`3" fi—MMM
`
`37
`
`
`AMAZON 1012
`
`Page 5 of 7
`
`AMAZON 1012
`Page 5 of 7
`
`

`

`l
`
`candoThetimeittakestoaervieeamche
`miss is directly rehted to the main memory’s
`latency so, with increasing processor
`speeds, cache misses have an ever greater
`impact on system performance, even when
`the hit-to-miss ratio is high.
`mmmm. The most common
`method of increasing memory system
`throughput is interleavhrg [Fig 4]. The idea
`here is to use not one. but several identical
`arrays of memory, or banks.
`in its simplest form. interleaving spreads
`out the memory addresses so that adjacent
`addresses occupy adjacent banks. The mnn-
`berofbsnksused, N, is a powerofl Ifan
`address yields a remainder of 0 when divid-
`edbyN(oraddressmoduloN- 0), then
`itnesidesinhankD; ifaddressmodulo N a
`1, then it resides in bank 1, and so forth.
`The net effect of interleaving is to finesse
`the memory bandwidth. or tlnoughput, by
`afactorofN: Nwordsarereadeachmem-
`ory cycle instead of only one. The N words
`are stored in a register. freeing the memo-
`ry banks to process the next access. If the
`memory addresses accessed are mostly se-
`quential. this form of interleaving works
`well; if they are not, it does poorly.
`Anotherlorm of
`while more
`
`Normal mode
`
`\I
`
`complex. worksbetterfornonsequential ac-
`cesses. k with the simple use, memory is
`divided into Nmodules and addresses are
`assigned to banks in the same way. In this
`case. however, the memory controller lakes
`on the additional responsibility of schedul-
`ing accesses. It looks at each separate re-
`questandschedulesitinsuchawayasto
`make maximum use of the data bus. The
`controller's objective is to overlap operation
`between memory banks as much as
`possible.
`Even though interleaving is popular and
`helpt'ul. it runs into several problems. For
`oner filling a wider bus may require too much
`memory. Also, to maintain the interleave,
`memory has to be upgraded in increments
`ofN.Iastlyinterlesvingcanresultinbulky,
`complex memory systems.
`While all these tedmiques have been used
`to improve systems perfomrance. they will
`not be able to cope with the faster pro-
`cessors in the offing. A new memory ar-
`chitecture is needed, and in addition. the
`physics of the interconnections must be kept
`in view.
`Designers of tnrly high-speed memory
`systems have to treat memory paths as
`transmission lines: their impedance has to
`
`HA5
`
`075
`
`Address
`
`W—E
`
`no
`
`as
`
`I Valid data
`- How
`- Colman - Don‘t care
`RT5=rowaccessslrobs;CAS=cohrmaccessstroDe;VTE=Mheenable.
`00 = data inpulroutpul: & a (moot enable.
`
`I Undefined
`
`[3jlnanonrralDRAM_mdcycle, MWMMmlyaflerbothmwnudwlumnad-
`dmseshawbeensupphed.flomr; wkmallthedatamededissmmdinthesammwm
`Mummedsmmnbycham'ngrhc column address only: aflermh change, the newly
`Wantonmmmwfidunfilmmmmoddrmrsmdwd.
`
`38
`
`be carehrlly controlled and paths have to be
`correctly terminated to reduce reflections,
`As for the parasitic capacitance and induc-
`tance of the I/O driver/receiver, the device
`packaging, and the printed-cm't board's
`traces, they have to be minimized and their
`effects taken into account.
`High throughput demands high transmis-
`sion rates. Since traditional TTL- and
`CMOS-level drivers and receivers cannot
`achieve the speeds necessary. new 110
`drivers with low-voltage swings. carefully
`controlled slew rates, and the abilityto drive
`a tenninated bus are required.
`In selectinga high-speed interlace. a ma-
`berofrelatedfactorshavetobe considered:
`the interface should be simple. effective,
`economical, wider supported, and easy to
`use, and should conserve power.
`As speed increases. so. too, does the sig-
`nificance of schemes for distributing clock
`signals. Sophisticated techniques will have
`tobe usedto control clock skew—the differ-
`ent times of arrival of the same clock signal
`at scattered points in the system. Also, the
`delay introduced by the clock distribution
`network within each chip has to be con-
`trolled. Both skew and delay should be kept
`as low as possible.
`New clock architectures should also be
`Considered. Instead of distributing a central
`clock to all the chips in the system (global
`synchronization), it may pay to ship a copy
`of the clock along with the data (source syn-
`chronization).
`HIE omens. Several new high-speed
`DRAMs solve some of the foregoing prob-
`lems. Synchronous DRAMs resemble con—
`ventional DRAMs, and so are merely an
`evolutionary step in DRAM technology.
`They differfr'om earlyparts in that allinputs
`and outputs are referenced (synchronized)
`to the rising edge of a clock pulse. Another
`difference is that, when a read operation is
`performed. more than one word is loaded
`mtoahigh-speedshiftregister; dresewords
`are shifted out, one word per clock cycle.
`As a result. synchronous DRAMs can have
`very high burst rates. (Note that some early
`synchronous DRAM designs use an inter-
`nallypipelined design that operatesonasin—
`gle word only.)
`A synchronous DRAM running at 100
`MHz has four times the bandwidth of page-
`mode DRAMs. However. access times are
`no faster than for conventional DRAMs.
`Some synchronous DRAMs do have a
`"wrap" feature, for servicing cache miss-
`es. They deliver a burst of perhaps four or
`eightcyclesofdata, withtheaddressedword
`appearing first, followed by the reminder
`of the blodr. and then wrap back around to
`the beginning of the block.
`A memory system built out of syn—
`chronous DRAMS has a peak (ideal) band—
`width equal to the system's clock frequen-
`cy multiplied by the number of data lines in
`the system's bus. While the bandwidth ac—
`tually delivered will. of course, be less than
`this,
`the memory bandwidth is drrectly'
`
`IBEE SPECTRUM OCTOBER 1992
`
`AMAZON 1012
`
`Page 6 of 7
`
`AMAZON 1012
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`

`
`
`proportional to the clock frequency.
`To derive the maximum benefit from
`these DRAMs. therefore, acomputermust
`be designed to run the memory system at
`ahighclockrate.’l'hisrequireeverycareful
`design. butthehighlmrstrateotsomesyn-
`chronous DRAMs makes it possible to use
`narrower memory paths than would be re-
`quired for conventional DRAMs.
`At present, some vendors are sampling
`parts based on a synchronous DRAM ar-
`chitecture, and theJoint Electmn Device En-
`gineering Coundl Oedec) is preparing a stan—
`dardforthemthatwillheavailabletoany
`interested party.
`II TIEII III. The cached DRAM is a pro-
`prietary development of Tokyo's
`Corp.,fromwhichsamplesareavailahle. Be-
`causeacachedDRAMhasasmallSRAM
`cache inserted between its extemal pins and
`an internal DRAM. accesses that hit sloca-
`tioninthe cachearemuchfastertlmntypi-
`cal DRAM accesses. Also. the cachesfill
`bandwidthisveryhighbecausethebuscon-
`nesting the SRAM and DRAM is very wide.
`ln system configurations where memory
`is connected directly to the processor.
`cached DRAM may replace the external
`cache. However.
`the memory controller
`mustperformthefimctionsofacacheoon-
`trollerandmaintainasetoftngRAMs.
`Another proprietary scheme. Rambus
`from Ramhus lnc.. Mountain View. Calif.,
`offers a complete and radical solution to
`building a memory system. Its specification
`describes the protocol, elect-ital interface.
`clocking scheme. the register set. device
`packaging and pinout. and board layout.
`
`Although its peak transfer rate is 500
`megabytes per second. actual memory
`handwidthislesabecauseaddressmontrol.
`anddataarealltnnsmitted overthessme
`setofwires.Thehandwidththatisinfna
`achieved depends on two factors:
`the
`amount of data transferred during each
`unnsaaiou.and(sincetheschemeinvolves
`caching)thehitrate.'l‘heamormtofover-
`headioreachtransferisfimd,sohuse£fi-
`
`ingalOOpercenthitrate,thepeakread
`handwidthiorthe45M-hitpartisabout360
`Mbyteslsiorfit-bytetranders;tortheIBM-
`hit part. which is fasterI it is about 400
`Mbytes/s. Bandwidth decreases if the hit
`rate or transfersizedecreases.
`WhatdoesRamhusmeanior-thesystem
`designer? Because eachchipisan indepen-
`dententity.veryfewareneededtobuilda
`memorysystemand.bearuseeachchiphas
`huilt-indeoodingandhitdetectionlogicthe
`memorycontrollercanbesimpler.lfthehit
`rateishighenwgh. itmayevenhepossi—
`ble to connect the processor directly to
`memoryandeliniinatethecsche.Aspecial
`Rsmbus interface. containing the 110
`drivers. phase-locked loop. and miscella-
`neous logic.
`is needed to interface to
`Rambus.
`SinceRamhusistheoreticallyacookbook
`solution.thedesignerneedmtworryahout
`
`issues;thedetailshaveal|beentakencare
`of. But because each device does much
`more than an everyday DRAM. Rambue
`DRAMs may cost more.
`Rambus is a proprietary technology
`
`M—Fuocmpuurmmrie-
`
`Taiwanesme
`Wkonthebasisofaddrsssmodulesflc
`mmmwmsmbym
`Winfield, wthr'sapwerof
`2);bfcaussfiebaukscanb¢accesudiuour—
`Wigwam throughput cauch
`Mfirmmhafldwof NJutlnsinr-
`MWJHMMMWW-
`Whyammcontmflim.fisiror¢-
`mmmnmm,mmm'm'
`Wmmw newMitre
`mmlfdmfimtstoudaudacmsed
`fiomcorrumh‘waddnsusmmmm
`mommies-Immune
`bkmflmfldWmMfieW
`inwhichthebanksddimdatatothcmm
`bnsmnbemw tropism' W.
`
`ficensedtomannl‘actmersofDRAMsand
`applicanon-specific [Cs (ASICs). ‘Ibslu‘ba.
`Fujitsu. and NEC are an-rently sampling
`Rambus DRAMS. The Ramhus haterface
`cellisavailshlefromatewASleendors,
`and'lhshihaflanstomakeASleersrons‘ of
`theRamhusoontrolleravailahle.
`RamLinkisanattempttotahesomeofthe
`work done for the Scalable Coherent Inter-
`faoe(SCDandadaptitioruseasaDRAM
`
`requiredregistersmndtheelectzical hater-
`fsce. whichisadifferenfialintertace.%ile
`Ramfiukdoesnotspedfydevicepinoutsor
`boardlayout,itisinmanywayssimilarto
`Rambosfihechiefdifferenceisthatkam-
`Lhikisbasedonaring.ratherthanbus.to-
`
`to point—and
`RAM are therefore point
`point-to-point connections can run faster
`thanbusedcomrections.’l‘hedisadvantage
`daringtopologyisthattherequestand
`replypacketsmusttraversetheentirering.
`Eachnodeontheringaddssomeannnd
`delay,sothe|atencycanbeveryhigh:Rsrn-
`Linkallowsuptosdnodes.
`ItisantidpatedthattheRathkspecifi-
`cationwillbeanIEEEstandardmA)
`whenworlr'noomplete.Novendorsanrert-
`lyofferaRamLinkpart.
`must. Main memoryisthesingle
`mosteimensiveiteminacomputcrsystem.
`TheeunentcostofDRAMisabmrtUSSliO
`amegahyte.AtypicalPCtodaycomeswith
`about4Mhytesexpandabletoperhaps16M
`hytesntypimlhidr-endworkstationcornes
`withsbout32Mbytes,and<nnholdupm
`512Mhytes.DRAMsareoommodityparts
`whose price is driven by volume. Any
`DRAMenimnoemeIInmstofleraclearhen—
`efitatasmallprice difference.
`AnyDRAMsohrtionthatcanetinn‘natethe
`needforacsche,yetcostlittleornonme .
`thanconventimalDRAMs,cwldbeoiu3e
`in personal computers. low-end worksta-
`
`IIII‘I'IEIIIII.RayNgisamemberoi
`ureteclmicalstaflctSunMicrosystemhn.
`anflathew,Calif..whueheisinvolved
`withthedevelopmentofmemorysystems
`for RISC-based workstations and future
`computersystems.
`Q
`
`39
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`AMAZON 1012
`
`Page 7 of 7
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`AMAZON 1012
`Page 7 of 7
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