United States Patent c191
`Heath et al.
`
`[t l) Patent Number:
`(45) Date of Patent:
`
`5,038,320
`Aug. 6, 1991
`
`[54) COMPUTER SYSTEM WITH AUTOMATIC
`INITIALIZATION OF PLUGGABLE OPTION
`CARDS
`
`(75)
`
`Inventors: Chester A. Heath; John K. Langgood,
`both of Boca Raton, Fla.; Ronald E.
`Valli, Pittsburgh, Pa.
`
`(73) Assignee:
`
`International Business Machines
`Corp., Armonk, N.Y.
`
`[21) Appl. No.: 296,387
`
`(22) Filed:
`
`Jan. 6, 1989
`
`[63)
`
`Related U.S. Application Data
`Continuation of Ser. No. 21,391, Mar. 13, 1987, aban(cid:173)
`doned.
`
`Int. CJ.s ......................... G-06F 13/00; G06F 7/04
`[51)
`[52) U.S. CI .................................. 364/900; 364/948.5;
`364/944.61; 364/975.2; 364/976.4; 364/945;
`364/929.5; 364/929.2; 371/11.1
`[58) Field of Search ... 364/200 MS File, 900 MS File;
`340/825.07, 825.06, 825.52, 825.06; 371/11.1,
`11.2, 11.3, 66, 7
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`3,480,914 11/1969 Schlaeppi ............................ 364/200
`3,510,843 5/1970 Bennett ............................... 364/200
`3,573,741 4/1971 Gavril ................................. 364/200
`3,818,447 6/1974 Craft ................................. 340/172.5
`4,003,033 1/1977 O'Keefe .............................. 364/200
`4,015,244 3/ l 977 Simpson .............................. 364/200
`(List continued on next page.)
`
`FOREIGN PATENT DOCUMENTS
`0041406 9/1981 European Pat. Off ..
`0087368 8/1983 European Pat. Off. .
`0121331 3/1984 European Pat. Off. .
`0121381 10/1984 European Pat. Off. .
`0136178 4/1985 European Pat. Off. .
`0179981 6/1985 European Pat. Off ..
`0171073 2/1986 European Pat. Off ..
`0182044 5/1986 European Pat. Off ..
`0200198 11/1986 European Pat. Off ..
`
`3508648 9/1986 Fed. Rep. of Germany .
`50-120935 9/1976 Japan .
`(List continued on next page.)
`
`OTHER PUBLICATIONS
`IBM TDB vol. 20, No. 7, Dec. 1977, Input/Output
`Device Address Recognition Mechanism.
`(List continued on next page.)
`
`Primary Examiner-Gareth D. Shaw
`Assistant Examiner-Paul Kulik
`Attorney, Agenr, or Firm-Winfield J. Brown, Jr.;
`Robert Lieber
`ABSTRACT
`[57)
`A data processing system includes a planar board hav(cid:173)
`ing a central processing .unit (CPU), a main memory
`unit, and input/output (1/0) sockets or slots, each
`adapted to receive a selected one of a plurality of differ(cid:173)
`ent and/or similar option cards. each card contains (or
`is connected to) and controls a respective peripheral
`device; and each card is pre-wired with an ID value
`corresponding to its card type. Software programmable
`option registers on each card store parameters such as
`designated default (or alternate) address information,
`priority levels, and other system resource parameters. A
`setup routine, during initial power-on, retrieves and
`stores the appropriate parameters in the I/O cards and
`also in slot positions in main memory, one position being
`assigned to each slot on the board. Each slot position is
`adapted to hold the parameters associated with the card
`inserted in its respective slot and the card ID value.
`That portion of main memory containing the slot posi(cid:173)
`tions is adapted to maintain the parameter and ID infor(cid:173)
`mation by means of battery power when system power
`fails or is disconnected, i.e., a nonvolatile memory por(cid:173)
`tion. Subsequent power-on routines are simplified by
`merely transferring parameters from the table to the
`card option registers if the status of all the slots has not
`changed since the last power-down, system reset, or
`channel reset.
`
`18 Claims, 7 Drawing Sheets
`
`l'QSHPOWER O• SW TEST) S£T\IP
`
`RESET CHANNEL
`
`•COMPllE EICH 10 VAWE Willi
`: ID VALUE IM RES?B:TIVE
`SI.OT ltSITION
`
`ID MISlll.ltH:
`INVOlE INITIALIZATIOll
`S!T~P P~R.111
`
`OLYMPUS et al. EX. 1016 - 1/16
`
`

`

`5,038,320
`
`Page 2
`
`U.S. PATENT DOCUMENTS
`
`4,025,903 5/1977 Kaufman ............................. 364/200
`4,027,108 5/1977 Moorehead .
`4,070,704 1/1978 Calle et al. .......................... 364/200
`4,075,693 2/1978 Fox ...................................... 364/200
`4, 155, 117 5/ 1979 Mitchell, Jr ......................... 364/200
`4,177,511 .12/1979 Taddei ................................ 364/200
`4,191,996 3/1980 Chesley ............................... 364/200
`4,236.207 11/1980 Rado ................................... 364/200
`4,253,087 2/1981 Saal ................................. 340/147 R
`4,253,144 2/1981 Bellamy .............................. 364/200
`4,254,463 3/1981 Busby .................................. 364/200
`4,268,901 5/1981 Subrizi ................................ 364/200
`4,293,924 10/1981 Struger ................................ 364/900
`4,303,993 12/1981 Panepinto ........................... 365/230
`4,314,354 2/1982 Felder ................................. 364/900
`4,335,426 6/1982 Maxwell .............................. 364/200
`4,356,475 10/1982 Neumann ............................ 340/521
`4,360,870 11/1982 McVey ................................ 364/200
`4,363,094 12/1982 Kaul .................................... 364/200
`4,373,181 2/1983 Chisholm et al. ................... 364/200
`4,400,775 8/1983 Nozaki ................................ 364/200
`4,432,049 2/1984 Shaw et al. ......................... 364/200
`4,437,157 3/1984 Witalka ............................... 364/200
`4,442,504 4/1984 Dummermuth ..................... 364/900
`4,454,596 6/1984 Wunsch ............................... 364/900
`4,458,357 7/1984 Weymouth ............................. 377/2
`4,491,913 1/1985 Calvignac ........................... 364/200
`4,514,728 4/1985 Ahuja ............................... 340/825.5
`4,521,847 6/1985 Ziehm et al. ....................... 371/7 X
`4.556,953 12/1985 Caprio et al. ....................... 364/900
`4,562,535 12/1985 Vincent et al. ..................... 364/200
`4,563,736 1/1986 Boudreau ............................ 364/200
`4,571,676 2/1986 Mantellina .......................... 364/200
`4,578,773 3/1986 Desai ................................... 364/900
`4,589,063 5/1986 Shah et al. .......................... 364/200
`4,604,690 8/1986 Crabtree et al. .................... 364/200
`4,622,633 11/1986 Ceccon et al. ...................... 364/200
`4,626,634 12/1986 Brahm ................................... 379/28
`4,633,392 12/1986 Vincent ............................... 364/200
`4,654.857 3/1987 Samson ................................. 371/68
`4,660, 14 l 4/ 1987 Ceccon ................................ 364/200
`4,670,855 6/1987 Caprio ................................. 364/900
`4,701,878 I0/1987 Gtinkel et al. ...................... 364/900
`4,713,834 12/1987 Brahm ................................... 379/28
`4,718,038 1/1988 Yoshida ............................... 364/900
`4,750,136 6/1988 Arpin et al. .................... 364/200 X
`4,760,553 7/1988 Buckley et al. ..................... 364/900
`4,787,025 11/1988 Cheselka ............................. 364/200
`4,787,028 11/1988 Finfrock et al. ................ 364/900 X
`4,787,030 11/1988 Harter ................................. 364/200
`4,870,704 9/1989 Matelan ............................... 364/200
`
`FOREIGN PATENT DOCUMENTS
`54-24314 3/1979 Japan .
`54-73531 6/1979 Japan .
`
`55-56235 4/1980 Japan .
`56-46384 10/1982 Japan .
`2101370 1/1983 United Kingdom .
`2137382 10/1984 United Kingdom .
`2166893 5/1986 United Kingdom .
`2175716 12/1986 United Kingdom .
`
`OTHER PUBLICATIONS
`
`IBM TDB vol. 20, No. 8, Jan. 1978, Initial Micropro(cid:173)
`gram Load by Blocks Via Cycle Steal.
`IBM TDB vol. 22, No. 2, Jul., 1979, Even/Odd Ad(cid:173)
`dresses to Allow Device Adapter Sharing by More
`Than One Processor.
`IBM TDB voi. 22, No. 5, Oct. 1979, Satellite Station
`Address Assignment Method.
`IBM TDB vol. 22, No. 10, Mar., 1980, Automatic Mod(cid:173)
`ule Detection.
`IBM TDB vol. 23, No. 8, Jan., 1981, Dynamic Device
`Address Assignment Mechanism.
`Electronic Design, Sep. 3, 1981, pp. 141-156, Several
`Articles, "Functional Architecture Threatens Centra:
`CPUs'', etc.
`Paper in Euromicro, Input/Output Control 6f IBM
`System/370 Model 125 through Dedicated Input/Out
`put Processors, by Assmuth et al., pp. 24-40.
`Technical Disclosure Bulletin (IBM) vol. 27, No. lI
`"Automatic Domain Configuration Mechanism for 1
`Multi-Device 1/0 Controller".
`Wescon Technical Paper Oct. 30-Nov. 2, 1984, "/l
`Standard Protocol for Host Computer-Peripheral In
`terface Allows Upgrading to the Latest Mass Storagi
`Devices".
`Technical Disclosure Bulletin (IBM) vol. 27, No. 2, Jul
`1984 "Input/Output Channel Address Assignrnen
`Mechanism".
`JP Abstract vol. 10, No. 256 (P-493) (23312) Sep. 2
`1986.
`JP Abstract vol. 9, No. 239 (P-391) (1962) Sep. 2~
`1985.
`JP Abstract vol. 9, vol. 9, No. 190 (P-378) (1913) Au.!1
`7, 1985.
`EDN Magazine vol. 26 (1981) Feb., No. 3, Boston, MA
`New Electronics 19(1986) Jul., No. 14, London, Grea
`Britain.
`vol. 22, No. 3, Aug. 1979, IBM Technical Disclosur,
`Bulletin, Programmable Identification for 1/0 Device
`J.M. McVey.
`vol. 16, No. 1 Jun. 1973, IBM Technical Disclosur
`Bulletin, Program Controlled 1/0 Address Assignmenl
`L. J. Rosenberg.
`
`OLYMPUS et al. EX. 1016 - 2/16
`
`

`

`U.S. Patent
`
`Aug. 6, 1991
`
`Sheet I of 7
`
`5,038,320
`
`FIG. I
`
`8
`
`17
`
`'D
`'O 14
`
`CPU
`
`ECO
`
`--+
`ECI
`
`---+
`EC7
`
`t
`
`15
`
`12
`
`5-0
`...
`5-1
`...
`
`5-7
`
`• • • (I
`I AD I PR I s I 0
`
`. . . . , .
`
`22
`
`20
`
`SLOT 2-1
`
`SLOT 2-7
`
`-----···
`
`18
`
`9
`10
`II
`
`.
`" •
`•
`
`OLYMPUS et al. EX. 1016 - 3/16
`
`

`

`U.S. Patent
`
`Aug. 6, 1991
`
`Sheet 2 of 7
`
`5,038,320
`
`FIG. 2
`
`PLANAR BOARD I
`
`(us 11 ...--__.__s_-1 _ _ _ _
`
`OPTION CARDS 5-0 TO
`
`CONTROL
`
`17a
`ADDRESS
`
`17b
`DATA
`
`17c
`
`OLYMPUS et al. EX. 1016 - 4/16
`
`

`

`... w
`00
`Q w
`...
`
`(J1
`
`0
`t-..)
`
`~
`
`...:a
`0 ....
`00. er g ....
`
`""" ~
`°' ,.
`> = ~
`
`~
`
`"""""
`f:Q
`~
`f7J. •
`~ •
`
`('t> = """""
`
`FIG. 3
`
`\:21
`
`REG.
`METER._
`
`TO tfc
`CARD ID
`
`DRIVERS
`
`ID
`
`20
`
`54
`
`•
`FROM 17c
`I
`4s · I
`.
`I
`100 IOI
`51
`I
`I
`I
`I~
`TO 17c -
`I ~
`
`L _______ _J
`--
`I
`I
`I
`I
`
`49
`
`ANO
`4S
`
`IOW
`A2
`EC7
`
`
`
`11
`
`102,103
`DECODE
`so
`
`102,103
`DECODE
`
`A I
`AO
`
`46
`
`AND
`
`m
`A2
`
`L _____________ J
`I
`I
`I
`I
`I
`I
`I
`I
`I
`
`'-----'
`
`DECOlI
`
`~
`SLOT
`
`~
`AND
`
`-
`
`~ I 11
`
`42 '""P
`
`ru ANO_
`c:
`--
`FROM 17c I I 1--.....1 I
`
`- 1
`
`~R--35--L40--41-, ,-,;--44---153
`
`_[_22
`
`( 14
`
`I
`I
`I
`I
`111=~, EC7 I
`: ~
`EC~
`lr2·7 I
`
`;LJ "'-61
`
`OR
`••••
`
`TO FFFF
`BUS 17c
`41 FORCE
`
`~
`
`IOR
`~ DECOOE RANGE 0100-0IO
`)lb !ADDRESS
`
`1/0 AOOR
`
`~ "
`/0 ADDR 0096
`
`OLYMPUS et al. EX. 1016 - 5/16
`
`

`

`U.S. Patent
`
`Aug. 6, 1991
`
`Sheet 4 of 7
`
`5,038,320
`
`FIG. 4
`
`i.-r--- CARO OUTPUTS DISABLE0----~~1 --
`
`ENABLE CARO
`
`IOR
`
`IOW
`
`DATA BUS Ile ___ __,I
`
`rCARDj r SWITCH
`n ____ ____.J,_ - - - -
`
`ID
`
`SETTINGS
`
`,
`
`OLYMPUS et al. EX. 1016 - 6/16
`
`

`

`0
`~
`
`... w
`QO
`0 w
`...
`en
`
`Ut
`
`...a
`Q ....
`n> ....
`00 =(cid:173) n>
`
`""'
`""' :g
`
`,.CJ\
`
`> = qg
`
`('D = '"""'
`"'C = '"""'
`00 •
`~ •
`
`__ _ _J
`I
`I
`,~-,
`
`FIG. 5
`
`58
`l-~-
`
`I
`
`56
`
`57
`
`REGISTER
`
`CARO SELECTED'
`
`FEEDBACK
`
`I
`... 1
`
`ENABLE
`
`SB.ECTED
`
`DECODE I
`lffilORITY
`
`55
`
`Ila
`
`PRIORITY
`
`CARO SELECTED
`
`DECODE I
`AODR
`
`23
`
`ENABLE
`STATUS•SLEEP/ENABLE
`
`DEFAULT /ALTERNATE f
`5-7
`
`1
`
`PR
`I AD 1
`PARM REG
`
`21
`
`OLYMPUS et al. EX. 1016 - 7/16
`
`

`

`U.S. Patent
`
`Aug. 6, 1991
`
`Sheet 6 of 7
`
`5,038,320
`
`FIG. 6
`
`INITIALIZATION SETUP
`·RESET CHANNEL ANO
`DISABLE ALL SLOTS
`
`It
`
`SCAN 1/0 ADDRESS SPACE
`LOOKING FOR A RESPONSE
`INDICATES A NON-COMPATIBLE
`FEATURE CARO)
`
`'
`RESPONSE.RECEIVED-SYSTEM
`USER TO PROVIDE (KEY- IN)
`NEEDED INFO BY
`SLOT POSITION
`
`••
`NO
`RESPONSE
`
`It
`
`RESET CHANNEL
`
`,,
`ENABLE SLOTS IN SEQUENCE
`
`''
`INTERROGATE ALL
`SOCKETS/CARDS FOR CARD
`ID'S IN SEQUENCE
`
`,,
`' CONRGURATION PRCX;P.AM QECKS
`A P~M •m.t FOR EACH
`ID
`{NAME• ID VAWE)WHICH
`CREATES PARAMETERS FOR EACH
`llSfETIVE CARO I N A TAB LE
`
`I~
`
`,,
`
`USER SUPPL! ES PARAMETER
`INFO IF A PROGRAM •FILE•
`IS NOT FOUND
`
`,,
`USER RESOLVES C KEYS- IN )
`PARAMETER CONFUCTS,e.g.
`SELECTS AN ALTERNATE 1/0
`A~~ SPACE FOR A SECOND ti
`TWO SIMILAR DEVICES
`
`••
`STORE THE CONFIGURATION
`TABLE ON DISKETTE
`
`.,
`TRANSFER THE PARAMETER
`INFO FROM TABLE
`TO SLOT POSITIONS
`SUCH AS 30,31,32 •••
`
`•
`TRANSFER PARAMETERS
`FROM SLOT POSITIONS TO
`CARD REGISTERS 21
`
`. ,
`
`TERMINATE SETUP
`PROCEDURE
`
`OLYMPUS et al. EX. 1016 - 8/16
`
`

`

`U.S. Patent
`
`Aug. 6, 1991
`
`Sheet 7 of 7
`
`5,038,320
`
`FIG. 7
`
`POST(POWER ON SELF TEST) SETUP
`
`RESET CHANNEL
`
`'
`
`I
`
`FETCH CARD I D'S
`IN SEQUENCE
`
`••
`
`COMPARE EACH ID VALUE WITH
`ID VALUE IN RESPECTIVE
`SLOT rosmoN
`
`-
`
`~
`ID MISMATCH :
`INVOKE INITIALIZATION
`SETUP PROGRAN
`
`-.
`
`IF ALL ID'S MATCH ,TRANSFER
`PARAMETER INFO FROM SlDT
`POSITIONS TO RESPECTIVE
`CARD REGISTERS 21
`
`OLYMPUS et al. EX. 1016 - 9/16
`
`

`

`1
`
`5,038,320
`
`2
`FIG. 4 shows timings for certain of the logic of FIG.
`3· ' FIG. 5 shows logic utilized by test routines to check
`the proper selection of an 1/0 card; and
`FIGS. 6 and 7 are flowcharts which illustrate briefly
`the setup routines used in the present system.
`
`s
`
`COMPUTER SYSTEM WITH AUTOMATIC
`INITIALIZATION OF PLUGGABLE OPTION
`CARDS
`
`This is a continuation of co-pending application Ser.
`No. 07/021,391 filed on 03/13/87, now abandoned.
`
`BACKGROUND OF THE INVENTION
`Users of smaller computer systems typically do not
`hltve sophisticated programming skills, and user-trans(cid:173)
`parent programmable parameter switches have been
`suggested to simplify configuration of the systems to the
`user's needs. However, the routines that are required to
`so configure such systems are complex, error prone, and
`time consuming. It is an objective of the present im(cid:173)
`provement to substantially reduce the time delay expe(cid:173)
`rienced by a user before he can do productive work on
`the system upon re-powering or resetting of the system
`after a power-down, so long as no cards are changed in, 20
`added to, or removed from the slots.
`
`SUMMARY OF THE INVENTION
`In the improved system, each card type is provided a
`unique ID, which value is hardwired on each card. A 25
`register is also provided on the card to store parameter
`data such as an address factor (to programmably change
`the I/O address space of the card where required),
`priority, status, and other system information providing
`for the efficient transfer of data between the system 30
`processor and the card, and between cards.
`When two or more of the same card type are used in
`the system, parameter data may be used to permit use of
`the cards at different priority levels or to render redun(cid:173)
`dant cards inactive.
`One portion of main memory is provided with battery
`backup to power that portion when system power fails
`or is turned off. Positions in this nonvolatile portion of
`memory are provided (one for each I/O slot) to store
`the ID values of the cards inserted in the respective 40
`slots together with the respective card parameter data.
`When the system is first configured and initialized, a
`complex routine is executed to create and/or fetch all of
`the parameter data required for the cards attached to
`the system, to resolve system resource conflicts and to 45
`store the data into the appropriate card registers and the
`memory slot positions.
`However, if after a power-down, no change is made
`in the cards attached to the slots or in the slot positions
`of the cards, a simplified setup routine determines that SO
`no change has been made by comparing each card ID
`with the ID value stored in the respective slot position.
`Then the routine transfers the parameter data from the
`memory slot positions to the respective card registers;
`and the system is ready for normal operation.
`After the system is configured and initialized, a feed(cid:173)
`back line is provided to signal the use of the select
`mechanism during normal operation. Routines are in(cid:173)
`voked to check the response of each card to given select
`resources to detect duplicate use of a select resource. 60
`These and other features of the present improvement
`will be apparent from the following detailed description
`and accompanying drawings, in which:
`FIG. 1 is a fragmentary block diagram of the im(cid:173)
`proved system;
`FIG. 2 illustrates the bus structure;
`FIG. 3 show certain of the logic utilized by the setup
`routines;
`
`DETAILED DESCRIPTION
`FIG. 1 illustrates a preferred embodiment of the pres-
`10 ent improvement in the form of an integrated circuit
`desktop type computer system featuring user-transpar(cid:173)
`ent establishment of addressing and other variable sys(cid:173)
`tem resource parameters for attached peripheral op(cid:173)
`tions. Thus the user is not burdened with having to set
`IS dip switches, follow complex setup procedures, etc.
`System resource conflicts are reduced or eliminated by
`reassigning of parameters. Other parameters include
`priority levels and a state bit which allows for coexis-
`tence of two identical option attachments.
`System board 1 contains plural sockets or slots 2-0 to
`2-7 into which 1/0 option cards 5-0 to 5-7 may be inter(cid:173)
`changeably plugged. These cards control various types
`of peripheral devices (disk drives, printers, etc.) and
`add-on memory which are either integrally contained
`on respective cards or attached thereto via external
`connectors, not shown. Board 1 also contains elements
`of the central processing system, including a central
`processor unit (CPU) 8, random access memory (RAM)
`main memory modules 9, 10, 11, direct memory access
`(OMA) controls 12, timing controls 13, slot address
`decoder 14, whose function is described below, other
`logical elements not relevant to the present discussion
`indicated collectively at 15, power supply 16, and bus
`17 which links the central processing elements with
`3S each other and with attached peripherals. Darkened
`portions of the bus represent plural address lines 17b,
`data lines 17c, and control lines 17a (FIG. 2).
`A feature hereof is that slots 2-0 to 2-7 can be ad(cid:173)
`dressed by "slot address" signals on the address lines of
`bus 17 during setup routines, and cards residing in the
`slots can be separately addressed by "1/0 address"
`signals on the address lines during normal program
`execution; where the slot addresses and 1/0 addresses
`are distinctly different values associated respectively
`with physical locations of the sockets and with the types
`of devices currently attached. Many different types of
`devices are each potentially attachable to any one of the
`few sockets of the system.
`One of the memory modules, module 10 in the illus(cid:173)
`tration, is nonvolatile, and stores information relative to
`each of the slots 2-0 to 2-7 and its associated card when
`the system is powered down. This module for example,
`may consist of an array of capacitive storage circuits,
`i.e., known complimentary metal-oxide silicon (CMOS)
`SS type semiconductor circuits, configured to operate
`under system power while the system is powered up
`and under battery power 18 in the absence of system.
`power. Within this module, a separately addressable
`space is allocated to each slot, for storing certain infor(cid:173)
`mation relative to the slot. As shown, this information
`includes an identity value ID, an addressing factor AD,
`a priority value PR, a state bit S, and other information
`0.
`A feature to be described is the use of this information
`65 in the nonvolatile memory to speed up initialization
`(FIG. 7) of the system when the slot configuration has
`not changed since the last power-down, and thereby
`reduce the time the user has to wait to begin useful
`
`OLYMPUS et al. EX. 1016 - 10/16
`
`

`

`5,038,320
`
`3
`the system power-on
`applications after operating
`switch, not shown, or after system or channel reset.
`This difference in complexity and number of steps re(cid:173)
`quired is illustrated by FIGS. 6 (initialization) and 7
`(POST).
`Details of card 5-7 are indicated as representative of
`the relevant logical organizations of all cards to the
`extent required for describing the present improvement.
`Driver circuits 20 are pre-wired at manufacture, and
`under conditions described below transmit a set of iden- 10
`tity signals ID which uniquely identify that card type
`and its respective peripheral device.
`Register 21 stores parameter information for control(cid:173)
`ling communications between the card and the system,
`including the address factor AD, the priority value PR, 15
`the state bit S, and other information 0 described with
`respect to module 10. This information is set by the
`central system during power-up initialization (FIG. 6).
`A feature of the system is that, if slot conditions have
`not changed since the last power-down of the system, 20
`the information is simply transferred to register 21 from
`the nonvolatile memory 10 in a relatively fast operation
`(FIG. 7), whereas if slot conditions have changed the
`system is required to perform a lengthy program pro(cid:173)
`cess (FIG. 6) to retrieve and/or develop some or all of 25
`the information and then transfer it to both memory 10
`and the card register 21.
`Control logic 22 and decode logic 23 control re(cid:173)
`sponse of the card 5-7 to I/O addresses appearing on
`bus 17. When power is applied to the system, the cards 30
`are addressable initially only through their sockets, and
`a portion of the address bus. But after the power-up
`process, the value AD in register 21 controls decoder 23
`to detect a default or alternate I/O address associated
`uniquely to the card type and unrelated to the socket 35
`location. Upon such detection, the priority value PR
`and state bit S in conjunction with control logic 22
`determine when data may be exchanged between the
`card and the bus 17. One manner in which an AD value,
`the decoder 23 and logic 22 detect an I/0 address is 40
`shown and described in Interfacing to the IBM Personal
`Computer by L. Eggebrecht published 1983 at pages
`130, 131.
`In operation, during its power-up sequence the cen(cid:173)
`tral system individually addresses the option sockets, by 45
`sending respective "slot address" signals on the bus
`which are uniquely detected by decoder 14 and result in
`separate activation of setup (or enable card) lines ECO(cid:173)
`EC7 extending to respective sockets 2-0 to 2-7 and
`through the sockets to attached cards 5-0 to 5-7. Upon 50
`activation of one such line, if the respective socket is
`vacant the hexadecimal value of FFFF is returned to
`the system which terminates further operation relative
`to that socket. However, if the socket contains a card,
`the activated line in conjunction with additional address SS
`signals on the bus 17 condition logic 22 on the respec(cid:173)
`tive card to cause drivers 20 to transmit the ID signals
`mentioned above which identify the respective card and
`device type. The system CPU compares the returned
`ID signals with the ID value stored in the location in 60
`memory 10 allocated to the respective slot, and sets an
`indication denoting whether the compared values are
`the same or different. This indication serves effectively
`as a branch condition for subsequent program processes
`which determine the action to be taken relative to the 65
`respective slot.
`If the indication just mentioned represents a matching
`comparison, and conditions of all other slots have not
`
`4
`changed, a subsequent program process will simply
`transfer the value of AD, PR, S, and 0, which are cur(cid:173)
`rently stored in the associated location of memory 10 to
`the respective card for storage in its register 21. If the
`S indication represents a non-matching comparison, and if
`the transmitted ID indicates that the respective slot
`contains a card, the processor 8 uses the transmitted ID
`and information gleaned from the other slots to retrieve
`and/or develop new AD, PR, S, and 0 values for the
`respective card using files describing card resource
`requirements and alternatives. After all card values are
`established, the values for each card are transferred in
`sequence first to the respective slot location in memory
`10 and subsequently to the respective card register 21.
`Mismatching comparisons occur when the state of
`the interrogated. socket has been altered. The ID value
`stored in memory 10 relative to a socket which was
`vacant at last power-down is FFFF, and the ID value
`stored relative to a previously occupied socket is that of
`the card last occupying that slot. Thus, if a card is in(cid:173)
`stalled into a previously vacant slot or substituted for a
`card having a different ID, a mismatching comparison
`will occur causing the system to retrieve and/or de-
`velop new AD, PR, S, and 0 values for the responding
`card.
`As noted above, the system cannot deal with mis(cid:173)
`matching indications until the states of all sockets have
`been ascertained. This is because the priority level, and
`in certain instances the address and state values, as(cid:173)
`signed to any card are relative to the cards in other
`slots. The address and state values are relative when
`two cards with the same identity ID are currently in(cid:173)
`stalled, either to provide redundant backup for device
`failure or to provide additional device capacity. In the
`latter instances, the state value can be used to place a
`backup device in an inactive state during normal system
`operation or the priority values can be used to allow
`both devices to operate fully but at different priority
`levels.
`In the preferred embodiment, system information is
`stored in the eight slot positions (only three-30, 31,
`32-are shown) of module 10 to accommodate up to
`eight feature cards 5-0 to 5-7. Each slot position is four
`bytes wide, twenty-eight bytes for seven feature cards.
`The card ID resides in the first two bytes and the switch
`(parameter) settings in. the last two bytes. The corre(cid:173)
`sponding ID and parameter data on each card resides in
`drivers 20 and register 21, respectively.
`FIG. 3 shows schematically certain of the logic on
`the board 1 and feature card 5-7 used during setup rou(cid:173)
`tines to read out a card ID and store parameters in the
`register 21. With respect to FIG. 3, the hexadecimal
`1/0 address values assigned to certain of the compo(cid:173)
`nents on each of the feature cards is as follows:
`096 - socket select value (one byte)
`100, 101 - ID drivers 20 (two bytes)
`102, 103 - parameter register 21 (two bytes)
`These are "dummy" addresses since they are used by
`the processor 8 to access I/O cards and components via
`the slots during setup operations. The address 096 se-
`lects the logic (gates 38, 39) of slot address decoder 14
`for storing the card select value into slot register 40 and
`also for reading out the value, i.e., during diagnosis.
`Address lines AO and Al of FIG. 3 form the lower
`address values 00, 01, 02, and 03 for selecting the com-
`ponents 20 and 21, while a logical 1 signal on address
`line Al provides the most significant digit value of l.
`
`OLYMPUS et al. EX. 1016 - 11/16
`
`

`

`5,038,320
`
`5
`AO, Al, and Al are coupled to appropriate bit lines of
`address bus 17b, FIG. 2.
`FIG. 3 shows in more detail certain of the logic of the
`slot address decoder 14 and of the control logic 22 of
`card 7 which are used in the setup routines of FIGS. 6 5
`and 7. It will be assumed for simplicity of discussion,
`that addressing of two bytes at a time, i.e., one cycle, is
`available and that two byte data transfers occurs on
`busses. Hence, decoding address 101 gates both bytes
`for addresses 101 and 100.
`.. Slot register 40 is program controlled to store a three
`bit value (000-111) corresponding to a slot (2-0 to 2-7) to
`be accessed. A decode circuit 41 changes this three bit
`binary value to a one in eight line output but only when
`it is gated by a signal on input line 42. Each output line, 15
`such as EC7, is connected via the respective socket to
`the card held in the socket. When a decode circuit 43
`decodes an address in the range 0100 - 0103 during a
`setup routine, it produces an output on line 42 to gate
`the value in 40 to cause an output (see FIG. 4) on a card 20
`setup line such EC7, one of the control lines 17a of bus
`17.
`This output on EC7 is applied to AND gates 44 and
`45. The address line A2 is coupled to gates 44 and 45.
`An I/O read line IOR and an I/O write line IOW (de- 25
`coded from control lines 17a) are coupled respectively
`to gates 44 and 45. An output 46 from gate 44 is coupled
`to a pair of decoder circuits 47 and 48. An output 49
`from gate 45 is coupled to a decode circuit 50. An out(cid:173)
`put 51 from decode 48 is coupled to the ID driver cir- 30
`cuit 20 and the output 52 from decode 50 is coupled to
`the parameter register 21.
`During the post setup routine of FIG. 7, when an ID
`is being fetched from card 7, the processor 8 forces A2
`negative (logical 1) and Al, AO to logic 01 (address 35
`101). EC7 is negative (FIG. 4). When IOR goes nega(cid:173)
`tive, the gate 44 produces an output at 46 to produce an
`output at 51 which gates the card ID value in 20 to data
`bus 17c. Processor 8 compares this ID with the ID in
`the respective slot position in memory module 10. If the 40
`IDs compare, processor 8 transfers the parameter val(cid:173)
`ues in the slot position 32 (FIG. 1) to data bus 17c and
`forces A2, Al, AO to logic 111 (address 103). Shortly
`thereafter, processor 8 issues an IOW to cause gate 45 to
`produce an output on 49. This gates an output from 50 45
`.to register 21 via line 52 to gate the parameter values on
`bus 17c into register 21. The output 53 of decode 47 is
`used during diagnostic routines to gate the output of
`parameter register 21 to bus 17c via gate 54.
`As discussed above with respect to a setup routine, an 50
`ID of hexadecimal value FFFF is returned during an
`ID fetch operation when the addressed socket is empty.
`One method of achieving this result is shown in FIG. 3.
`A pre-wired circuit 60 is gated to force bus 17 to all
`"I's" during the IOR cycle by a negative going signal 55
`on any one of the enable card lines ECl to EC7 via OR
`circuit 61 and the negative going signal on IOR. If a
`card is in the socket which has been addressed, its ID is
`gated to bus 17c at the same time and all logical O's in
`the ID override the logical l's from 60 to correctly 60
`reproduce the ID on bus 17c.
`The logic of FIG. 3 is used in a similar manner during
`the initialization setup and the POST setup routines of
`FIGS. 6 and 7.
`When two identical cards (same ID) are connected to 65
`two of the I/O slots and it is desired to render both
`active, the first card is assigned the standard 1/0 default
`address at one priority level and the other card is as-
`
`6
`signed an alternate 1/0 address at a different priority
`level.
`·
`The logic of FIG. 5 is then utilized during a diagnos(cid:173)
`tic routine to ascertain whether each card properly
`responds to its respective 1/0 address. The address
`decode logic 23 decodes the address on bus 17b if it
`corresponds to the alternate address when the appropri(cid:173)
`ate alternate address factor AD is stored in parameter
`register 21 and the least significant bit is on (the card is
`10 active). Similarly, a priority decode circuit 55 produces
`an output if the priority value on bus 17a is equal to PR
`in register 21 and the card active bit is on. If outputs are
`produced by logic 23 and 55, an AND gate 56 produces
`a feedback signal on line 57 to set one bit in a register 58
`on the board 1. The CPUS under program control will
`read register 58 .to determine that one and only one card
`properly responded to the I/O alternate address and
`reset register 58. Similar circuits on the other identical
`card will respond to the default 1/0 address and the
`appropriate priority level to set another bit in register 58
`for diagnostic purposes.
`While there have been described what are at present
`considered to be a preferred embodiment of this inven(cid:173)
`tion, it will. be obvious to those skilled in the art that
`various changes and modifications may be made therein
`without departing from the invention, and it is, there-
`fore, intended to cover all such changes and modifica(cid:173)
`tions as fall within the true spirit and scope of the inven-
`tion.
`What is claimed is:
`1. In a data processing system having a system pro(cid:173)
`cessor and a plurality of 1/0 sockets to which periph(cid:173)
`eral control cards of various types are attachable, and in
`which means on at least one card permanently stores an
`identity value corresponding to the respective card
`type, said system comprising:
`nonvolatile memory means storing, in memory loca-
`tions thereof assigned to respecti