United States Patent [19}
`
`Heath et a1.
`
`[11]
`
`[451
`
`Patent Number:
`
`5,038,320
`
`Date of Patent:
`
`Aug. 6, 1991
`
`3508648
`50-12093:
`
`9/1986 Fed. Rep. ofGermany.
`9/1976 Japan.
`
`(List continued on next page.)
`
`OTHER PUBLICATIONS
`
`IBM TDB vol. 20, No. 7, Dec. 1977, Input/Output
`Device Address Recognition Mechanism.
`(List continued on next page.)
`
`Primary Examiner—Gareth D. Shaw
`Assistant Examiner—Paul Kulik
`Attorney. Agent. or Firm—Winfield J. Brown, Jr.;
`Robert Lieber
`
`[57]
`
`ABSTRACT
`
`[54]
`
`[75]
`
`[73]
`
`121]
`
`[221
`
`[63]
`
`[511
`[521
`
`[58]
`
`[56]
`
`COMPUTER SYSTEM WITH AUTOMATIC
`INITIALIZATION OF PLUGGABLE OPTION
`CARDS
`
`Inventors: Chester A. Heath; John K. Langgood,
`'
`both of Boca Raton, Fla; Ronald E.
`Valli. Pittsburgh, Pa.
`International Business Machines
`Corp., Armonk, NY.
`
`Assignee:
`
`Appl. No.:
`Filed:
`
`296,387
`
`Jan. 6, 1989
`
`Related US. Application Data
`Continuation of Ser. No. 21,391. Mar. 13, 1987, aban-
`cloned.
`
`Int. Cl.5 ....................... .. G06F 13/00; G06F 7/04
`US. Cl. ............................... .. 364/900: 364/948.5;
`364/944.61; 364/9752; 364/976.4; 364/945;
`364/9295; 364/9292; 371/11.1
`364/200 MS File. 900 MS File;
`Field of Search
`340/825.07, 825.06, 825.52, 825.06; 371/11.1,
`11.2, 11.3, 66, 7
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`3,480,914 11/1969 Schlaeppi .......................... .. 364/200
`3,510,843
`5/1970 Bennett
`364/200
`3.573,741
`4/1971 Gavril
`364/200
`3,818,447
`6/1974 Craft .... ..
`. 340/1725
`4,003,033
`1/1977 O‘Keefe
`364/200
`4,015,244
`3/1977 Simpson ............................ .. 364/200
`(List continued on next page.)
`
`WSTiPOVER 0| SELF 113115me
`
`18 Claims, 7 Drawing Sheets
`
`CARD REBlmSZi
`
`A data processing system includes a planar board hav-
`ing a central processing .unit (CPU),
`21 main memory
`unit, and input/output (I/O) sockets or slots, each
`adapted to receive a selected one of a plurality of differ-
`ent and/or similar option cards. each card contains (or
`is connected to) and controls a respective peripheral
`device; and each card is pre-wired with an ID value
`corresponding to its card type. Software programmable
`option registers on each card store parameters such as
`designated default (or alternate) address information,
`priority levels, and other system resource parameters. A
`setup routine, during initial power—on, retrieves and
`stores the appropriate parameters in the I/O cards and
`also in slot positions in main memory, one position being
`assigned to each slot on the board. Each slot position is
`adapted to hold the parameters associated with the card
`inserted in its respective slot and the card ID value.
`That portion of main memory containing the slot posi-
`tions is adapted to maintain the parameter and ID infor-
`mation by means of battery power when system power
`fails or is disconnected, Le, a nonvolatile memory por-
`tion. Subsequent power—on routines are simplified by
`merely transferring parameters from the table to the
`card option registers if the status of all the slots has not
`changed since the last power-down, system reset, or
`channel reset.
`
`FOREIGN PATENT DOCUMENTS
`0041406
`9/1981
`0087368
`8/1983
`0121331
`3/1984
`0121381 10/1984
`0136178 4/1985
`0179981
`6/1985
`0171073
`2/1986
`01820-44
`5/1986
`0200198 11/1986
`
`European Pat. Oi‘l‘.
`European Pat. Off.
`European Pat. Off.
`European Pat. OiT.
`European Pat. Off.
`European Pat. Off.
`European Pat. Off.
`European Pat. Off.
`European Pat. Off.
`
`.
`.
`.
`.
`.
`.
`.
`.
`.
`
`RESET CHMNEL
`
`VETCK CARD ID'S
`lit
`SEQUENCE
`
`jCOllPlRE EICN ID VALUE Willi
`‘
`[NILth I11 RESBTIVE
`SLOT P13517101!
`
`ID 11151018“:
`IIVDIE illTlAllUllDl
`SU'JP PROGW
`
`' IF A11 ID'S IATEHJRMGER
`PARAKUER Ilia MI 5181
`P05010115 1‘0 ESPECTWE
`
`OLYMPUS EX. 1019 - 1/16
`
`

`

`Page 2
`________________________________________-—————————
`
`5,038,320
`
`U.S. PATENT DOCUMENTS
`............. .. 364/200
`Kaufman ............ ..
`5/1977
`Moorehead .
`5/1977
`Calle et a1.
`1/1978
`Fox
`2/1978
`5/1979
`Mitchell, Jr.
`Taddei ..... ..
`.12/1979
`3/1980
`Chesley ..
`Rado .... ..
`11/1980
`Saal ...... ..
`2/1981
`2/1981
`Bellamy .
`3/1981
`Busby
`Subrizi
`5/1981
`10/1981
`Struger .... ..
`12/1981
`Panepinto .........
`Felder ...............
`2/1982
`Maxwell
`6/1982
`Neumann ..
`10/1982
`11/1982
`McVey .... ..
`Kaul ............ ..
`12/1982
`Chisholm et a1.
`2/1983
`Nozaki
`8/1983
`Shaw et al.
`2/1984
`Witalka
`3/1984
`Dummerrnuth ..
`4/1984
`Wunsch
`6/1984
`7/1984
`Weymouth
`1/1985
`Calvignac
`4/1985
`Ahuja
`Ziehm et a1.
`6/1985
`12/1985
`Caprio et a1.
`Vincent et a1.
`12/1985
`Boudreau
`1/1986
`Mantellina
`2/1986
`Desai ............
`3/1986
`Shah et al.
`5/1986
`Crabtree et a].
`8/1986
`11/1986
`Ceccon et a1.
`Brahm'
`12/1986
`Vincent
`12/1986
`Samson
`3/1987
`Ceccon
`4/1987
`6/1987
`Caprio
`Giinkel et a1.
`10/1987
`Brahm
`12/1987
`Yoshida
`1/1988
`6/1988
`Arpin et al.
`7/1988
`.
`Buckley et a1.
`Cheselka ....... ..
`11/1988
`Finfrock et a1.
`11/1988
`Harter
`11/1988
`Matelan
`9/1989
`
`55-56235
`56-46384
`2101370
`2137382
`2166893
`2175716
`
`4/1980
`10/1982
`1/1983
`10/1984
`5/1986
`12/1986
`
`Japan .
`Japan .
`United Kingdom .
`United Kingdom .
`United Kingdom .
`United Kingdom .
`
`OTHER PUBLICATIONS
`
`364/200
`364/200
`364/200
`364/200
`.. 364/200
`364/200
`340/147 R
`364/200
`364/200
`364/200
`364/900
`365/230
`364/900
`364/200
`340/521
`364/200
`364/200
`364/200
`364/200
`364/200
`364/200
`364/900
`. 364/900
`............. ., 377/2
`364/200
`. 340/8255
`371/7 X
`364/900
`.. 364/200
`364/200
`.. 364/200
`364/900
`.. 364/200
`364/200
`. 364/200
`379/28
`364/200
`371/68
`. 364/200
`364/900
`, 364/900
`............ .. 379/28
`364/900
`. 364/200 X
`364/900
`364/200
`. 364/900 X
`364/200
`364/200
`
`4,025,903
`4,027,108
`4,070,704
`4,075,693
`4,155,1 17
`4,177,51 1
`4,191,996
`4,236,207
`4,25 3,087
`4,253,144
`4,254,463
`4,268,901
`4,293,924
`4,303,993
`4,314,354
`4,335,426
`4,356,475
`4,360,870
`4,363,094
`4,373,181
`4,400,775
`4,432,049
`4,437,157
`4,442,504
`4,454,596
`4,458,357
`4,491,913
`4,514,728
`4.521.847
`4.556953
`4,562,535
`4,563,736
`4,571,676
`4,578,773
`4,589,063
`4,604,690
`4,622,633
`4,626,634
`4,633,392
`4,654,857
`4,660,141
`4,670,855
`4,701,878
`4,713,834
`4,718,038
`4,750,136
`4,760,553
`4,787,025
`4,787,028
`4,787,030
`4,870,704
`
`.
`
`..
`
`.
`
`FOREIGN PATENT DOCUMENTS
`54-24314
`3/1979 Japan.
`54-73531
`6/1979 Japan .
`
`L. J. Rosenberg.
`
`IBM TDB vol. 20, No. 8, Jan. 1978, Initial Micropro-
`gram Load by Blocks Via Cycle Steal.
`IBM TDB vol. 22, No. 2, Jul., 1979, Even/Odd Ad-
`dresses to Allow Device Adapter Sharing by More
`Than One Processor.
`IBM TDB vol. 22, No. 5, Oct. 1979, Satellite Station
`Address Assignment Method.
`.
`IBM TDB vol. 22, No. 10, Mar., 1980, Automatic Mod-
`ule Detection.
`IBM TDB vol. 23, No. 8, Jan., 1981, Dynamic Device
`Address Assignment Mechanism.
`Electronic Design, Sep. 3, 1981, pp. 141-156, Several
`Articles, “Functional Architecture Threatens Central
`CPUs”, etc.
`Paper in Euromicro, Input/Output Control 6f IBM
`System/370 Model 125 through Dedicated Input/Out-
`put Processors, by Assmuth et 31., pp. 24-40.
`11?
`Technical Disclosure Bulletin (IBM) vol. 27, No.
`“Automatic Domain Configuration Mechanism for :
`Multi—Device I/O Controller”.
`Wescon Technical Paper Oct. 30—Nov. 2, 1984, “A
`Standard Protocol for Host Computer—Peripheral In
`terface Allows Upgrading to the Latest Mass Storagt
`Devices“.
`Technical Disclosure Bulletin (IBM) vol. 27, No. 2, Jul
`1984 “Input/Output Channel Address Assignmen
`Mechanism".
`JP Abstract vol. 10, No. 256 (P-493) (23312) Sep. 2
`1986.
`JP Abstract vol. 9, No. 239 (P-391) (1962) Sep. 25
`1985.
`JP Abstract vol. 9, vol. 9, No. 190 (P—378) (1913) Aug
`7, 1985.
`EDN Magazine vol. 26 (1981) Feb, No. 3, Boston, MA
`New Electronics 1909516) JUL, No. 14, London, Great
`Britain.
`vol. 22, No. 3, Aug. 1979, IBM Technical Disclosurl
`Bulletin, Programmable Identification for I/O Device
`J. M. McVey.
`1 Jun. 1973, IBM Technical Disclosurt
`vol. 16, No.
`Bulletin, Program Controlled I/O Address Assignmenl
`
`OLYMPUS EX. 1019 - 2/16
`
`

`

`Aug. 6, 1991
`
`Sheet 1 of 7
`
`US. Patent
`
`5,038,320
`
`OLYMPUS EX. 1019 - 3/16
`
`

`

`US. Patent
`
`Aug. 6, 1991
`
`Sheet 2 of 7
`
`5,038,320
`
`PLANAR BOARD I
`
`OPTION CARDS 5-O TO
`
`5-?
`
`DATA
`
`gflUS I?
`
`CONT ROL
`
`I'Ia
`
`ADDRESS
`
`17b
`
`OLYMPUS EX. 1019 - 4/16
`
`

`

`’
`
`1991
`
`7f03teehS
`
`Aug. 6
`
`952%2
`
`5,038,320
`
`U.S. Patent
`
`OLYMPUS EX. 1019 - 5/16
`
`

`

`US. Patent
`
`Aug. 6, 1991
`
`Sheet 4 of 7
`
`5,038,320
`
`DATA BUS m —‘L__["L_______J———_
`
`'low —‘——1__J——‘—
`CARD
`SWITCH
`I" no "I
`[“semucs
`
`ENABLE CARD
`
`r——-GARD OUTPUTS DISABLED——————’]
`|
`|
`
`IOR‘ ——L__J———————‘
`
`OLYMPUS EX. 1019 - 6/16
`
`

`

`cmHA
`
`19916,
`
`Sheet 5 of 7
`
`5,038,320
`
`_5:8:
`855mm23
`
`US. Patent
`
`-52E
`
`33555?8.25
`
`mEzzmbibibo
`
`815?.
`
`OLYMPUS EX. 1019 - 7/16
`
`

`

`US. Patent
`
`Aug. 6, 1991
`
`Sheet 6 of 7
`
`5,038,320
`
`FIG. 6
`
`mmmzmou SETUP
`
`RESET CHANNEL AND
`DISABLE ALL SLOTS
`
`SCAN |/O ADDRBS SPACE
`LOOKING FOR A RESPONSE
`INDICATES A NON-COMPATIBLE
`FEATURE CARD)
`
`RESPONSE RECE WED-SYSTEM
`USER TO PROVIDE (KEY-IN)
`NEEDED INFO BY
`SLOT POSITION
`
`USER SUPPLIES PARAMETER
`INFO IF A PROGRAM 'FILE'
`IS NOT FOUND
`
`USER RESOLVES (KEYS - IN )
`PARAMETER CONFLICTS,o.g.
`SELECTS AN ALTERNATE IID
`SPACE FOR A SECOND '
`TWO SIMILAR DEVICES
`
`PROCEDURE
`
`' CONFIGURATION PROGRAM GECKS
`A PROGRAM 'FILE' FOR EACH ID
`(NAME- ID VALUE) WHICH
`CREATES PARAMETERS RIR EACH
`RESPECTIVE CARD IN A TABLE
`
`RESET CHANNEL
`
`STORE THE CONFIGURATION
`TABLE ON OISKETTE
`
`ENABLE SLOTS IN SEOUENGE
`
`INTERROGATE ALL
`SOCKETS/CARDS FOR CARD
`ID'S IN SEQUENCE
`
`TRANSFER THE PARAMETER
`INFO FROM TABLE
`TO SLOT POSITIONS
`SUCH AS .SO,3|,32 .. .
`
`TRANSFER PARAMETERS
`FROM SLOT POSITIONS TO
`CARD REGISTERS 2|
`
`TERMINATE SETUP
`
`OLYMPUS EX. 1019 - 8/16
`
`

`

`US. Patent
`
`Aug. 6, 1991
`
`Sheet 7 of 7
`
`5,038,320
`
`POSTIPOWER 0N SELF TEST) SETUP
`
`CARD REGISTERS 2|
`
`IF ALL ID'S HATCHJRAIISFER
`POSITIONS TO RESPECTIVE
`
`RESET CHANNEL
`
`FETCH CARD ID'S
`IN SEQUENCE
`
`COMPARE EACH ID VALUEWITH
`ID VALUE IN RESPETIVE
`
`SLOT POSITION
`
`m "ism";
`mvggufigkfigggm
`
`‘
`
`‘
`
`PARAMETER INFO FROM SUIT
`
`OLYMPUS EX. 1019 - 9/16
`
`

`

`1
`
`5,038,320
`
`2
`FIG. 4 shows timings for certain of the logic of FIG.
`
`3;
`
`5
`
`FIG. 5 shows logic utilized by test routines to check
`the proper Selection of an I/O card; and
`FIGS. 6 and 7 are flowcharts which illustrate briefly
`the setup routines used in the present system.
`DETAILED DESCRIPTION
`
`reduce the time the user has to wait to begin useful
`
`FIG. 1 illustrates a preferred embodiment of the pres-
`ent improvement in the form of an integrated circuit
`desktop type computer system featuring user-transpar-
`ent establishment of addressing and other variable sys-
`tem resource parameters for attached peripheral op~
`tions. Thus the user is not burdened with having to set
`dip switches, follow complex setup procedures, etc.
`System resource conflicts are reduced or eliminated by
`reassigning of parameters. Other parameters include
`priority levels and a state bit which allows for coexis-
`tence of two identical option attachments.
`System board 1 contains plural sockets or slots 2-0 to
`2—7 into which 1/0 option cards 5-0 to 5-7 may be inter-
`changeably plugged. These cards control various types
`of peripheral devices (disk drives, printers, etc.) and
`add-on memory which are either integrally contained
`on respective cards or attached thereto via external
`connectors, not shown. Board 1 also contains elements
`of the central processing system, including a central
`processor unit (CPU) 8, random access memory (RAM)
`main memory modules 9, IO, 11, direct memory access
`(DMA) controls 12,
`timing controls 13, slot address
`decoder 14, whose function is described below, other
`logical elements not relevant to the present discussion
`indicated collectively at 15, power supply 16, and bus
`17 which links the central processing elements with
`each other and with attached peripherals. Darkened
`portions of the bus represent plural address lines 17b.
`data lines 17c, and control lines 170 (FIG. 2).
`A feature hereof is that slots 2-0 to 2-7 can be ad-
`dressed by “slot address" signals on the address lines of
`bus 17 during setup routines, and cards residing in the
`slots can be separately addressed by “I/O address"
`signals on the address lines during normal program
`execution; where the slot addresses and [/0 addresses
`are distinctly different values associated respectively
`with physical locations of the sockets and with the types
`of devices currently attached. Many different types of
`devices are each potentially attachable to any one of the
`few sockets of the system.
`One of the memory modules, module 10 in the illus-
`tration, is nonvolatile, and stores information relative to
`each of the slots 24] to 2-7 and its associated card when
`the system is powered down. This module for example,
`may consist of an array of capacitive storage circuits,
`i.e., known complimentary metal—oxide silicon (CMOS)
`type semiconductor circuits, configured to operate
`under system power while the system is powered up
`and under battery power 18 in the absence of system_
`power. Within this module, a separately addressable
`space is allocated to each slot, for storing certain infor-
`mation relative to the slot. As shown. this information
`includes an identity value ID, an addressing factor AD,
`a priority value PR, a state bit S, and other information
`0.
`
`COMPUTER SYSTEM WITH AUTOMATIC
`INITIALIZATION OF PLUGGABLE OPTION
`CARDS
`
`This is a continuation of co-pending application Ser.
`No. 07/021,391 filed on 03/13/87, now abandoned.
`
`BACKGROUND OF THE INVENTION
`
`Users of smaller computer systems typically do not 10
`have sophisticated programming skills, and user-trans-
`parent programmable parameter switches have been
`suggested to simplify configuration of the systems to the
`user's needs. However, the routines that are required to
`so configure such systems are complex, error prone, and
`time consuming. It is an objective of the present im-
`provement to substantially reduce the time delay expe-
`rienced by a user before he can do productive work on
`the system upon re-powering or resetting of the system
`after a power-down, so long as no cards are changed in,
`' added to, or removed from the slots.
`SUMMARY OF THE INVENTION
`
`In the improved system, each card type is provided a
`unique ID, which value is hardwired on each card. A
`register is also provided on the card to store parameter
`data such as an address factor (to programmably change
`the I/O address space of the card where required),
`priority, status, and other system information providing
`for the efficient transfer of data between the system
`processor and the card, and between cards.
`When two or more of the same card type are used in
`the system, parameter data may be used to permit use of
`the cards at different priority levels or to render redun-
`dant cards inactive.
`
`35
`
`45
`
`One portion of main memory is provided with battery
`backup to power that portion when system power fails
`or is turned off. Positions in this nonvolatile portion of
`memory are provided (one for each I/O slot) to store
`the ID values of the cards inserted in the respective 40
`slots together with the respective card parameter data.
`When the system is first configured and initialized, a
`complex routine is executed to create and/or fetch all of
`the parameter data required for the cards attached to
`the system, to resolve system resource conflicts and to
`store the data into the apprOpriate card registers and the
`memory slot positions.
`However, if after a power-down, no change is made
`in the cards attached to the slots or in the slot positions
`of the cards, a simplified setup routine determines that
`no change has been made by comparing each card ID
`with the ID value stored in the respective slot position.
`Then the routine transfers the parameter data from the
`memory slot positions to the respective card registers;
`and the system is ready for normal operation.
`After the system is configured and initialized, a feed-
`back line is provided to signal the use of the select
`mechanism during normal operation. Routines are in-
`voked to check the response of each card to given select
`resources to detect duplicate use of a select resource.
`These and other features of the present improvement
`will be apparent from the following detailed description
`and accompanying drawings, in which:
`FIG. I is a fragmentary block diagram of the im-
`proved system;
`FIG. 2 illustrates the bus structure;
`FIG. 3 show certain of the logic utilized by the setup
`routines;
`
`A feature to be described is the use of this information
`in the nonvolatile memory to speed up initialization
`(FIG. 7) of the system when the slot configuration has
`not changed since the last power-down, and thereby
`
`OLYMPUS EX. 1019 - 10/16
`
`

`

`3
`
`5,038,320
`
`line A2 provides the most significant digit value of l.
`
`applications after operating the system power-on
`switch, not shown, or after system or channel reset.
`This difference in complexity and number of steps re-
`quired is illustrated by FIGS. 6 (initialization) and 7
`(POST).
`Details of card 5-7 are indicated as representative of
`the relevant logical organizations of all cards to the
`extent required for describing the present improvement.
`Driver circuits 20 are pre-wired at manufacture, and
`under conditions described below transmit a set of iden-
`tity signals ID which uniquely identify that card type
`and its respective peripheral device.
`Register 21 stores parameter information for control-
`ling communications between the card and the system,
`including the address factor AD, the priority value PR,
`the state bit 8, and other information 0 described with
`respect to module 10. This information is set by the
`central system during power-up initialization (FIG. 6).
`A feature of the system is that, if slot conditions have
`not changed since the last power-down of the system,
`the information is simply transferred to register 21 from
`the nonvolatile memory 10 in a relatively fast operation
`(FIG. 7), whereas if slot conditions have changed the
`system is required to perform a lengthy program pro-
`cess (FIG. 6) to retrieve and/or develop some or all of 25
`the information and then transfer it to both memory 10
`and the card register 21.
`Control
`logic 22 and decode logic 23 control re-
`sponse of the card 5-7 to l/O addresses appearing on
`bus 17. When power is applied to the system, the cards
`are addressable initially only through their sockets, and
`a portion of the address bus. But after the power-up
`process, the value AD in register 21 controls decoder 23
`to detect a default or alternate I/O address associated
`uniquely to the card type and unrelated to the socket
`location. Upon such detection, the priority value PR
`and state bit 5 in conjunction with control logic 22
`determine when data may be exchanged between the
`card and the bus 17. One manner in which an AD value,
`the decoder 23 and logic 22 detect an I/O address is
`shown and described in Interfacing to the IBM Personal
`Computer by L. Eggebrecht published 1983 at pages
`130. 131.
`In operation, during its power-up sequence the cen-
`tral system individually addresses the option sockets, by
`sending respective “slot address" signals on the bus
`which are uniquely detected by decoder 14 and result in
`separate activation of setup (or enable card) lines ECO-
`EC7 extending to respective sockets 2-0 to 2-7 and
`through the sockets to attached cards 5-0 to 5-7. Upon
`activation of one such line, if the respective socket is
`vacant the hexadecimal value of FFFF is returned to
`the system which terminates further Operation relative
`to that socket. However, if the socket contains a card,
`the activated line in conjunction with additional address
`signals on the bus 17 condition logic 22 on the respec-
`tive card to cause drivers 20 to transmit the ID signals
`mentioned above which identify the respective card and
`device type. The system CPU compares the returned
`ID signals with the ID value stored in the location in
`memory 10 allocated to the respective slot, and sets an
`indication denoting whether the compared values are
`the same or different. This indication serves effectively
`as a branch condition for subsequent program processes
`which determine the action to be taken relative to the
`respective slot.
`If the indication just mentioned represents a matching
`comparison, and conditions of all other slots have not
`
`4
`changed, a subsequent program process will simply
`transfer the value of AD, PR, 5, and O, which are cur-
`rently stored in the associated location of memory 10 to
`the respective card for storage in its register 21. If the
`indication represents a non-matching comparison, and if
`the transmitted ID indicates that the respective slot
`contains a card, the processor 8 uses the transmitted ID
`and information gleaned from the other slots to retrieve
`and/or develop new AD, PR, 5, and 0 values for the
`reSpective card using files describing card resource
`requirements and alternatives. After all card values are
`established, the values for each card are transferred in
`sequence first to the respective slot location in memory
`10 and subsequently to the respective card register 21.
`Mismatching comparisons occur when the state of
`the interrogated. socket has been altered. The ID value
`stored in memory 10 relative to a socket which was
`vacant at last power-down is FFFF, and the ID value
`stored relative to a previously occupied socket is that of
`the card last occupying that slot. Thus. if a card is in-
`stalled into a previously vacant slot or substituted for a
`card having a different ID, a mismatching comparison
`will occur causing the system to retrieve and/or de-
`velop new AD, PR, S, and O values for the responding
`card.
`As noted above, the system cannot deal with mis—
`matching indications until the states of all sockets have
`been ascertained. This is because the priority level, and
`in certain instances the address and state values, as-
`signed to any card are relative to the cards in other
`slots. The address and state values are relative when
`two cards with the same identity ID are currently in-
`stalled, either to provide redundant backup for device
`failure or to provide additional device capacity. In the
`latter instances, the state value can be used to place a
`backup device in an inactive state during normal system
`operation or the priority values can be used to allow
`both devices to operate fully but at different priority
`levels.
`In the preferred embodiment, system information is
`stored in the eight slot positions (only three—30, 31,
`32—are shown) of module 10 to accommodate up to
`eight feature cards 5-0 to 5-7. Each slot position is four
`bytes wide, twenty—eight bytes for seven feature cards.
`The card ID resides in the first two bytes and the switch
`(parameter) settings in, the last two bytes. The corre-
`sponding ID and parameter data on each card resides in
`drivers 20 and register 21. respectively.
`FIG. 3 shows schematically certain of the logic on
`the board 1 and feature card 5-7 used during setup rou-
`tines to read out a card ID and store parameters in the
`register 21. With respect to FIG. 3. the hexadecimal
`I/O address values assigned to certain of the compo-
`nents on each of the feature cards is as follows:
`096 - socket select value (one byte)
`100, 101 - ID drivers 20 (two bytes)
`102. 103 - parameter register 21 (two bytes)
`These are "dummy" addresses since they are used by
`the processor 8 to access I/O cards and components via
`the slots during setup operations. The address 096 se-
`lects the logic (gates 38, 39) of slot address decoder 14
`for storing the card select value into slot register 40 and
`also for reading out the value, i.e., during diagnosis.
`Address lines A0 and A1 of FIG. 3 form the lower
`address values 00, 01, 02. and 03 for selecting the com-
`ponents 20 and 21, while a logical l signal on address
`
`OLYMPUS EX. 1019 - 11/16
`
`

`

`5,038,320
`
`5
`A0, A1, and A2 are coupled to appropriate bit lines of
`address bus 17b, FIG. 2.
`FIG. 3 shows in more detail certain of the logic of the
`slot address decoder 14 and of the control logic 22 of
`card 7 which are used in the setup routines of FIGS. 6
`and 7. It will be assumed for simplicity of discussion,
`that addressing of two bytes at a time, i.e., one cycle, is
`available and that two byte data transfers occurs on
`busses. Hence, decoding address 101 gates both bytes
`for addresses 101 and 100.
`-
`. Slot register 40 is program controlled to store a three
`bit value (000-1 11) corresponding to a slot (2-0 to 2-7) to
`be accessed. A decode circuit 41 changes this three bit
`binary value to a one in eight line output but only when
`it is gated by a signal on input line 42. Each output line,
`such as EC7, is connected via the respective socket to
`the card held in the socket. When a decode circuit 43
`decodes an address in the range 0100 - 0103 during a
`setup routine, it produces an output on line 42 to gate
`the value in 40 to cause an output (see FIG. 4) on a card
`setup line such EC'I, one of the control lines 17a of bus
`17.
`
`5
`
`I0
`
`15
`
`20
`
`the identity value and parameter data of the card
`
`1. In a data processing system having a system pro-
`cessor and a plurality of I/O sockets to which periph-
`eral control cards of various types are attachable, and in
`which means on at least one card permanently stores an
`identity value corresponding to the respective card
`type, said system comprising:
`nonvolatile memory means storing, in memory loca~
`tions thereof assigned to respective I/O sockets,
`the identity value and parameter data of the at least
`one card connected to a respective socket when
`power was last applied to said system, said parame-
`ter data being representative of peripheral options
`for the attached card; and
`means effective after power has been removed from
`and reapplied to said system for comparing the
`identity value on said card connected to the respec-
`tive socket with the identity value stored in the
`corresponding nonvolatile memory location to
`determine if said card has been added, removed or
`moved since the previous removal of power from
`said system; and
`means responsive to outputs of said comparing means
`indicating successful comparison of the identity
`value for transferring and storing into said card,
`parameter data stored in the corresponding mem-
`ory location, thereby eliminating the need to create
`_
`the parameter data.
`2. A data processing system having a plurality of I/O
`sockets for attaching cards of different types, and in
`which the system during subsequent power-up retrieves
`parameter data for at least one card currently attached
`to the system by way of a respective socket and in
`which means is provided on the card for permanently
`storing an identity value corresponding to the card
`When two identical cards (same ID) are connected to 65 type, said system comprising;
`two of the 1/0 slots and it
`is desired to render both
`nonvolatile memory means storing, in memory loca—
`active, the first card is assigned the standard I/O default
`tions thereof assigned to respective I/O sockets,
`address at one priority level and the other card is as-
`
`6
`signed an alternate I/O address at a different priority
`level.
`‘
`
`The logic of FIG. 5 is then utilized during a diagnos-
`tic routine toi‘a'scertain whether each card properly
`responds to its respective I/O address. The address
`decode logic 23 decodes the address on bus 17b if it
`corresponds to the alternate address when the appropri-
`ate alternate address factor AD is stored in parameter
`register 21 and the least significant bit is on (the card is
`active). Similarly, a priority decode circuit 55 produces
`an output if the priority value on bus 17a is equal to PR
`in register 21 and the card active bit is on. If outputs are
`produced by logic 23 and 55, an AND gate 56 produces
`a feedback signal on line 57 to set one bit in a register 58
`on the board 1. The CPU8 under program control will
`read register 58 to determine that one and only one card
`properly responded to the I/O alternate address and
`reset register 58. Similar circuits on the other identical
`card will respond to the default I/O address and the
`appropriate priority level to set another bit in register 58
`for diagnostic purposes.
`While there have been described what are at present
`considered to be a preferred embodiment of this inven-
`tion, it willibe obvious to those skilled in the art that
`various changes and modifications may be made therein
`without departing from the invention, and it is, there-
`fore, intended to cover all such changes and modifica-
`tions as fall within the true spirit and scope of the inven-
`tion.
`What is claimed is:
`
`30
`
`This output on EC] is applied to AND gates 44 and
`45. The address line A2 is coupled to gates 44 and 45.
`An 1/0 read line IOR andan I/O write line [OW (de-
`coded from control lines 170) are coupled respectively
`to gates 44 and 45. An output 46 from gate 44 is coupled
`to a pair of decoder circuits 47 and 48. An output 49
`from gate 45 is coupled to a decode circuit 50. An out-
`put 51 from decode 48 is coupled to the ID driver cir-
`cuit 20 and the output 52 from decode 50 is coupled to
`the parameter register 21.
`During the post setup routine of FIG. 7, when an ID
`is being fetched from card 7, the processor 8 forces A2
`negative (logical
`l) and A1, A0 to logic Ol (address
`101). EC7 is negative (FIG. 4). When 10R goes nega-
`tive, the gate 44 produces an output at 46 to produce an
`output at 51 which gates the card ID value in 20 to data
`bus 17c. Processor 8 compares this [D with the ID in
`the respective slot position in memory module 10. If the
`IDs compare, processor 8 transfers the parameter val-
`ues in the slot position 32 (FIG. 1) to data bus 17c and
`forces A2, A1, A0 to logic 111 (address 103). Shortly
`thereafter, processor 8 issues an IOW to cause gate 45 to
`produce an output on 49. This gates an output from 50
`.to register 21 via line 52 to gate the parameter values on
`bus 17c into register 21. The output 53 of decode 47 is
`used during diagnostic routines to gate the output of
`parameter register 21 to bus 17c via gate 54.
`As discussed above with respect to a setup routine, an
`ID of hexadecimal value FFFF is returned during an
`ID fetch operation when the addressed socket is empty.
`One method of achieving this result is shown in FIG. 3.
`A pre-wired circuit 60 is gated to force bus 17 to all
`“1’s” during the 10R cycle by a negative going signal
`on any one of the enable card lines EC] to EC7 via 0R
`circuit 61 and the negative going signal on 10R. If a
`card is in the socket which has been addressed, its ID is
`gated to bus 17c at the same time and all logical 0’s in
`the ID override the logical
`[’5 from 60 to correctly 60
`reproduce the ID on bus 17c.
`The logic of FIG. 3 is used in a similar manner during
`the initialization setup and the POST setup routines of
`FIGS. 6 and 7.
`
`50
`
`55
`
`OLYMPUS EX. 1019 - 12/16
`
`

`

`identity information received
`
`7
`connected to the respective socket before
`tem is powered down;
`means effective upon power-up of the system for
`comparing the identity value stored on the at-
`tached card with the identity value stored in the
`nonvolatile memory location corresponding to the
`socket to which the card is attached; and
`means responsive to outputs of said comparing means
`indicating successful comparisons of identity val-
`ues for writing and storing into each respective
`card the parameter data stored in its corresponding
`nonvolatile memory location.
`3. The system of claim 2 further comprising
`said comparing means including means interrogating
`each l/O sooket to fetch and identity value of the
`card attached to the socket and to produce a unique
`null identity value when an interrogated socket is
`empty;
`said nonvolatile memory storing the null
`identity
`value in each location corresponding to an I/O
`socket found empty; and
`said comparing means further effective upon power-
`up of the system for comparing the null identity
`value produced upon interrogating an empty
`socket with the identity value in the nonvolatile
`memory location correspon
`ocket for
`determining i
`when the system previously was pow
`4. The system of claim 2 wherein the data processing
`system includes a system processing unit, the system
`further comprising
`a feedback line on the card,
`means on the card responsive to a card select input
`signal and to parameter data stored on the card for
`effectively enabling the card to send a signal to the
`system processing unit by way of said feedback line
`indicating selection of the card.
`5. The system of claim 2 further comprising
`said comparing means including means interrogating
`each [/0 socket to fetch the identity value of the
`card attached to the socket and to produce a prede-
`termined identity value to indicate when an inter-
`rogated socket is empty;
`said nonvolatile memory storing the predetermined
`identity value in each location corresponding to an
`empty 1/0 socket; and
`said comparing means further effective upon power-
`up of the system for comparing the predetermined
`identity value produced upon interrogating an
`empty socket with the identity value in the nonvol-
`atile memory location correspOnding to that socket
`for determining if that socket had contained a card
`owered down.
`6. In a computer system having atta