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Petitioner’s Supplemental Reply in Support of Petition
`IPR2017-01430
`
`
`DOCKET NO.: 2211726-00145
`Filed on behalf of Unified Patents Inc.
`By: David L. Cavanaugh, Reg. No. 36,476
`Daniel V. Williams, Reg. No. 45,221
`Matthew J. Leary, Reg. No. 58,593
`Wilmer Cutler Pickering Hale and Dorr LLP
`1875 Pennsylvania Ave., NW
`Washington, DC 20006
`Tel: (202) 663-6000
`Email: david.cavanaugh@wilmerhale.com
`
`Roshan Mansinghani, Reg. No. 62,429
`Jonathan Stroud, Reg. No. 72,518
`Unified Patents Inc.
`1875 Connecticut Ave. NW, Floor 10
`Washington, DC, 20009
`Tel: (202) 805-8931
`Email: roshan@unifiedpatents.com
`Email: jonathan@unifiedpatents.com
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`____________________________________________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`____________________________________________
`UNIFIED PATENTS INC.
`Petitioner
`v.
`PLECTRUM LLC
`Patent Owner
`IPR2017-01430
`Patent 5,978,951
`PETITIONER’S SUPPLEMENTAL REPLY
`
`
`
`
`

`

`Petitioner’s Supplemental Reply in Support of Petition
`IPR2017-01430
`
`
`TABLE OF CONTENTS
`
`I. 
`II. 
`
`B. 
`
`Page
`SUMMARY ..................................................................................................... 1 
`ROW-BASED SRAMS IN VIEW OF CHERITON ARE OBVIOUS ........... 2 
`A. 
`Row-based SRAM memories were well-known, and are the only type
`of SRAMs described in the record. ....................................................... 2 
`It would have been obvious for Cheriton’s SRAMs to have rows. ...... 3 
`B. 
`III.  EACH ELEMENT OF THE NEW CLAIMS IS DISCLOSED AND/OR
`RENDERED OBVIOUS IN VIEW OF CHERITON ...................................... 5 
`A. 
`Element 2(b) – “a cache comprised of plural rows, each having plural
`respective entries” and element 21(c) – “a cache having plural rows,
`each of said rows having plural entries” ............................................... 5 
`Element 2(f) – “using said received, encoded address information to
`identify one of said cache rows”, 21(h) – “using…said cache address
`to identify a cache entry” ...................................................................... 6 
`Element 1(g) – “comparing said coded address to a value associated
`with a row” ............................................................................................ 7 
`Element 2(g), [(i)] – “retrieving first [second] address information
`from a [said] first entry of said identified row” and element 1(h) – “in
`the event of a match…with said row, comparing said received
`destination address with a cached destination address associated with
`a first entry in said row” ........................................................................ 8 
`Dependent claims 3-6, 12-14 and 22-24 are rendered obvious ............ 9 
`E. 
`IV.  CONCLUSION ................................................................................................ 9 
`
`
`C. 
`
`D. 
`
`i
`
`
`

`

`Petitioner’s Supplemental Reply in Support of Petition
`IPR2017-01430
`
`
`SUMMARY
`Following the SAS decision, the Board instituted claims 1-6, 12-14, and 21-
`
`I.
`
`24 (the “New Claims”). Paper 16 at 2.
`
`Addressing Claim 1, the Board preliminarily asserted that Cheriton lacked: 1)
`
`a “comparison of values associated with a row in a cache,” and 2) the subsequent
`
`comparison of a value within that row. Paper 11 at 3. The first step uses, e.g., a
`
`hash value as an index/address to “identify” a cache row that potentially has routing
`
`data for a packet. E.g., ’951 patent (EX1001), Fig. 7B. Notably, Claims 2 and 21
`
`simply require that a row is “identif[ied]” without requiring comparing values. The
`
`second step retrieves an entry from that identified row and compares it to the
`
`incoming packet’s destination address to see if the row contains the hoped-for
`
`routing data. Id., Claim 2, ll. 56-59.
`
`These limitations comprise actions (identification and comparison) using
`
`particular data (values and destination addresses) stored in a specific structure
`
`(rows). The petition demonstrated that Cheriton explicitly taught the actions on the
`
`particular data, such as using a hash index to “identify” address data in an SRAM
`
`for element 2(f). Petition at 39-40. Hence, the Board’s preliminary decision
`
`amounted to finding that Cheriton does not explicitly disclose that the acted-upon
`
`data was in a row-based structure. Paper 11 at 3.
`
`But the petition and the as-filed record demonstrate that it would have been
`
`1
`
`
`

`

`Petitioner’s Supplemental Reply in Support of Petition
`IPR2017-01430
`
`obvious to use row-based SRAMs in Cheriton (addressed in Section II below). E.g.,
`
`Petition at 30-31. As a result, it would have been obvious for Cheriton’s disclosed
`
`actions on its disclosed data to have been used in row-based SRAMs (the structure
`
`the record demonstrates was obvious) (addressed in Section III below). Seshan
`
`(EX1007) ¶¶ 62, 86-100, 105-106. This is why Cheriton renders the New Claims
`
`obvious.
`
`For example, the Board does not appear to contest that Cheriton taught the
`
`action of retrieving and comparing destination addresses from multiple-entry
`
`elements in SRAM as per limitations 2(g) and 2(i). See Board Decision, Paper 8 at
`
`14-15. If that SRAM was row-based (which the petition and the as-filed record
`
`demonstrate was obvious), the Petition showed that Cheriton rendered obvious
`
`retrieving that address from a row. Petition at 40-41.
`
`II. ROW-BASED SRAMS IN VIEW OF CHERITON ARE OBVIOUS
`A. Row-based SRAM memories were well-known, and are the only
`type of SRAMs described in the record.
`There is no dispute that row-based SRAMs were well-known in the prior art.
`
`See Petition at 22-23; POPR at 6-8. To demonstrate the state of the art, the Petitioner
`
`provided both expert testimony and a corroborative reference, Fujishima. See
`
`Fujishima (EX1019); Seshan (EX1007) ¶¶ 62-64. As noted in the Petition,
`
`Fujishima teaches that “SRAM memory cell array 12 is provided with a cache row
`
`2
`
`
`

`

`Petitioner’s Supplemental Reply in Support of Petition
`IPR2017-01430
`
`decoder 43…. [which] is responsive to a cache row address signal … for selecting
`
`one row in the SRAM memory cell array.” Id. at 12:49-54; accord id. at 5:38-44
`
`(“The second [SRAM] memory cell array is divided into a plurality of regions each
`
`comprising the same number of a plurality of rows”).
`
`Row-based SRAMs are the only type of SRAM in the record. Such SRAMs
`
`were so common that Dr. Seshan explained that the POSA would understand
`
`Cheriton’s SRAM’s to be row based even if not explicitly stated. Seshan (EX1007)
`
`¶ 62. Properly understood, even the Ross reference cited by Patent owner used row-
`
`based SRAMs. Specifically, Ross cited prior art algorithms to efficiently find data
`
`in “array” (row-based) environments. See Ross (EX2001) at 1:38-67 (listing pre-
`
`1990 “array binary searches” indexing); Summary of Invention; Fig. 9; 7:34.
`
`B.
`It would have been obvious for Cheriton’s SRAMs to have rows.
`Responding to the arguments made in the POPR (p. 7), there were multiple
`
`reasons why it would have been obvious to use rows in Cheriton’s SRAMs. First,
`
`row-based SRAMS were not just known, but common—indeed, they are the only
`
`type of SRAMs in evidence. See, e.g., Cubist Pharms., Inc. v. Hospira, Inc., 805
`
`F.3d 1112, 1129 (Fed. Cir. 2015) (affirming obviousness because claimed
`
`purification method was “known to be one of the most common” options); Monsanto
`
`Tech. LLC v. E.I. DuPont de Nemours & Co., 878 F.3d 1336, 1346 (Fed. Cir. 2018)
`
`(a “patent can be obvious in light of a single prior art reference if it would have been
`
`3
`
`
`

`

`Petitioner’s Supplemental Reply in Support of Petition
`IPR2017-01430
`
`obvious to modify that reference to arrive at the patented invention”); Idemitsu
`
`Kosan Co. v. SFC Co., 870 F.3d 1376, 1382 (Fed. Cir. 2017) (affirming single-
`
`reference obviousness without extrinsic evidence). Second, it would have been
`
`obvious to try row-based SRAMs because doing so was one of a (very) limited
`
`number of potential solutions to arrange SRAM memory and to use that memory
`
`once so-arranged. See KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 421 (2007). The
`
`dearth of other options led Dr. Seshan to say that the POSA understood SRAMs to
`
`be row-based, which was corroborated by Fujishima; the record is devoid of any
`
`other possibility. Seshan (EX1007) ¶ 62. The use of row-based SRAMs would also
`
`have been obvious as the application of a well-known technique to the identical
`
`memory devices (SRAMs) that Cheriton uses, in the same way the POSA used row-
`
`based SRAMs in other prior art (such as Fujishima). See, e.g., KSR, 550 U.S. at 417.
`
`The POSA would have been motivated to use row-based SRAM solutions for
`
`storage in Cheriton with a high expectation of success. Row-based SRAMs were
`
`mature technology, having had existed and been in use for at least seven years before
`
`Cheriton’s 1995 filing (given Fujishima’s 1988 priority date). The record
`
`demonstrates that row-based SRAMs had been used successfully for years in caches
`
`in the same manner as Cheriton used SRAMs, which would make their use in
`
`Cheriton predictably successful. See Fujishima, title (“Semiconductor memory
`
`device for simple cache system”), Fig. 6. Cheriton also referred to its SRAMs
`4
`
`
`

`

`Petitioner’s Supplemental Reply in Support of Petition
`IPR2017-01430
`
`generically as existing devices which indicates that Cheriton would work
`
`successfully with commonly-available SRAMs—those that were row-based. See
`
`e.g., Cheriton (EX1002) at 9:29-33, Fig. 6.
`
`Finally, the Patent Owner’s complaint that the Petition argued inherency is
`
`wrong. This is not inherency—rather, given that the only evidence of record is that
`
`SRAM memory is arranged and identified as rows, it was obvious to identify data in
`
`the SRAMs by row. See Seshan (EX1007) ¶ 62; Cubist 805 F.3d at 1129. The lack
`
`of other options in the record simply highlights how all of the evidence supports the
`
`Petition.
`
`III. EACH ELEMENT OF THE NEW CLAIMS IS DISCLOSED AND/OR
`RENDERED OBVIOUS IN VIEW OF CHERITON
`A. Element 2(b) – “a cache comprised of plural rows, each having
`plural respective entries” and element 21(c) – “a cache having
`plural rows, each of said rows having plural entries”
`As Section II demonstrated, it would have been obvious to use rows in
`
`Cheriton’s SRAMs. This results in Cheriton rendering obvious a cache
`
`“comprising” rows. As shown in Cheriton Figure 6, SRAMs form the storage in
`
`Cheriton’s “virtual path cache,” and that cache would comprise rows when
`
`Cheriton’s SRAMs use rows. See id. (EX1002) Figs. 6, 3, 5:64; Seshan (EX1007)
`
`¶¶ 62, 104-105.
`
`With respect to “rows having plural…entries,” Cheriton states that the data it
`
`5
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`

`

`Petitioner’s Supplemental Reply in Support of Petition
`IPR2017-01430
`
`stores comprises multiple entries. See, e.g., Cheriton (EX1002) at Fig. 3 (showing
`
`various fields), 8:53-61. Specifically, the data elements that Cheriton stores in its
`
`SRAMs include various “fields,” each of which is also an “entry” as shown in
`
`Cheriton Fig. 3 (EX1002) (showing a “tag field” with source/destination addresses).
`
`As the petition demonstrated, these entries would thus be stored in rows when using
`
`row-based SRAMs. Petition at 33, 37-38; Seshan (EX1007) at ¶ 105; Cheriton
`
`(EX1002) at Fig. 6.
`
`B.
`
`Element 2(f) – “using said received, encoded address information
`to identify one of said cache rows”, 21(h) – “using…said cache
`address to identify a cache entry”
`Cheriton explicitly taught the action of identifying (looking up) data in
`
`SRAMs by address. Petition at 39-40 (citing Cheriton, 10:46-49; 9:34-38). And
`
`when using row-based SRAMs, that same addressing would identify rows in those
`
`SRAMs for claims 2 and 21. See Seshan (EX1007) ¶¶ 114-116. Such row-based
`
`addressing is the only disclosed method of identifying data in such SRAMs. Petition
`
`at 30-31. Corroborating this, Fujishima states that “SRAM memory cell array 12 is
`
`provided with a cache row decoder 43…. [which] is responsive to a cache row
`
`address signal … for selecting one row in the SRAM memory cell array.” Id.
`
`(EX1019) at 12:49-54; emphasis added.
`
`
`
`6
`
`
`

`

`Petitioner’s Supplemental Reply in Support of Petition
`IPR2017-01430
`
`
`C. Element 1(g) – “comparing said coded address to a value
`associated with a row”
`The row-based addressing/identification discussed in the previous section also
`
`constitutes a “comparison” of the searched-for address to the address associated with
`
`a row in the SRAM for claim element 1(g). See Petition at 30-31.
`
`Cheriton confirms that address-based indexing (which would address rows
`
`when using row-based SRAMs)
`
`is
`
`the same as
`
`the “comparison” and
`
`“identif[ication]” in the New Claims. Immediately after explaining that its “virtual
`
`path index” “indexes” the SRAMs, Cheriton notes that the same “virtual path index
`
`is further compared in parallel” to the SRAM outputs. Petition at 30 (citing Cheriton
`
`(EX1002) at 10:49-52, 9:34-38 (index is used to “look[] up the four parallel sets of
`
`the virtual path cache SRAMs 601 through 604.”)
`
`The ’951 patent and its file history confirm that an address-based lookup as
`
`Cheriton discloses, is the same as the claimed “comparison” recited in claim 1. The
`
`patent describes its cache “lookup” (which corresponds to the “comparison” claim
`
`element) as an address-based lookup and explains that “cache 28 configuration
`
`information is required by the ACA 26 to properly generate SRAM addresses,” and
`
`that the ACA is used “to lookup data in the cache”); (emphasis added). Figures 6a-
`
`6c also show the ‘ACA’ looking up data in SRAMs by “adr” (address). Id.; id. at
`
`2:28-34 (use of “CRC code of the address to be searched”); 5:47-50; File History,
`
`7
`
`
`

`

`Petitioner’s Supplemental Reply in Support of Petition
`IPR2017-01430
`
`(EX1017) at 5 (claims 1 & 2 “recite the coding of a portion of a received, destination
`
`address….used to index rows of a cache.”).
`
`D. Element 2(g), [(i)] – “retrieving first [second] address information
`from a [said] first entry of said identified row” and element 1(h) –
`“in the event of a match…with said row, comparing said received
`destination address with a cached destination address associated
`with a first entry in said row”
`Cheriton retrieves a first/second address from its SRAMs as an entry from an
`
`earlier-stored, multi-entry “tag field 310.” Petition at 40-42; Cheriton, (EX1002) at
`
`10:52-56 (retrieving “the virtual path record stored in SRAM cache”); Fig. 3 (entries
`
`in that record include a multiple addresses); 7:10-27; Fig. 6. Since it would have
`
`been obvious to use row-based SRAM in Cheriton, then the destination address
`
`would be stored in a row. That is, Cheriton stores its addresses as entries in the
`
`SRAMs, those addresses are later retrieved from the SRAMs, and Cheriton would
`
`retrieve the entries from the rows in the SRAMs since Cheriton renders a row-based
`
`SRAM implementation obvious. Id. at 10:52-56, Fig. 6.
`
`After locating a row per element 1(g) or 2(f) as just explained, Cheriton also
`
`discloses the later “comparison” of the addresses in the tag field from the SRAMs at
`
`comparators 611, 612, 613, and 614. Id. at Fig. 6, 9:34-43. Cheriton compares the
`
`address found in the row to the “source-destination address pair of the incoming
`
`datagram” that Cheriton receives. Id.; Seshan (EX1007) ¶¶ 90-94.
`
`
`
`8
`
`
`

`

`Petitioner’s Supplemental Reply in Support of Petition
`IPR2017-01430
`
`
`E. Dependent claims 3-6, 12-14 and 22-24 are rendered obvious
`The additional row-based elements of claims 12-14 and 24 are obvious for the
`
`reasons given above and in the Petition, and also because (for claim 14) “tag field
`
`310” also has a “source address.” See §§ III.A-III.D, supra. As shown in the
`
`Petition, the prior art, alone or in combination, discloses the remaining non-row-
`
`related elements of the New Claims. Petition at 24-71.
`
`IV. CONCLUSION
`For the foregoing reasons,1 the Board should enter a final decision finding
`
`each of the New Claims, as well claims as 8 and 11, unpatentable under 35 U.S.C. §
`
`103.
`
`
`
`
`
`
`1 The Board denied Petitioner’s request to support this reply with rebuttal evidence.
`
`Paper 17. Petitioner respectfully reserves its rights to judicial review of that denial.
`
`9
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`

`

`Petitioner’s Supplemental Reply in Support of Petition
`IPR2017-01430
`
`
`
`
`
`
`Respectfully Submitted,
`
`/Matthew J. Leary/
`
`David L. Cavanaugh
`Registration No. 36,476
`
`Roshan Mansinghani
`Registration No. 62,429
`
`Jonathan Stroud
`Registration No. 72,518
`
`Daniel V. Williams
`Registration No. 45,221
`
`Matthew J. Leary
`Registration No. 58,593
`
`
`
`10
`
`
`
`
`
`
`
`
`

`

`
`
`
`
`
`Petitioner’s Supplemental Reply in Support of Petition
`IPR2017-01430
`
`
`Table of Exhibits for Petitioner’s Supplemental Reply
`
`Exhibit
`1001
`1002
`1003
`
`1004
`
`1005
`1006
`1007
`1008
`1009
`1010
`1011
`1012
`1013
`1014
`1015
`1016
`1017
`1018
`1019
`1020
`
`1021
`
`1022
`
`Description
`US Pat. No. 5,978,951
`US Pat. No. 6,091,725 (“Cheriton”)
`European Patent Application No. EP0522743A1 (“Jain”)
`Kessler et al., “Inexpensive Implementations of Set-
`Associativity”, 17:3 ACM SIGARCH Computer Architecture
`News – Special Issue: Proceedings of the 16th annual
`international symposium on Computer Architecture 131 (June
`1989) (“Kessler”)
`Kessler with date stamp from Library of Congress
`Declaration of Scott Bennett
`Declaration of Professor Srinivasan Seshan
`US Pat. No. 5,566,170 (“Bakke”)
`Newman et al., “IP Switching and Gigabit Routers”, IEEE
`Comm. Magazine 64 (Jan. 1997) (“IP Switching”))
`US Pat. No. 5,914,938 (“Brady”)
`US Pat. No. 5,917,821 (“Gobuyan”)
`US Pat. No. 5,509,135 (“Steely”)
`US Pat. No. 4,377,855 (“Lavi”)
`File History, Application (12/11/97)
`File History, Preliminary Amendment (3/10/1998)
`File History, Office Action (11/09/98)
`File History, Amendment (02/09/99)
`File History, NOA (03/15/99)
`US Pat. No. 5,226,147 (“Fujishima”)
`Petitioner’s Voluntary Interrogatory Responses
`Raj Jain, A Comparison of Hashing Schemes for Address Lookup
`in Computer Networks, IEEE Trans. On Comm., Vol 40, No. 10
`at 1570-73 (Oct. 1992) (“Hashing Comparison”)
`Raj Jain, A Comparison of Hashing Schemes for Address Lookup
`in Computer Networks, DEC-TR-593 (1989) (“Hashing Technical
`Report”)
`
`
`
`i
`
`
`

`

`Petitioner’s Supplemental Reply in Support of Petition
`IPR2017-01430
`
`
`CERTIFICATE OF SERVICE
`I hereby certify that on June 8, 2018, I caused a true and correct copy of the
`
`foregoing materials:
`
` Petition’s Supplemental Reply Under 35 U.S.C. § 312 and 37 C.F.R. §
`42.104
` Exhibit List
`to be served via email on the following correspondent of record as listed on PAIR:
`
`
`Antonelli, Harrington & Thompson LLP
`4306 Yoakum Blvd., Ste. 450
`Houston, TX 77006
`(713) 581-3000
`Emails: zac@ahtlawfirm.com
`matt@ahtlawfirm.com
`larry@ahtlawfirm.com
`
`/Matthew J. Leary/
`Matthew J. Leary
`
`
`
`ii
`
`
`

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