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`05005226147A
`
`[:91
`United States Patent
`[11] Patent Number:
`5,226,147
`
`[45] Date of Patent.
`Jul. 6, 1993
`Fujishima et a1.
`
`[54] SEMICONDUCI‘OR MEMORY DEVICE FOR
`SIMPLE CACHE SYSTEM
`
`5,014.240
`5,111,386
`
`5/1991 Suzuki ................................... 365/49
`5/1992 Fujishima et a1.
`395/425
`
`[75]
`
`Inventors: anuyasu Fujishimn; Yoshio‘
`Matsuda; Miltio Asakura, all of
`Hyogo, Japan
`
`[73] Assignee: MimuhishiDenkIKahushiki Knish,
`Tokyo, Japan
`
`[2]] App]. 140.: 564,657
`
`[22] Filed:
`
`Aug. 9, 1990
`
`‘
`Related US. Application Data
`Continuation of Ser. No. 266,601. Nov. 3, I988, aban-
`cloned.
`
`[63]
`
`Foreign Application Priority Date
`[30]
`Nov. 6, 1987 up]
`Japan .............................. .. 62-281619
`
`Dec. 17, 1987 [JP]
`Japan
`.. 62-322126
`
`[51]
`
`Int. C1.5
`
`................. 60637 12/00; GO6F 12/08;
`GO6F 13/00; 6110 7/00
`....... 395/425; 365/230.03;
`[52] US. Cl. ..................
`365/63; 365/49; 364/1316. l; 364/2414]
`[58] Field of Search ...................... 365/49, 230.03, 63;
`364/200 MS File, 900 MS File, 243.4, 243.41,
`'
`964, 964.2; 395/425
`
`156]
`
`References Cited
`U.5. PATENT DOCUMENTS
`
`9/1979 DeKarske ............................. 365/49
`4.168.541
`8/1980 Kobayashi et al.
`365/49 X
`4,219,883
`
`3/1986 Matick et a1.
`365/49
`4.577.293
`4,656,626 4/1987 Yudichak
`365/49
`
`4,669,043
`5/1987 Kaplinsky .. ...
`. . . ... 364/200
`365/189.05
`4,731,758
`3/1988 Lam et al.
`4.754.433 6/1988 Chin et al.
`365/189.02
`.
`4,845,677 7/l989 Chappell et a1.
`365/l89.02
`4,872,138 10/1989 Ciacci ............. ..
`365/49
`4,926,385
`5/1990 Fujishima et al.
`. 365/230.03
`
`4,953,073 8/l990 Moussouris et a1.
`364/200
`
`
`
`' OTHER PUBLICATIONS
`Asakura et al., "An Experimental le Cache DRAM
`with ECC”, 1989 Symposium on VLSI Circuits (May
`25~27, 1989), pp. 43—44.
`l-Mbit Cache
`Asakura ~et al., “An Experimental
`DRAM with ECG”; IEEE Journal afSolid—Smre Cir—
`cuits. vol. 25, No.
`1 (Feb. 1990), pp. 5-10.
`Hidaka et al., “The Cache DRAM Architecture: A
`DRAM with an 0n~Chip Cache Memory", IEEE
`Micro (Apr. 1990) PP. 15—24.
`Primary Examiner—Alyssa H. Bowler
`Attorney. Agent. or Firm—Lowe, Pn'ce, LeBlanc &
`Becker
`‘
`
`ABSTRACT
`[57]
`A semiconductor memory device comprises in DRAM
`memory cell array comprising a plurality of dynamic
`type memory cells arranged in a plurality of rows and
`columns, and an SRAM memory cell array comprising
`static type memory cells arranged in a plurality of rows
`and columns. The DRAM memory cell array is divided
`into a plurality of blocks each comprising a plurality of
`columns. The SRAM memory cell array is divided into
`a plurality of blocks each comprising a plurality of
`columns, corresponding to the plurality of blocks in the
`DRAM memory cell array. The SRAM memory cell
`array is used as a cache memory. Al the time of cache
`hit, data is accessed to the SRAM memory cell array.
`At
`the time of cache miss, data is accessed to the
`DRAM memory cell array. On this occasion, data cor-
`responding to one row in each of the blocks in the
`DRAM memory'cell array is transferred to one row in
`the corresponding block in the SRAM memory cell
`array.
`
`19 China, 12 Drawing Sheets
`
`
`
`UNIFIED 1019
`
`UNIFIED 1019
`
`

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`July 6,1993
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`US. Patent
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`July 6, 1993
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`July 6,1993
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`US. Patent
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`July 6, 1993
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`1
`
`5,226,147
`
`V SEMICONDUCTOR MEMORY DEVICE FOR
`SIMPLE CACHE SYSTEM
`
`This application is a continuation; application of ap-
`plication ser. No. 07/266,601, filed Nov. 3, 1988, now
`abandoned.
`Related, copending application of particular interest
`to the instant application is US. Ser. No. 07/266,060
`entitled “Cache Contained Type Semiconductor Mem~
`ory Device and Operating Method Therefor" filed
`Nov. 2, 1988 and assigned to the same amignee of the
`instant application. The application issued as US. Pat.
`No. 5,111,386.
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`The present invention relates generally to semicon~
`ductor memory devices for a simple cache system, and
`more particularly, to semiconductor memory devices
`having a cache memory integrated on a chip on which
`the semiconductor memory device is formed.
`2. Description of the Prior Art
`Conventionally,
`in order to improve cost perfor-
`mance of a computer system, a small capacity and high-
`speed memory has been frequently provided as a high-
`speed buffer between a main memory structured by a
`lowvspeed but
`large capacity and low-cost dynamic
`random access memory (DRAM) and a central process-
`ing unit (CPU). The high~spoed buffer is referred to as
`a cache memory. A block of data which the CPU may
`request is copied from the main memory and stored in
`the high-speed buffer. The state in which data stored in
`an address, in the DRAM, which the CPU attempts to
`access exist in the cache memory is referred to as “hit”.
`In this case, the CPU makes access to the high-speed
`cache memory, and acquires the requested data from
`the cache memory. On the other hand, the state in
`which data stored in an address which the CPU at-
`tempts to access does not exist in the cache memory is
`referred to as "cache miss". In this case, the CPU makes
`access to the low-speed main memory, acquires the
`requested data from the main memory and at the same
`time. transfers to the cache memory a data block to
`which the data belongs.
`However, such a cache memory system could not be
`employed in a small-sized computer system attaching
`important to the cost because it requirm a high-cost and
`a high-speed memory. Conventionally, a simple cache
`system has been configured utilizing a high-speed access
`function of a general-purpose DRAM, such as a page
`mode and a static column mode.
`FIG. 1 is a block diagram showing a basic structure
`of a conventional DRAM device having a function of a
`page mode or a static column mode.
`~
`In FIG. I, a memory cell array 1 has a plurality of
`word lines and a plurality of bit line pairs arranged
`intersecting with each other, memory cells being pro-
`vided at intersections thereof, respectively. In FIG. I,
`there are typically shown on] a single word line WI...
`a single bit line pair BL and h and a single memory
`cell MC provided at an intersection of the word line
`WL and the bit line BL. The word lines in the memory
`cell array 1 are connected to a row decoder portion 3
`through a word driver 2. In addition, the bit line pairs in
`the memory cell array 1 are connected to a column
`decoder portion 6 through a sense amplifier portion 4
`and an [/0 switching portion 5. A row address buil‘er 7
`
`5
`
`10
`
`15
`
`25
`
`30
`
`35
`
`45
`
`55
`
`65
`
`2
`is connected to the row decoder portion 3, and a col-
`umn address buffer 8 is connected to the column de-
`coder portion 6. A multiplex address signal MPXA
`obtained by multiplexing a row address signal RA and a
`column address signal CA is applied to the row address
`buffer 7 and the column address buffer 8. An output
`buffer 9 and an input buffer 10 unconnected to the 1/0
`switching portion 5.
`’ FIGS. 2A, 23 and 2C are waveform diagrams show-
`ing operations in an ordinary read cycle, a page mode
`cycle and a static column mode cycle of the DRAM,
`respectively.
`‘
`In the ordinary read cycle shown in FIG. 2A, the
`row address buffer 7 first acquira the multiplex address
`signal MPXA at the falling edge of a row address strobe
`signal m and applies the same to the row decoder
`portion 3 as a row address signal RA. The row decoder
`portion 3 is responsive to the row address signal RA for
`selecting one of the plurality of word lines. The selected
`word line is activated by the word driver 2. Conse‘
`quently, information stored in the plurality of memory
`cells connected to the selected word lines are read out
`onto the corresponding bit lines. respectively. The in-
`formation are detected and amplified by the sense am-
`plifier portion 4. At this time point, information stored
`in the memory cells corresponding to one row are
`latched in the sense amplifier portion 4. Then, the col~
`umn address buffer 8 acquires the multiplex address
`signal MPXA at the falling edge of a column address
`strobe signal C33 and applies the same to the column
`decoder portion 6 as a column address signal CA. The
`column decoder portion 6 is responsive to the column
`address signal CA for selecting one of information cor-
`responding to one row latched in the sense amplifier
`portion 4. This selected information is extracted to the
`exterior through the I/O switching portion 5 and the
`out at buffer 9 as output data Dom: An access time
`access time) true in this case is the time period
`elapsed from the falling edge of the row addrem strobe
`signal an until the output data Dow-becomes valid.
`In addition, a cycle time t; in this case is the sum of the
`time period during which the device is in an active state
`and an m precharge time my. As a standard value, tc
`is approximately 200 as when trucis 100 as.
`In the page mode cycle and the static column mode
`cycle shown in FIGS. 28 and 2C, memory cells on the
`same row address are accessed by changing the column
`address signal CA. In the page mode cycle, the column
`address signal CA is latched at the falling edge of the
`column address strobe signal as. Thus. the access
`time is a time period chc (CA8 access time) elapsed
`from the falling edge of the column address strobe sig‘
`nal CKS until the output data Dow becomes valid,
`which becomes a time period of approximately one-half
`of the access time time in the ordinary cycle, i.e., ap-
`proximately 50 as, where tcp denotes a
`recharge time
`of the column address strobe signal Cfi, and trc de-
`notes a cycle time.
`In the static column mode, access is made in response
`to only the change 'm the column address signal CA, as
`in a static RAM (SRAM). Thus. the access time is a
`time period t,“ (address access time) from the time
`when the column address signal CA is changed to the
`time when the output data Dourbccomes valid, which
`becomes approximately one-half of the accem time
`tmcin the ordinary cycle similarly to tac, i.e., gener-
`ally about 50 ns.
`'
`
`

`

`5,226,147
`
`.
`3
`More specifically, in the page mode cycle, when the
`falling edge of the column address strobe signal as is
`inputted to the column address buffer 8, the column
`address signal CA is sent to the column decoder. There-
`fore, any of the data corresponding to one row latched
`in the sense amplifier portion 4 is made valid,- so that the
`output data Douris obtained through the output buffer
`9. Also in the static column mode cycle. the same opera-
`tion as that in the page mode cycle is performed except
`a reading operation is initiated in response to the change
`in addrefi signal,
`FIG, 3 is a block diagram showing a structure of a
`simple cache system utilizing the page mode or the
`static column mode of the DRAM device shown in
`FIG. I. In addition, FIG. 4 is a waveform diagram
`showing an operation of the simple cache system shown
`in FIG. 3.
`In FIG. 3, a main memoryrzo comprises 1M byte
`which comprises 8 DRAM devices 21 each, having
`IM X 1 organization. In this case, the row address signal
`RA and the column address signal CA having a total of
`20 bits (220:1048576==1M) are required. An address
`multiplexer 22, which applies 10-bit row address signal
`RA and the 10-bit column address signal CA to the
`main memory 20 two times. has 20 address lines A0 to
`An receiving a 20-bit address signal and 10 address lines
`Aoto A9 applying a 10-bit address signal as multiplexed
`(multiplex address signal MPXA) to the DRAM de~
`vices 21.
`It is assumed here that data corresponding, to one r0w
`selected by a row address RAL has been already
`latched in the sense amplifier portion 4 in each of the
`DRAM devices 21. An address generator 23 generates
`a 20-bit address signal correspOnding to data which the
`CPU requests.» The latch TAG) 25 holds the row ad-
`dress RAL corresponding to data selected in the pre-
`ceding cycle. A comparator 26 compares the 10-bit row
`address RA out of the 20-bit address signal with the row
`address RAL held in the TAG 25. When both coincide
`with each other, which means that the same row as that
`accessed in the preceding cycle is accessed (“hit”), the
`comparator 26 generates an “H” level cache hit signal
`CH. A state machine 27 is responsive to the cache hit
`signal CH for performing page mode control in which a
`column address strobe signal m is toggled (raised and
`then, lowered) with a row address strobe signal was
`being kept at a low level. In response thereto, the ad-
`dress multiplexer 22 applies the column address signal
`CA to the DRAM devices 21 (see FIG. 4). Thus, data
`corresponding to the column address signal CA is ex.
`tracted from a group of data latched in the sense ampli-
`fier portion in each of the DRAM devices 2!. In the
`case of such "hit", output data is obtained from the
`DRAM devices 21 at high speed in an access time tcxc.
`On the other hand, when the row address signal RA
`generated from the address generator 23 and the row
`address KAI. held in the TAG 25 do not coincide with
`each other, which means that a different row from the
`row accessed in the preceding cycle is accessed ("cache
`miss"), the comparator 26 does not generate the "H"
`level cache hit signal CH. in this case, the state machine
`27 performs ordinary m and as control in the ordi-
`nary read cycle, and the address multiplexer 22 sequen-
`tially applies the row address signal RA and the column
`address signal CA to the DRAM devices 21 (see FIG.
`5). In the case of such “cache miss", the ordinary read
`cycle beginnin with precharging of the row address
`strobe signal
`_
`occurs, so that output data is obtained
`
`4
`at low speed in the access time tmc. Therefore, the
`state machine 27 generates a wait signal Wait, to bring .
`a CPU 24 into a Wait state. In the case of “cache miss",
`a new row address signal RA is held in the TAG 25.
`As described in the foregoing, in the simple cache .
`system shown in FIG. 3, data corresponding to one row
`of the memory cell array in each of the DRAM devices
`(1024 bits in the case of a 1M bit device) is latched in a
`sense amplifier portion as one block. Therefore, the
`block size is unnecessarily large and'the blocks (entries)
`held in the TAG 2.5 are insufficient in number. For
`example, in the system shown in FIG. 3, the number of
`entries becomes I. Thus, only when access is continu-
`ously made to the same row address, cache hit occurs.
`Consequently, for example, when a program routine
`bridged over continuous two row addresses is repeat-
`edly implemented,.cache miss necessarily occurs, so
`that a cache hit rate is low.
`Meanwhile, as another conventionally example, a
`simple cache system has been proposed, which is dis-
`closed in 11.5. Pat. No. 4,577,293. In this simple cache
`system, a register holding data corresponding to one
`row is provided outside a memory cell array. In the case
`of "hit". the data is directly extracted from this register,
`so that accessing is speeded up. However, in the simple
`cache system disclosed in the US. Patent, the external
`register holds data corresponding to one row in the
`memory cell array, so that the block size is unnecessar-
`ily large and the. cache hit rate is low as inrthe conven-
`tional example shown in FIG. 1 and 3.
`'
`
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`
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`
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`
`SUMMARY OF THE INVENTION
`One object of the present invention is to provide a
`semiconductor memory device which can configure a
`highvspeed simple cache system having a high cache hit
`rate.
`’
`
`35
`
`Another object of the present invention is to provide
`a semiconductor memory device which can configure a
`simple cache system having an increased number of
`entries.
`'
`Still another object of the present
`invention is to
`provide a semiconductor memory device containing a
`cache memory in which an access time at the time of
`cache hit can be shortened.
`Still another object of the preseni invention is to
`provide a semiconductor memory device containing a
`cache memory in which the number of entries of data
`can be increased without unmeasurin increasing the
`data block size.
`A further object of the present invention is to provide
`an operating method for a semiconductor memory de-
`vice which can configure a high~speed simple cache
`system having a high cache hit rate.
`A still further object of the present invention is to
`provide an operating method for a semiconductor mem-
`ory device containing a cache memory in which an
`access time at the time of cache hit can be shorten.
`The semiconductor memory device according to the
`present invention is a semiconductor memory device
`containing a cache memory employed in a simple cache
`system including a generator for generating a cache
`hit/miss indicating signal, which comprises a first mem-
`ory cell array, a second memory cell array. first access
`means, second access means. and data transfer means.
`The first memory cell array comprises a plurality of
`memory cells arranged in a plurality of rows and-col-
`umns. The second memory cell array comprises a plu-
`rality of static type memory cells arranged in a plurality
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`memory cell array._,‘In addition, a plurality of data
`blocks respectively on a plurality of different rows in
`the same block in the first memory cell array can be
`simultaneously held in different regions in the second
`memory cell array. Furthermore, the data blocks re-
`spectively on the plurality of different rows in the same
`block in the first memory cell array can be arranged on
`, one row in the second memory cell array.
`Thus, if the second memory cell array is utilized as a
`cache memory. the number of entries of data can be
`efficiently increased, so that the cache hit rate can be
`improved. Additionally, access can be made to the sec-
`ond memory cell array before determination of cache
`hit/cache miss. In this case, data are extracted from the
`plurality of regions in the second memory cell array.
`‘ Thereafter, when it is determined that cache hit occurs.
`any of the data extracted from the plurdity of regions is
`selected. When it is determined that cache miss occurs.
`the data extracted from the second memory cell array is
`ignored. Thus, an access time at the time of cache hit
`can be shorten. As a result, semiconductor memory
`' device can configure a high-speed simple set associative
`cache system having a high cache hit rate.
`BRIEF DESCRIPTION OF THE DRAWINGS
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`of rows and a plurality of columns corresponding to the
`plurality of columns in the first memory cell array. The
`first access means is responsive to a cache miss indicat-
`ing signal for accessing data to a memory cell selected
`by a first row address signal externally applied and a
`column address signal externally applied in the first
`memory cell array. The second access means is respon-
`sive to a cache hit indicating signal for accessing data to
`a static type memory cell selected by a second row
`address signal externally applied and the column ad-
`drem signal externally applied in the second memory
`cell array. The datatransfer. means transfers data be
`tween a row selected‘by the first row address signal
`externally applied in the first memory ceil array and a
`row selected by the seCOnd row address signal exter-
`nally applied in the second memory cell array.
`In the semiconductor memory device according to
`the present invention, since the second memory cell
`array comprises a plurality of statictype memory cells
`in a plurality of rows, data blocks on different rows in
`the first memory cell array can be held in the secbnd
`memory cell array. Thus. the semiconductor memory
`device can configure a simple cache system in which
`the number of entries is increased so that a cache hit rate
`is improved.
`In accordance with another aspect of the prwent
`invention, a semiconductor memory device for a simple
`cache system having a cache memory integrated on a
`chip on which the semiconductor memory device is
`formed comprises a first memory cell array, a second
`memory cell array, first access means, second access
`means, block selecting means, region selecting means,
`data transfer means and data selecting means.
`The first memory cell array comprises a plurality of
`memory cells arranged in a plurality of rows and col-
`umns. The first memory cell array is divided into a
`plurality of blocks each comprising a plurality of col-
`umns. The second memory cell array comprises a plu-
`rality of static type memory cells arranged in a plurality
`of rows and columns. The second memory cell array is
`divided into a plurality of regions each comprising the
`same number of a plurality of rows as the plurality of
`columns included in each of the plurality of blocks in
`the first memory cell array. The first access means ac-
`cesses data to a memory cell selected by a first row
`address signal externally applied and a column address
`signal externally applied in the first manory cell array.
`The second access means accesses data to a static type
`memory cell selected by a cache address signal exter-
`nally applied in the plurality of regions in the second
`mory cell array.
`The block selecting means is responsive to a block
`selecting signal extemally applied for selecting any of
`the plurality of blocks in the first memory cell array.
`The region selecting means is responsive to a region
`selecting signal externally applied for selecting any of
`the plurality of regions in the second memory cell array.
`The data transfer means transfers data between the a
`block, in the first memory cell array, selected by the
`block selecting means and the region,
`in the second
`memory cell array, selected by the region selecting
`means. Data selecting means is responsive to the region
`selecting signal for selecting any of data to/from the
`plurality of static type memory cells accessed by the
`mound accea means in the plurality of regions.
`In this semiconductor memory device containing a
`cache memory, data blocks on the plurality of rows in
`the first memory cell array can be held on the second
`
`.
`
`FIG. 1 is a block diagram showing a structure of a
`conventional DRAM device;
`FIG. 2A is a waveform diagram showing an opera-
`tion in an ordinary read cycle of the conventional
`DRAM device;
`.
`FIG. 23 is a waveform diagram showing an opera-
`tion in a page mode cycle of the conventional DRAM
`device;
`'
`FIG. ZC is a waveform diagram showing an opera-
`tiOn in a static column mode cycle of the conventional
`DRAM device;
`‘
`-
`FIG. 3 is a block diagram showing a structure of a
`simple cache system utilizing the DRAM device shown
`in FIG. 1;
`'
`FIG. 4 is a waveform diagram showing an operation
`of a simple cache system shown in FIG. 3;
`FIG. 5 is a block diagram showing a structure of a
`DRAM device containing a cache memory according
`to one embodiment of the present invention;
`FIG. 6 is a block diagram showing specifically a
`gtructure ofa part ofthe DRAM device shown in FIG.
`FIG. 7 is a block diagram showing a structure of a
`simple cache system utilizing the DRAM device shown
`in FIG. 5;
`FIG. 8 is a waveform diagram showing an operation
`of the simple cache system shown in FIG. 7;
`FIG. 9 is a block diagram showing a structure of a
`semiconductor memory device according to another
`embodiment of the present invention;
`FIG. 10 is a block diagram showing specifime a
`structure of a part of the semiconductor memory device
`shown in FIG. 9;
`FIG. 11 is a block diagram showing a structure of a
`simple set associative cache system utilizing the semi.
`conductor memory device shown in FIG. 9; and
`FIG. 12 is a waveform diagram showing an operation
`of the simple cache system shown in FIG. 11.
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
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`Referring now to the drawings, embodiments of the
`present invention will be described in detail.
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`FIG. 5 is a block diagram showing a structure of a
`DRAM device containing a cache memory according
`to one embodiment of the present invention.
`This DRAM device is the same as the conventional
`DRAM device shown in FIG, 1 except for the follow—
`ing. More specifically. a DRAM memory cell array 1 is
`divided into a plurality of blocks each comprising
`DRAM memory cells (dynamic type memory cells) in a
`plurality of rows on the address space. In FIG. 5, the
`DRAM memory cell may 1 is divided into four blocks
`81 to B4. In addition, a transfer gate portion 11 and a
`static random access memory type memory cell array
`(referredto as SRAM memory cell array hereinafter)
`are previded between a sense amplifier portion 4 and an
`[/0 switching portion 5. Furthermore, block decoders
`13a to d and a way decoder 14 are provided. The
`SRAM memory cell array 12 is divided into four blocks
`a to (1 corresponding to the four blocks Bl to B4 in the
`DRAM memory celllarray 1. Activation of each of the .
`20
`block decoders 13a to 13d is controlled by an AND gate
`(31 to which more significant two bits of a column ad-
`dress signal CA from a column address buffer 8 and an V
`inverted signal of a cache hit sing CH are inputted.
`More speCifically, when the cache hit signal CH is at an
`“L” level, a block decoder corresponding to a block
`selected by more significant two bits of the column
`address signal CA is activated. On the other hand, when
`the cache hit signal CH‘is at an “H” level, no block
`decoder is activated. In addition, a way address signal
`WA is applied to the way decoder 14 through a way
`address buffer 15. The way decoder 14 is responsive to
`the way address signal WA for selecting and driving
`word lines in the SRAM memory cell array 12. Circuit
`blocks shown in FIG. 5 are all formed on the same
`semiconductor chip.
`FIG. 6 is a diagram showing specifically a structure
`of a part of the DRAM device shown in FIG. 5.
`In FIG. 6, a sense amplifier portion 4, a transfer gate
`portion 11. an l/O switching portion 5 and a column
`decoder portion 6 comprise a plurality of sense amplifi-
`ers 40, a plurality of transfer gates 110, a plurality of I/O
`switches 50 and a plurality of column decoders 60,
`respectively, corresponding to a plurality of bit line
`pairs BL and E in the DRAM memory cell array 1.
`Each of the sense amplifiers 40 is connected between
`each of the bit line pairs BL and BIZ. Each of the trans»
`fer gates 60 comprises N channel MOSFETs Q1 and
`Q2. Each of the 1/0 switches 50 comprises N channel
`MOSFETs Q3 and Q4. In the SRAM memory cell
`array 12. a plurality of bit line pairs 83].. and SEE are
`arranged corresponding to the plurality of bit line pairs
`31. and E]: in the DRAM memory cell array 1. Four
`word lines W1 to W4, for example. are arranged inter-
`secting with the plurality of bit line pairs SBL and SEE,
`static type memory cells (referred to as SRAM memory
`cells hereinafter) 128 being provided at intersections
`thereof.
`'
`Each of the bit line pairs BL and El: is connected to
`the corresponding bit line pair SBL and $51: in the
`SRAM memory cell may 12 through the MOSFE’I‘s
`Q! and 02 in the corregfinding transfer gate 119. The
`bit line pairs SBL and
`in the SRAM memory cell
`array 12 is connected to 1/0 buses I/O and I70 through
`the MOSFETs Q3 and Q4 in the corresponding [/0
`switch 50, respectively.
`Additionally, block decoders 13a to 13:! are arranged
`corresponding to the blocks B] to B4 in the DRAM
`memory cell array 1. The block decoders 13a to 13d
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`apply common transfer signals to gates of the MOS-
`FETs and Q2 in the transfer gate 110 belonging to the
`corresponding blocks. respectively. In addition, each of
`the' column decoders 60 applies a column selecting sig-
`nal to gates of MOSFETs Q3 and Q4 in the correspond-
`ing I/O switch 50.
`In this DRAM device, when any of the block decod-
`ers 13a to 13:! applies a transfer signal to the transfer
`gates 110 belonging to' the corresponding block in re-
`spouse to the cache hit signal CH, data on one row in
`the corresponding block in the DRAM memory cell
`array 1 is transferred to the corresponding block in the
`SRAM memory cell array 12. On the other hand, when
`any'of the word lines W1 to W4 in the SRAM memory
`cell array 1 is selected and driven by the way decoder
`14 (FIG. 5). data stored in the SRAM memory cells 129
`connected to the word line are read out onto the cone-
`sponding bit line pairs SBL and sat. When a column
`selecting signal is applied from any of the column de-
`coders 60 to the correSponding l/O switch 50. the data
`read out onto the corresponding bit line pair__SEL and
`m is read out onto the I/O buses 1/0 and 1/0.
`In this DRAM device, data corresponding to one
`row in a plurality of columns are considered as one data
`block. A plurality of data blocks each on different rows
`are held in the plurality of SRAM memory cells 120. In
`addition, data blocks respectively on different rows in
`the same block are simultaneously held on the SRAM
`memory cell array 12 (associativity). Thus,
`if the
`SRAM memory cell array 12 is utilized as a cache mem.
`ory, the number of entries of data can be incrmd. As
`a result. a cache hit rate can be improved.
`Furthermore,
`if the word lines W1 to W4 in the
`SRAM memory cell array 12 are kept in an inactive
`state, a structure can be configured in which no transfer
`to the cache memory is made at the time of writing and
`reading operations to and from the DRAM memory
`cell array 1, so that the degree of freedom is increased in
`the application to the cache memory system.
`FIG. 7 is a block diagram showing a structure of .a
`simple cache system utilizing the DRAM device shown
`in FIG. 5. ,
`.
`In FIG. 7. a main memory 30 comprises lM byte
`which comprise 8 DRAM devices 31 each having
`1M x 1 organization. The cache system shown in FIG. 7
`is the same as the cache system shown in FIG. 3 except
`for the following. More specifically, the number of
`TAGs 25 is increased corresponding to the number of
`divisions of blocks in each of the DRAM devices 31 and
`the number of Word lines (the number of sets)-ia the '
`SRAM memory cell may 12. Since the DRAM mem-
`ory cell array