UNITED STATES PATENT AND TRADEMARK OFFICE
`______________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`______________________
`
`INTEL CORP., CAVIUM, INC., and
`WISTRON CORPORATION,
`Petitioner,
`
`v.
`
`ALACRITECH, INC.,
`Patent Owner.
`______________________
`
`Case IPR2017-013921
`U.S. Patent No. 7,337,241
`Title: FAST-PATH APPARATUS FOR RECEIVING DATA CORRESPONDING
`TO A TCP CONNECTION
`______________________
`
`DECLARATION OF ROBERT HORST IN SUPPORT OF PETITIONER’S
`REPLY TO PATENT OWNER’S RESPONSE TO PETITION FOR INTER
`PARTES REVIEW OF U.S. PATENT NO. 7,337,241
`
`Mail Stop “PATENT BOARD”
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`1 Cavium, Inc., which filed a Petition in Case IPR2017-01728, has been joined as a
`
`petitioner in this proceeding. Wistron Corporation, who filed a Petition in Case
`
`IPR2018-00328, has been joined as a petitioner in this proceeding.
`
`
`
`INTEL EX.1223.001
`
`
`______________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`______________________
`
`INTEL CORP., CAVIUM, INC., and
`WISTRON CORPORATION,
`Petitioner,
`
`v.
`
`ALACRITECH, INC.,
`Patent Owner.
`______________________
`
`Case IPR2017-013921
`U.S. Patent No. 7,337,241
`Title: FAST-PATH APPARATUS FOR RECEIVING DATA CORRESPONDING
`TO A TCP CONNECTION
`______________________
`
`DECLARATION OF ROBERT HORST IN SUPPORT OF PETITIONER’S
`REPLY TO PATENT OWNER’S RESPONSE TO PETITION FOR INTER
`PARTES REVIEW OF U.S. PATENT NO. 7,337,241
`
`Mail Stop “PATENT BOARD”
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`1 Cavium, Inc., which filed a Petition in Case IPR2017-01728, has been joined as a
`
`petitioner in this proceeding. Wistron Corporation, who filed a Petition in Case
`
`IPR2018-00328, has been joined as a petitioner in this proceeding.
`
`
`
`INTEL EX.1223.001
`
`
`
`U.S. Patent No. 7,337,241
`Ex. 1223 (“Horst Reply Decl.”)
`
`TABLE OF CONTENTS
`
`Page
`
`I.
`
`INTRODUCTION .......................................................................................... 2
`
`II. MATERIALS RELIED UPON IN FORMING MY OPINION ................ 5
`
`III. UNDERSTANDING OF THE GOVERNING LAW ................................. 5
`
`A.
`
`B.
`
`Invalidity by Anticipation ..................................................................... 6
`
`Invalidity by Obviousness ..................................................................... 6
`
`IV. LEVEL OF ORDINARY SKILL IN THE ART ......................................... 8
`
`V. ALTEON ......................................................................................................... 9
`
`A. Alteon was available prior to October 14, 1997 ................................... 9
`
`B.
`
`Alteon teaches the transfer of data without headers from the
`protocol stack ...................................................................................... 13
`
`VI. COMBINATION OF ERICKSON, TANENBAUM96, AND
`ALTEON ....................................................................................................... 14
`
`VII. COMBINATION OF ERICKSON AND TANENBAUM ........................... 16
`
`A.
`
`B.
`
`C.
`
`TCP/IP and UDP ................................................................................ 16
`
`Race conditions .................................................................................. 21
`
`Erickson’s Adapter ............................................................................ 22
`
`VIII. POLLING STATUS REGISTERS ................................................................ 24
`
`IX.
`
`INTERRUPTS IN THE ALLEGED PRIORITY APPLICATION ............... 25
`
`
`
`
`
`i
`
`INTEL EX.1223.002
`
`
`
`U.S. Patent No. 7,337,241
`Ex. 1223 (“Horst Reply Decl.”)
`
`I, Robert Horst, hereby declare as follows:
`
`I.
`
`INTRODUCTION
`1. My name is Robert Horst. I have been retained on behalf of Petitioner
`
`Intel Corporation (“Intel”) to provide this Declaration concerning technical subject
`
`matter relevant to the petition for inter partes review (“Petition”) concerning U.S.
`
`Patent No. 7,337,241 (Ex. 1001, the “241 Patent”). I reserve the right to
`
`supplement this Declaration in response to additional evidence that may come to
`
`light.
`
`2.
`
`I am over 18 years of age. I have personal knowledge of the facts
`
`stated in this Declaration and could testify competently to them if asked to do so.
`
`3.
`
`I am being compensated for my time at the rate of $550 per hour. My
`
`compensation is not based on the resolution of this matter. My findings are based
`
`on my education, experience, and background in the fields discussed below.
`
`4.
`
`I am an independent consultant with more than 30 years of expertise
`
`in the design and architecture of computer systems. My current curriculum vitae is
`
`submitted as Ex. 1236 and some highlights follow.
`
`5.
`
`Currently, I am an independent consultant at HT Consulting where my
`
`work includes consulting on technology and intellectual property. I also have an
`
`appointment as an adjunct research professor at the University of Illinois in the
`
`Department of Electrical and Computer Engineering. I have testified as an expert
`
`2
`
`INTEL EX.1223.003
`
`
`
`
`witness and consultant in patent and intellectual property litigation as well as inter
`
`U.S. Patent No. 7,337,241
`Ex. 1223 (“Horst Reply Decl.”)
`
`partes reviews and re-examination proceedings.
`
`6.
`
`I earned my M.S. (1978) in electrical engineering and Ph.D. (1991) in
`
`computer science from the University of Illinois at Urbana-Champaign after
`
`earning my B.S. (1975) in electrical engineering from Bradley University. During
`
`my master’s program, I designed, constructed, and debugged a shared memory
`
`parallel microprocessor system. During my doctoral program, I designed and
`
`simulated a massively parallel, multi-threaded task flow computer.
`
`7.
`
`After receiving my bachelor’s degree and while pursuing my master’s
`
`degree, I worked for Hewlett-Packard Co. While at Hewlett-Packard, I designed
`
`the micro-sequencer and cache of the HP3000 Series 64 processor. From 1980 to
`
`1999, I worked at Tandem Computers, which was acquired by Compaq Computers
`
`in 1997. While at Tandem, I was a designer and architect of several generations of
`
`fault-tolerant computer systems and was the principal architect of the NonStop
`
`Cyclone superscalar processor. The system development work at Tandem also
`
`included development of the ServerNet System Area Network and applications of
`
`this network to fault tolerant systems and clusters of database servers.
`
`8.
`
`Since leaving Compaq in 1999, I have worked with several
`
`technology companies, including 3Ware, Network Appliance, Tibion, and AlterG
`
`in the areas of network-attached storage and biomedical devices. From 2012 to
`
`3
`
`INTEL EX.1223.004
`
`
`
`
`2015, I was Chief Technology Officer of Robotics at AlterG, Inc., where I worked
`
`U.S. Patent No. 7,337,241
`Ex. 1223 (“Horst Reply Decl.”)
`
`on the design of anti-gravity treadmills and battery-powered orthotic devices to
`
`assist those with impaired mobility.
`
`9.
`
`In 2001, I was elected an IEEE Fellow “for contributions to the
`
`architecture and design of fault tolerant systems and networks.” I have authored
`
`over 30 publications, have worked with patent attorneys on numerous patent
`
`applications, and I am a named inventor on 82 issued U.S. patents.
`
`10. My patents include those directed to networks (e.g., U.S. Pat. No.
`
`6,157,967: Method of data communication flow control in a data processing
`
`system using busy/ready commands), storage (e.g., U.S. Pat. No. 6,549,977: Use of
`
`deferred write completion interrupts to increase the performance of disk
`
`operations), and multi-processor systems (e.g., U.S. Pat. No. 5,751,932: Fail-fast,
`
`fail-functional, fault-tolerant multiprocessor system). My publications include a
`
`conference paper that examined the performance and efficacy of protocol offload
`
`engines. Ex.1004.
`
`11. My current Curriculum Vitae, which is filed as Ex. 1236, contains
`
`further details on my education, experience, publications, and other qualifications
`
`to render this opinion as expert.
`
`4
`
`INTEL EX.1223.005
`
`
`
`
`II. MATERIALS RELIED UPON IN FORMING MY OPINION
`In addition to reviewing U.S. Patent No. 7,337,241 (Ex. 1001), I also
`12.
`
`U.S. Patent No. 7,337,241
`Ex. 1223 (“Horst Reply Decl.”)
`
`reviewed and considered the prosecution history of the 241 Patent (Ex. 1002). I
`
`also reviewed U.S. Pat. No. 5,768,618, to Erickson (Ex. 1005), A. Tanenbaum, 3rd
`
`ed. (1996) (Ex. 1006), and “Gigabit Ethernet Technical Brief: Achieving End-to-
`
`End Performance”, Alteon Networks, Inc. First Edition, Sept. 1996. (Ex. 1033). I
`
`also considered the background materials cited in my original declaration, Ex.
`
`1003.
`
`13.
`
`I also reviewed the Institution Decisions, Patent Owner’s Preliminary
`
`Response (and exhibits provided therewith), Patent Owner’s Corrected Response
`
`(and exhibits provided therewith), Dr. Almeroth’s declaration, and Dr. Almeroth’s
`
`deposition transcripts. In addition, I have reviewed Patent Owner’s Motion to
`
`Amend.
`
`14.
`
`I have also considered the additional background materials cited
`
`herein.
`
`III. UNDERSTANDING OF THE GOVERNING LAW
`I understand that a patent claim is invalid if it is anticipated or
`15.
`
`rendered obvious in view of the prior art. I further understand that invalidity of a
`
`patent claim requires that the claim be anticipated or obvious from the perspective
`
`of a person of ordinary skill in the relevant art at the time the invention was made.
`
`5
`
`INTEL EX.1223.006
`
`
`
`
`
`U.S. Patent No. 7,337,241
`Ex. 1223 (“Horst Reply Decl.”)
`
`A.
`16.
`
`Invalidity by Anticipation
`I have been informed that a patent claim is invalid as anticipated
`
`under 35 U.S.C. § 102 if each and every element of a claim, as properly construed,
`
`is found either explicitly or inherently in a single prior art reference.
`
`17.
`
`I have been informed that a claim is invalid under 35 U.S.C. § 102(a)
`
`if the claimed invention was patented or published anywhere, before the
`
`applicant’s invention. I further have been informed that a claim is invalid under 35
`
`U.S.C. § 102(b) if the invention was patented or published anywhere more than
`
`one year prior to the first effective filing date of the patent application (critical
`
`date). I further have been informed that a claim is invalid under 35 U.S.C. §
`
`102(e) if an invention described by that claim was disclosed in a U.S. patent
`
`granted on an application for a patent by another that was filed in the U.S. before
`
`the date of invention for such a claim.
`
`B.
`18.
`
`Invalidity by Obviousness
`I have been informed that a patent claim is invalid as obvious under
`
`35 U.S.C. § 103 if it would have been obvious to a person of ordinary skill in the
`
`art, taking into account (1) the scope and content of the prior art, (2) the differences
`
`between the prior art and the claims, (3) the level of ordinary skill in the art, and
`
`(4) any so called “secondary considerations” of non-obviousness, which include:
`
`(i) “long felt need” for the claimed invention, (ii) commercial success attributable
`
`6
`
`INTEL EX.1223.007
`
`
`
`
`to the claimed invention, (iii) unexpected results of the claimed invention, and (iv)
`
`U.S. Patent No. 7,337,241
`Ex. 1223 (“Horst Reply Decl.”)
`
`“copying” of the claimed invention by others. I further understand that it is
`
`improper to rely on hindsight in making the obviousness determination. I have
`
`been informed that Patent Owner claims a filing priority date no later than October
`
`14, 1997, for claims 1-24 of the 241 Patent. Accordingly, my analysis of the prior
`
`art for the claims of the 241 Patent is based on the prior art and knowledge of a
`
`person having ordinary skill in the art (“POSA”) as of October 14, 1997.
`
`19.
`
`I have been informed that a claim can be obvious in light of a single
`
`prior art reference or multiple prior art references. I further understand that
`
`exemplary rationales that may support a conclusion of obviousness include:
`
`(A) Combining prior art elements according to known methods to
`yield predictable results;
`
`(B) Simple substitution of one known element for another to obtain
`predictable results;
`
`(C) Use of known technique to improve similar devices (methods, or
`products) in the same way;
`
`(D) Applying a known technique to a known device (method, or
`product) ready for improvement to yield predictable results;
`
`(E) “Obvious to try” - choosing from a finite number of identified,
`predictable solutions, with a reasonable expectation of success;
`
`(F) Known work in one field of endeavor may prompt variations of it
`for use in either the same field or a different one based on design
`
`7
`
`INTEL EX.1223.008
`
`
`
`
`
`U.S. Patent No. 7,337,241
`Ex. 1223 (“Horst Reply Decl.”)
`
`incentives or other market forces if the variations are predictable to
`one of ordinary skill in the art;
`
`(G) Some teaching, suggestion, or motivation in the prior art that
`would have led one of ordinary skill to modify the prior art reference
`or to combine prior art reference teachings to arrive at the claimed
`invention.
`
`IV. LEVEL OF ORDINARY SKILL IN THE ART
`20. The definition of a POSA is set forth in my prior declaration.
`
`Ex. 1003, ¶¶ 18-20. While it would be rare to find all of these skills in a single
`
`individual, it is my opinion that a POSA is a person with at least the equivalent of a
`
`B.S. degree in computer science, computer engineering or electrical engineering
`
`with at least five years of industry experience including experience in computer
`
`architecture, network design, network protocols, software development, and
`
`hardware development. Ex. 1003, ¶ 19.
`
`21.
`
`I understand that Patent Owner contends that a POSA would be a
`
`person with a Bachelor’s degree in computer science, computer engineering, or the
`
`equivalent, and several years’ experience in the fields of computer networking
`
`and/or networking protocols. Paper No. 34 at 8. While I disagree with this
`
`proposed level of ordinary skill, my opinions in this declaration would remain the
`
`same even if Patent Owner’s opinion concerning the level of ordinary skill in the
`
`art were applied.
`
`8
`
`INTEL EX.1223.009
`
`
`
`U.S. Patent No. 7,337,241
`Ex. 1223 (“Horst Reply Decl.”)
`
`22. The statements that I make in this declaration when I refer to a POSA
`
`
`
`are from the perspective of October 14, 1997.
`
`V. ALTEON
`A. Alteon was available prior to October 14, 1997
`23. The Internet Archive shows that Alteon was available through a series
`
`of links from the Alteon.com home page at least by June 22, 1997, which is still
`
`months before the earliest possible priority date of the 241 Patent.
`
`24. The Internet Archive (available at archive.org) was a known resource
`
`in 1997. Ex. 1243 (indicating the founding of the Internet Archive in 1996).
`
`Further, like the Internet Archive, search engines also use crawlers to index web
`
`pages for searching. If a crawler for the Internet Archive was able to access
`
`Alteon, then I would expect that a crawler for a search engine available at the time
`
`would also be able to access the Alteon reference. A POSA in the field of
`
`computer networking would certainly have relied on search engines in 1997 to
`
`locate relevant art.
`
`25. Search engines were available at the time of the alleged invention and
`
`a POSA would have known how to use and access them. Popular search engines
`
`available before 1997 included Webcrawler (1994), Lycos (1994), Infoseek (1995),
`
`AltaVista (1995), and Inktomi (1996). Ex. 1244 and Ex. 1245. A POSA in 1997
`
`9
`
`INTEL EX.1223.010
`
`
`
`
`would have known how to use and access information indexed by Altavista or one
`
`U.S. Patent No. 7,337,241
`Ex. 1223 (“Horst Reply Decl.”)
`
`of the other available search engines.
`
`26.
`
`I discussed the availability of Alteon in my declaration in support of
`
`Petitioner’s Opposition to the Patent Owner’s Motion to Amend, which is
`
`incorporated below:
`
`Alteon Networks and its website were well known to those interested
`in the relevant art. See, e.g. Ex. 1219 at .005 (August 26, 1996
`Infoworld Article, “Budding Alteon to Offer Gigabit Ethernet
`Switch”) and Ex. 1220 at .006 (May 12, 1997 Infoworld Article,
`“IBM, Alteon strike Gigabit Ethernet Deal”).
`
`I have compared Exhibit A of the First Affidavit of Christopher Butler
`(Ex. 1087.005-.030) with Ex. 1033 (“Alteon”) and find that these are
`the same document.
`
`I have compared Exhibit A pages 7-31 of the Second Affidavit of
`Christopher Butler (Ex. 1215.009-033) with Alteon and find that these
`are the same document.
`
`I have compared the documents cited in U.S. Patent Nos. 7,124,205,
`8,131,880, 7,337,241, 7,237,036, 7,673,072, 9,055,104, and 8,805,948
`identified as “Gigabit Ethernet Technical Brief, Achieving End-to-
`End Performance. Alteon Networks, Inc., First Edition, Sep. 1996”
`with Ex. 1033 (“Alteon”) and find that they are the same document.
`
`I have also reviewed Ex. 1221 which was identified by Patent Owner
`in the 241 Patent as “Internet pages directed to Technical Brief on
`Alteon Ethernet Gigabit NIC technology, www.alteon.com, 14 pages,
`10
`
`INTEL EX.1223.011
`
`
`
`
`
`U.S. Patent No. 7,337,241
`Ex. 1223 (“Horst Reply Decl.”)
`
`printed Mar. 15, 1997.” (emphasis added). While this is not the same
`document as Alteon, it is from the same website (Alteon.com) and
`contains much of the same text and figures as Alteon that I cite and
`reference in Appendix A below and ¶ 14 above.
`
`As I explain below, the archive.org website and Second Affidavit of
`Christopher Butler show that Ex. 1033 was readily accessible from the
`alteon.com home page in the prior art time frame.
`
`Ex. 1201 is a true and correct copy of the following website as of
`December 27, 2017: https://web.archive.org/web/19970622102719/
`http://www.alteon.com/index.html. This is an archived version of the
`Alteon home page. On this webpage, there is a link to a page
`identified as “press room.” That link leads to another website
`Ex. 1202 described below.
`
`I have compared Ex. 1201 to Ex. A page 2 of the Second Affidavit of
`Christopher Butler (Ex. [2015].004 [sic]) and find that these are the
`same document.
`
`Ex. 1202 is a true and correct copy of the following website as of
`December 27, 2017: https://web.archive.org/web/19970622102647/
`http://www.alteon.com:80/presintr.html. On this webpage, there is a
`link to a page identified as “technical brief.” That link leads to a
`website Ex. 1203 described below.
`
`I have compared Ex. 1202 to Ex. A page 3 of the Second Affidavit of
`Christopher Butler (Ex. 2015.005) and find that these are the same
`document.
`
`11
`
`INTEL EX.1223.012
`
`
`
`
`
`U.S. Patent No. 7,337,241
`Ex. 1223 (“Horst Reply Decl.”)
`
`Ex. 1203 is a true and correct copy of the following website as of
`December 27, 2017: https://web.archive.org/web/19970622102901/
`http://www.alteon.com:80/techbr01.html. On this webpage, there is a
`link to a page identified as “click here to DOWNLOAD the Technical
`Brief in PDF format.” That link leads to a website Ex. 1204 described
`below.
`
`I have compared Ex. 1203 to Ex. A pages 4-5 of the Second Affidavit
`of Christopher Butler (Ex. 2015.006-7) and find that these are the
`same document.
`
`Ex. 1204 is a true and correct copy of the document available at
`following website as of December 27, 2017: https://web.archive.org/
`web/19970622103538/http://www.alteon.com:80/whitpapr.pdf.
`Ex. 1204 is a true and correct copy of Ex. 1033 (“Alteon”).
`
`I have compared Ex. 1204 to Ex. A pages 7-31 of the Second
`Affidavit of Christopher Butler (Ex. 1215.009-.033) and find that
`these are the same document.
`
`Based on the First Affidavit of Christopher Butler (Ex. 1087), the
`URLs for Exs. 1201-1204 indicate that they are records of the Internet
`Archive archived on June 22, 1997. Id. at ¶ 5.
`
`Ex. 1210, ¶¶ 15-29.
`
`27. As explained in my prior declaration, Alacritech cited to both a
`
`“Technical Brief” printed from Alteon website which Alacritech admits it printed
`
`on March 15, 1997 (Ex. 1221) and Alteon (Ex. 1033) during the prosecution of the
`
`241 Patent. See Ex. 1001.003 (citing both Alteon and Ex. 1221). Ex. 1221 is
`
`12
`
`INTEL EX.1223.013
`
`
`
`
`almost identical to the second half of the Alteon paper. Every portion of Alteon
`
`U.S. Patent No. 7,337,241
`Ex. 1223 (“Horst Reply Decl.”)
`
`that I cited to in my original declaration is included in Ex. 1221. In order to
`
`illustrate the similarity between Alteon and Ex. 1221, Ex. 1239 shows Alteon with
`
`the corresponding portions of Ex. 1221 side-by-side.
`
`28. Alteon was one of only a few known developers of Gigabit
`
`networking technology in 1997. A POSA would have been motivated to look to
`
`documentation provided by Alteon as a reference. Several large corporations had
`
`partnered with Alteon to promote its Gigabit Ethernet Network Interface Card.
`
`Alteon and Network Appliance demonstrated access to a NetApp F540 filer
`
`equipped with an Alteon PCI-bus Gigabit Ethernet Network Interface Card
`
`(NIC) at Networld+Interop in 1996: Ex. 1246. Also, Alteon and Sun
`
`Microsystems partnered to deliver Gigabit Ethernet products and demonstrated
`
`these at Networld+Interop in May 1997. Ex. 1247.
`
`B. Alteon teaches the transfer of data without headers from the
`protocol stack
`29. As I provided in my original declaration, Alteon discusses and
`
`clarifies that the protocol stack moves the data minus the header (i.e., Ethernet, IP,
`
`and TCP headers) to the application memory. Ex. 1003 at A-14. As I also
`
`discussed in my original declaration, in the combination of Erickson in view of
`
`Tanenbaum and Alteon, a “POSA would therefore be motivated to use the
`
`Tanenbaum96 teaching to improve Erickson’s fast path receiving processing by
`13
`
`INTEL EX.1223.014
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`
`
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`including TCP.” Ex. 1003, ¶ 167. In other words, the relevant portion of the
`
`U.S. Patent No. 7,337,241
`Ex. 1223 (“Horst Reply Decl.”)
`
`protocol stack in the prior art combination would reside in the network interface
`
`device. Thus, Alteon’s clarification of the protocol stack moving data into the
`
`application memory (on the host) teaches the sending of the data from each packet
`
`to application memory without any of the Ethernet, IP, or TCP headers.
`
`VI. COMBINATION OF ERICKSON, TANENBAUM96, AND ALTEON
`30. Dr. Almeroth argues that “while Erickson does describe a template
`
`header, the network layer and transport layer are not prepended ‘at one time,’ but
`
`rather serially in a traditional fashion.” Ex. 2026, ¶ 138. I disagree with Dr.
`
`Almeroth’s opinion. There is no disclosure in Erickson that the headers might be
`
`prepended at separate times as part of the combination process. As the Board has
`
`already found, Erickson discloses the filling in of a template to create a
`
`UDP/IP/MAC header. “[T]he header and data to be transmitted, both stored in the
`
`memory of the network interface device, would be combined in one of two obvious
`
`manners—either the header is prepending to the data or the data is appended to the
`
`header.” Paper 11 at 17-18. Under Dr. Almeroth’s theory of Erickson, “[w]hen
`
`building a packet for transmission, Erickson [] appears to first prepends the
`
`Ethernet header 704 to the user data, then prepends the IP header 706 to the
`
`Ethernet header, and finally prepends the UDP header 708 to the IP header.” Ex.
`
`2026, ¶ 134. However, this cannot be correct. If the Ethernet header was
`
`14
`
`INTEL EX.1223.015
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`
`
`prepended first, followed by the IP header and then the UDP header, the headers
`
`U.S. Patent No. 7,337,241
`Ex. 1223 (“Horst Reply Decl.”)
`
`would be backwards. Ex. 1005 at Fig. 6.
`
`31. Even if one were to assume that Erickson disclosed prepending of
`
`headers serially (UDP then IP then Ethernet), it would have been obvious to
`
`modify Erickson to prepend the headers at one time given the template structure
`
`used. It would have been a simple design choice to complete the transport layer, IP
`
`and Ethernet headers with the header template before copying the user data rather
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`than after.
`
`32. Dr. Almeroth also argues that the combination of Erickson and Alteon
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`(or Erickson, Alteon, and Tanenbaum96) does not disclose processing MAC layer
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`headers without an interrupt dividing the processing. Ex. 2026, ¶ 120. I disagree
`
`with this opinion. As explained above, the templates of Erickson explicitly include
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`a MAC header along with the IP and transport layer headers. Ex. 1005 at Figs. 6
`
`and 7. I understand that the Board found “all processing to generate headers for
`
`packets to be sent from the network interface device of Erickson is performed by
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`the processing capability of Erickson’s network interface device with no reason to
`
`interrupt the processing of the host computer requesting the transmission.” Paper
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`11 at 19. I agree with the Board’s understanding and confirm that it applies to the
`
`receive side as well. When either receiving or sending packets, the processing of
`
`15
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`INTEL EX.1223.016
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`
`
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`headers is performed by Erickson’s network interface device and there is no reason
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`U.S. Patent No. 7,337,241
`Ex. 1223 (“Horst Reply Decl.”)
`
`to interrupt the processing of the host computer during the header processing.
`
`VII. COMBINATION OF ERICKSON AND TANENBAUM
`A. TCP/IP and UDP
`33. Dr. Almeroth argues that “Erickson only provides a working example
`
`of a UDP script,” and that the combination of Erickson and Tanenbaum96 “would
`
`not enable a POSA to make or use a TCP implementation.” Ex. 2026, ¶ 144. I
`
`disagree with Dr. Almeroth’s opinions.
`
`34. As I discussed, in my original declaration, Erickson states that its
`
`network adapter can be used with TCP scripts and cites to Tanenbaum for
`
`information about TCP sockets and packets. See e.g., Ex. 1003, ¶¶ 139, A-3. Also
`
`as I discussed in my original declaration, Tanenbaum96 describes both TCP and
`
`UDP transport protocols. Ex. 1003, ¶ 142. Furthermore, as I explained in my
`
`original declaration, a POSA would have understood TCP/IP well and would have
`
`understood how to adapt Erickson’s UDP scripts to TCP. Ex. 1003, ¶ 161-168.
`
`35. The well-known textbook, Stevens1 (TCP/IP Illustrated Volume 1)
`
`explains that the TCP/IP protocol suite includes several protocols including UDP.
`
`Ex. 1008. “The TCP/IP protocol suite is a combination of many protocols.
`
`Although the commonly used name for the entire protocol suite is TCP/IP, TCP
`
`16
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`INTEL EX.1223.017
`
`
`
`
`and IP are only two of the protocols.” Ex. 1008 at .028. As shown in the following
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`U.S. Patent No. 7,337,241
`Ex. 1223 (“Horst Reply Decl.”)
`
`figure, UDP is part of the TCP/IP protocol suite protocols.
`
`(Ex. 1008.030).
`
`36. The sample code in both Stevens1 and Ex. 1013 (“Stevens2”) includes
`
`C code for both TCP and UDP. These examples show that UDP was included in
`
`standard Unix releases. “Figure 1.10 shows a chronology of the various BSD
`
`
`
`17
`
`INTEL EX.1223.018
`
`
`
`
`releases, indicating the important TCP/IP features. The BSD Networking Releases
`
`U.S. Patent No. 7,337,241
`Ex. 1223 (“Horst Reply Decl.”)
`
`shown on the left side are publically available source code releases containing all
`
`of the networking code: both the protocols themselves and many of the
`
`applications and utilities (such as Telnet and FTP).” Ex. 1008.040. (emphasis
`
`added).
`
`18
`
`
`
`INTEL EX.1223.019
`
`
`
`
`(Ex. 1008.041)
`
`U.S. Patent No. 7,337,241
`Ex. 1223 (“Horst Reply Decl.”)
`
`37. Furthermore, Stevens2, (TCP/IP Illustrated Volume 2), includes C
`
`code for both UDP as well as TCP. Ex. 1013. Chapter 23 of Stevens2 is
`
`completely devoted to UDP including explanations and code examples. Stevens2
`
`includes extensive discussions of the Berkeley networking source code.
`
`38. A number of higher level protocols are designed so that their
`
`application interfaces can run on top of either UDP or TCP.
`
`39. The Berkeley Sockets implementation is an example of a protocol that
`
`was written to run either on UDP or TCP. Ex. 1242.2 The same programming
`
`interface could be used for reliable communications over TCP or for datagram
`
`service over UDP. Id.
`
`There are several socket types, which represent classes of services.
`Each type may or may not be implemented in any communication
`domain. If a type is implemented in a given domain, it may be
`implemented by one or more protocols, which may be selected by the
`user.
`
`
`2 John S. Quarterman, Abraham Silberschatz, and James L. Peterson. 1985.
`
`4.2BSD and 4.3BSD as examples of the UNIX system. ACM Comput. Surv. 17, 4
`
`(December 1985), 379-418.
`
`19
`
`INTEL EX.1223.020
`
`
`
`
`
`U.S. Patent No. 7,337,241
`Ex. 1223 (“Horst Reply Decl.”)
`
`• SOCK-STREAM. Stream sockets provide
`reliable duplex
`sequenced data streams. No data are lost or duplicated in delivery,
`and there are no record boundaries. This type is supported in the
`Internet domain by the TCP protocol. In the UNIX domain, pipes
`are implemented as a pair of communicating stream sockets. …
`
`• SOCK-DGRAM. Datagram sockets transfer messages of variable
`size in either direction. There is no guarantee that such messages
`will arrive in the same order in which they were sent, or that they
`will be unduplicated, or that they will arrive at all, but the original
`message (record) size is preserved in any datagram that does
`arrive. This type is supported in the Internet domain by the UDP
`protocol.
`
`Ex. 1242 at .030.
`
`40. NFS (network file system) is an example of a protocol that was
`
`written to run either on UDP or TCP. “NFS was originally written to use UDP,
`
`and that’s what all vendors provide. Newer implementations, however, also
`
`support TCP.” Ex. 1008.497.
`
`41. SNMP (Simple Network Management Protocol) is another protocol
`
`that has been written to run over UDP and TCP. “For example, one application of
`
`network management is to poll nodes to determine if they are up or not. When a
`
`node is up, it makes little difference whether SNMP operates over TCP or UDP.”
`
`Ex. 1240.008.
`
`20
`
`INTEL EX.1223.021
`
`
`
`U.S. Patent No. 7,337,241
`Ex. 1223 (“Horst Reply Decl.”)
`
`42. Remote Procedure Call implementations have also been written to run
`
`
`
`over UDP and TCP. “Sun RPC comes in two flavors. One version is built using
`
`the sockets API and works with TCP and UDP.” Ex. 1008.487.
`
`B. Race conditions
`43. Dr. Almeroth expresses the opinion that “Tanenbaum cites to the
`
`‘race’ conditions created by offloading ‘elaborate protocols,’ but offers no solution
`
`to this problem.” Ex. 2026, ¶ 128. The race conditions discussed in Tanenbaum96
`
`at Ex.1006.589 are the well-known need to synchronize processors in a
`
`multiprocessor system and is typically solved by including locking primitives to
`
`provide a way to give exclusive access to resources. This problem is necessarily
`
`solved in every functioning multiprocessor system including those that predated
`
`the Patent Owner patents by decades. When addressing this problem, a POSA
`
`would consider the design and purpose of the system or product and incorporate
`
`the appropriate well-known design techniques.
`
`44. Solutions to the multiprocessor synchronization are described in many
`
`references including Hennessey and Patterson 1990.
`
`One of the major requirements of a shared-memory multiprocessor is
`being able to coordinate processes that are working on a common
`task. Typically, a programmer will use lock variables to synchronize
`the processes. The difficulty for the architect of a multiprocessor is to
`provide a mechanism to decide which processor gets the lock and to
`
`21
`
`INTEL EX.1223.022
`
`
`
`
`
`U.S. Patent No. 7,337,241
`Ex. 1223 (“Horst Reply Decl.”)
`
`provide the operation that locks a variable. Arbitration is easy for
`shared-bus multiprocessors, since the bus is the only path to memory:
`The processor that gets the bus locks out all other processors from
`memory. If the CPU and bus provide an atomic swap operation,
`programmers can create locks with the proper semantics.
`
`Ex. 1035.503.
`
`45. Thus, a POSA reading Tanenbaum96 would have understood that the
`
`TCP fast path could be offloaded to that second “slower” CPU. Ex. 2028 at
`
`135:17-234, 139:18-25
`
`C. Erickson’s Adapter
`46. Dr. Almeroth expresses the opinion that “Erickson’s I/O device
`
`adapter has inherent memory and processing limitations.” Ex. 2026, ¶ 94. I
`
`disagree with his opinion. Erickson discloses that one embodiment may have
`
`particular limitations. “In all likelihood, the adapter would have a very limited
`
`knowledge of the user process’ virtual address space, probably only knowing how
`
`to map virtual-to-physical for a very limited range, maybe as small as a single
`
`page.” Ex. 1005 at 8:16-20. I understand that prior art is not limited to specific
`
`embodiments in the specification. However, even if Erickson was limited to a
`
`single page, TCP segments are often smaller than a page. For example, in Ethernet
`
`which is the most common media, TCP segments are typically about 1500 bytes,
`
`which is smaller than a typical page size of 4K bytes. Thus, a POSA could have
`
`22
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`INTEL EX.1223.023
`
`
`
`
`implemented a TCP embodiment without making changes to the Erickson
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`U.S. Patent No. 7,337,241
`Ex. 1223 (“Horst Reply Decl.”)
`
`adapter’s ability to cross page boundaries.
`
`47. Erickson also suggests the possibility of mapping multiple pages.
`
`This would merely require multiple calls
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