a2, United States Patent
`US 6,334,153 B2
`(10) Patent No.:
`Boucheretal.
`(45) Date of Patent:
`*Dec. 25, 2001
`
`
`US006334153B2
`
`(75)
`
`(54) PASSING A COMMUNICATION CONTROL
`BLOCK FROM HOST TO A LOCAL DEVICE
`SUCH THAT A MESSAGEIS PROCESSED
`ON THE DEVICE
`Inventors: Laurence B. Boucher, Saratoga;
`Stephen E. J. Blightman, San Jose;
`Peter K. Craft, San Francisco; David
`A. Higgen, Saratoga; Clive M.
`Philbrick, San Jose; Daryl D. Starr,
`Milpitas, all of CA (US)
`(73) Assignee: Alacritech, Inc., San Jose, CA (US)
`.
`*
`a
`.
`.
`.
`(*) Notice:
`Subjectto any disclaimer, the term of this
`patent is extended or adjusted under 35
`US.C. 154(b) by 0 days.
`
`es patent is subject to a terminal dis-
`Cranmer.
`
`(21) Appl. No.: 09/748,936
`
`(22)
`
`Filed:
`
`Dec. 26, 2000
`
`Related U.S. Application Data
`
`5,163,131
`5,212,778
`5,280,477
`
`11/1992 Row et al. wee 395/200
`.. 395/400
`5/1993 Dally et al.
`...
`
`1/1994 Trapp .oeecccecesceeecseeeeeeee 370/85.1
`(List continued on next page.)
`FOREIGN PATENT DOCUMENTS
`PCT?st.nl
`11/1998 (EP)
`WO98/19412
`5/1998 (WO).
`WO98/50852
`11/1998 (WO).
`W099/04343
`1/1999 (WO).
`OTHER PUBLICATIONS
`Internet pages entitled: DART Fast Application—Level Net-
`working Via Data-Copy Avoidance, by Robert J. Walsh,
`printed Jun. 3, 1999.
`(List continued on next page.)
`Primary Examiner—Zarni Maung
`(74) Attorney, Agent, or Firm—Mark Lauer; T. Lester
`Wallace
`
`(57)
`
`ABSTRACT
`
`Asystem for protocol processing in a computer network has
`an intelligent network interface card (INIC) or communica-
`tion processing device (CPD) associated with a host com-
`puter. The INIC provides a fast-path that avoids protocol
`(63) Continuation of application No. 00/489.603; filed on Nov.
`:
`-
`12, 1999, now Pat. No. 6,247,060, which
`is a continuation
`angenNeOseon apesr now GSNfoemostIngemul-pasktmeseseal
`Provisional application No. 60/061,809, filed on Oct. 14,
`host for those message packets that are chosen for process-
`1997,
`ing by host software layers. A communication control block
`for a message is defined that allows DMAcontrollers of the
`INIC to move data, free of headers, directly to or from a
`destination or source in the host. The context is stored in the
`INIC as a communication control block (CCB)that can be
`passed back to the host for message processing by the host.
`The INIC contains specialized hardware circuits that are
`much faster at their specific tasks than a general purpose
`CPU. A preferred embodiment includes a trio of pipelined
`processors with separate processors devoted to transmit,
`receive and management processing, with full duplex com-
`munication for four fast Ethernet nodes.
`
`(60)
`
`(SL) Unt. C1 eeecceeeeees GO6F 15/16; GO6F 15/173
`(52) U.S. Ch. cece 709/230; 709/250; 709/238
`(58) Field of Search ...cccccsssscsssesenee 709/250, 230,
`709/236, 238, 243 28 345
`,
`,
`,
`,
`
`(56)
`
`References Cited
`
`4,336,538
`4.991.133
`5,056,058
`5,097,442
`
`U.S. PATENT DOCUMENTS
`12/1992 Johnson et al
`364/200
`2/1991 Daviset al.
`....
`
`10/1991 Hirata et al. we eee eeeee 364/900
`3/1992 Ward et al. vc eeeeeeeeeeeenee 365/78
`
`2 Claims, 82 Drawing Sheets
`
`
`
`INTEL Ex. 1259.001
`
`INTEL Ex. 1259.001
`
`

`

`US 6,334,153 B2
`Page 2
`
`U.S. PATENT DOCUMENTS
`
`
`
`Jato Technologies Internet pages entitled: Network Accel-
`erator Chip Architecture, twelve—slide presentation, printed
`Aug. 19, 1998.
`EETIMESarticle entitled: Enterprise System Uses Flexible
`Spec, by Christopher Harrer and Pauline Shulman, dated
`Aug. 10, 1998, Issue 1020, printed Nov. 25, 1998.
`Internet pages entitled: iReady About Us and iReady Prod-
`ucts, printed Nov. 25, 1998.
`Internet pages entitled: Smart Ethernet Network Interface
`Card, with Berend Ozceri is developing, printed Nov. 25,
`1998.
`
`2/1994 Latif et ab. wee ceeteeee 395/275
`5,289,580
`
`4/1994 Yokoyamaetal. .
`. 395/200
`5,303,344
`5/1995 Hausmanetal. ...
`.. 395/250
`5,412,782
`
`9/1995 Richter et al. oe 370/94.1
`5,448,566
`. 395/200.12
`1/1996 Hitz et al.
`...
`5,485,579
`
`4/1996 Batd oo. eeeccceecseseeseneeeceeseeeee 395/250
`5,506,966
`4/1996 Suda ............
`.. 395/280
`5,511,169
`...
`8/1996 Young et al.
`. 395/280
`5,548,730
`
`10/1996 Bakkeet al. ole
`eeeeeeee 370/60
`5,566,170
`. 395/200.15
`12/1996 Reddin et al.
`..
`5,588,121
`
`12/1996 Senoet al. oe eeeeeee 395/675
`5,590,328
`
`1/1997 Isfeld etal. .....
`. 395/200.02
`5,592,622
`Internet pages entitled : Hardware Assisted Protocol Pro-
`
`5/1997 Delp et al. wees 370/411
`5,629,933
`cessing, which Eugene Feinberg is working on, printed Nov.
`5/1997 Andrewsetal.
`. 395/200.07
`5,634,099
`
`25, 1998.
`5/1997 Cloud et al. oe
`eeeeee 395/680
`5,634,127
`Internet pages of XaQti Corporation entitled: Giga Power
`.. 395/200.2
`6/1997 Pardillos .........
`5,642,482
`
`Protocol Processor Product Preview, printed Nov. 25, 1998.
`9/1997 Krech, Jr. et al. ve. 395/200.64
`5,664,114
`Internet pages of Xpoint Technologies www.xpoint.com
`9/1997 Collins oo. eetencteceeeee 395/200.2
`5,671,355
`web site (5 pages), printed Dec. 19, 1997.
`10/1997 Yakoyamaetal.
`oo... 709/212
`5,678,060
`11/1997 Shobu et al. oo. 395/200.12
`5,692,130
`Internet pages relating to iReady Corporation and the iReady
`12/1997 Sartore et al.
`..
`. 395/230.06
`5,699,317
`Internet Tuner Module, printed Nov. 2, 1998.
`5,701,434=12/1997 Nakagawa... cece 395/484
`Internet pages entitled: Asante and 10OBASE-T Fast Eth-
`5,749,095
`5/1998 Hagersten .... cece cece 711/141
`ernet, printed May 27, 1997.
`5,751,715
`5/1998 Chan et al.
`.
`. 370/455
`
`Internet pages entitled: A Guide to the Paragon XP/S—A7
`5,752,078
`5/1998 Delp et ab. wees 395/827
`5/1998 Silverstein et al... 395/200.58
`5,758,084
`Supercomputerat Indiana University, printed Dec. 21, 1998.
`
`5/1998 Gentry et al. ou. 395/200.64
`5,758,089
`
`60/053,240 (U.S. Provisional Application), by Jolitz et al.
`oe 395/831
`5,758,186
`5/1998 Hamilton et al.
`(listed filing date Jul. 18, 1997).
`5/1998 Kuzma oo. cseeeeceeceeeneee 395/886
`5,758,194
`
`Zilog Product Brief entitled “Z85C30 CMOS SCCSerial
`. 395/188.01
`5,771,349
`6/1998 Picazo Jr., et al
`
`Communication Controller’, Zilog Inc., 3 pages (1997).
`8/1998 Osborne 0. eeeeeeeees 395/200.75
`5,790,804
`
`Richard Stevens, “TCP/IP Illustrated, vol. 1, The Protocols”,
`8/1998 Hansen et al. oe 395/800.01
`5,794,061
`
`pp. 325-326 (1994).
`9/1998) McAlpice occ
`cee 711/149
`5,802,580
`
`. 395/200.43
`9/1998 Van Seters etal.
`5,812,775
`Andrew Tanenbaum, “Computer Networks”, Third Edition,
`
`9/1998 Purcell et al. ce
`eee 395/163
`5,815,646
`ISBN 0-13-349945-6, entire book (1996).
`
`3/1999 Bilanskyetal. ....
`. 395/200.57
`5,878,225
`Internet pages entitled: Northridge/Southbridge vs.
`7/1999 Mendelsonetal.
`5,930,830
`« TU/L71L
`
`Hub Architecture, 4 pages, printed Feb. 19, 2001.
`11/1999 Radognaetal.....
`5,991,299
`« 370/392
`Gigabit Ethernet Technical Brief, Achieving End-to-End
`6,009,478
`12/1999 Panneret al.
`oe.
`eeeeneeeceee 710/5
`6,034,963
`3/2000 Minamietal. .
`. 370/401
`Performance. Alteon Networks, Inc., First Edition, Sept.
`1996.
`6,061,368
`5/2000 Hitzelberger wee 370/537
`6,247,060 *
`6/2001 Boucheret al. oe 709/238
`OTHER PUBLICATIONS
`
`
`
`
`
`Intel
`
`Internet pages of InterProphet entitled: Frequently Asked
`Questions, by Lynne Jolitz, printed Jun. 14, 1999.
`Internet pages entitled: Technical White Paper—Xpoints
`Disk-to-—LAN Acceleration Solution for Windows NT
`
`VT8501 Apollo MVP4 Documentation, VIA Technologies,
`Inc., pp. i-iv, 1-11, cover and copyright page, revision 1.3
`(Feb. 1, 2000).
`Internet pages directed to; Technical Brief on Alteon Eth-
`ernet Gigabit NIC technology, www.alteon.com, 14 pages,
`printed Mar. 15, 1997.
`
`Server, printed Jun. 5, 1997.
`
`* cited by examiner
`
`INTEL Ex. 1259.002
`
`INTEL Ex. 1259.002
`
`

`

`U.S. Patent
`
`Dee. 25, 2001
`
`Sheet 1 of 82
`
`US 6,334,153 B2
`
`
`
`UPPER
`LAYER
`
`35
`
`
`
`
`
`
`
` 0
`
`CONTEXT
`
`UPPER LAYER
`INTERFACE
`
`TRANSPORT
`
`NETWORK
`
`STORAGE
`
`INTEL Ex. 1259.003
`
`INTEL Ex. 1259.003
`
`

`

`U.S. Patent
`
`Dee. 25, 2001
`
`Sheet 2 of 82
`
`US 6,334,153 B2
`
`RECEIVE PACKET
`FROM NETWORK
`BY CPD
`
`47
`
`VALIDATE PACKET,
`
`52
`HEADERS
`
`59
`
`No_|SENDPACKET TO
`
`FAST PATH
`STACK FOR SLOW-
`CANDIDATE?
`PATH PROCESSING
`
`
`61
`
`YES
`
`67
`
`53
`
`65
`
`
`CACHE
`MATCH
`Wen ccR?
`CCB IN
`STACK FOR SLOW-
`
`CPD
`
`NO
`
`SEND PACKET TO
`
`PATH PROCESSING
`
`
`
`SEND TO
`
`
`DESTINATION
`CREATE CCB
`IN HOST VIA
`FOR MESSAGE
`
`FAST-PATH
`
`
`
`51
`
`FIG. 3
`
`INTEL Ex. 1259.004
`
`INTEL Ex. 1259.004
`
`

`

`U.S. Patent
`
`Dee. 25, 2001
`
`Sheet 3 of 82
`
`US 6,334,153 B2
`
`INTEL Ex. 1259.005
`
`INTEL Ex. 1259.005
`
`

`

`U.S. Patent
`
`Dee. 25, 2001
`
`Sheet 4 of 82
`
`US 6,334,153 B2
`
`
`
`164
`
`162
`
`NETWORK
`
`
`168
`
`APPLICATION ||
`
`166
`TRANSPORT
`||
`
`
`
`
`|
` 170
`DATA LINK_|
`
`171
`
`SLOW-PATH
`
`
`
`INTEL Ex. 1259.006
`
`INTEL Ex. 1259.006
`
`

`

`U.S. Patent
`
`Dec. 25, 2001
`
`Sheet 5 of 82
`
`US 6,334,153 B2
`
`MEDIA ACCESS
`CONTROLLER
`
`ASSEMBLY
`REGISTER
`
`FLY BY
`PACKET
`SEQUENCER
`CONTROL
`
`
`
`MULTIPLEXOR
`
`SEQUENCER
`
`
`
` 182
`
`186
`
` UE®F
`
`SRAM
`CONTROL
`
`DRAM CONTROL
`
`188
`
`MANAGER
`
`FIG. 7
`
`INTEL Ex. 1259.007
`
`INTEL Ex. 1259.007
`
`

`

`U.S. Patent
`
`Dee. 25, 2001
`
`Sheet 6 of 82
`
`US 6,334,153 B2
`
`176
`
`PACKET
`
`
`
`174
`
`
`
`
`
`
`
`
`CONTROL
`eee
`SEQUENCER
`
`
`
` MACJTNETWORK
`
`
`178
`TRANSPORTTeSESSION
`
`
`
`SEQUENCER
`
`
`
`
`SEQUENCER
`
`MULTIPLEXOR
`
`FIG. 8
`
`INTEL Ex. 1259.008
`
`INTEL Ex. 1259.008
`
`

`

`U.S. Patent
`
`Dec. 25, 2001
`
`Sheet 7 of 82
`
`US 6,334,153 B2
`
`264 270
`FAST-PATH
`
`
`
`
`
`
`iiabeiey A
`faieesianlenl eeieeanteieentamstententan
`pntastantecadneient
`
`|PROCESSOR_||
`
`
`
`
`RRDWaRELOGT
`
`
`
`Tac
`
`
`
`oe eee ew5
`
`
`
`
`200,
`
`230)
`
`
`
`262
`
`HARDWARE LOGIC |
`
`-__---- > --->
`
`4
`
`202
`
`360
`
`350
`
`INTEL Ex. 1259.009
`
`INTEL Ex. 1259.009
`
`

`

`U.S. Patent
`
`Dee. 25, 2001
`
`Sheet 8 of 82
`
`US 6,334,153 B2
`
`TRANSPORT
`
`DATA LINK
`
`NETWORK
`
`NETWORK
`
`DATA LINK
`
`INTEL Ex. 1259.010
`
`INTEL Ex. 1259.010
`
`

`

`U.S. Patent
`
`Dec. 25, 2001
`
`Sheet 9 of 82
`
`US 6,334,153 B2
`
`6&C
`
`CCC
`
`OCC
`
`LIZ
`
`Sic
`
`C1?
`
`00
`
`06¢-~-
`
`LE?
`
`61
`
`eeeeeeweaeeeee—
`
`INATTO
`
`oanfans
`
`p9l
`
`col
`
`O9T
`
`OSI
`
`LSI
`
`INTEL Ex. 1259.011
`
`INTEL Ex. 1259.011
`
`

`

`U.S. Patent
`
`Dec. 25, 2001
`
`Sheet 10 of 82
`
`US 6,334,153 B2
`
`210
`
`REG FILE
`
`MICRO-
`PROCESSOR
`
`4
`
`Lee wn eee ee ew ew a a a a a a a a ee fm ee rn rer rer
`
`PCI BUS INTERFACE UNIT
`
`FIG. 13
`
`199
`
`INTEL Ex. 1259.012
`
`INTEL Ex. 1259.012
`
`
`
`
`
`

`

`U.S. Patent
`
`Dee. 25, 2001
`
`Sheet 11 of 82
`
`US 6,334,153 B2
`
`pewnf a @ = — = wefeewonfnneneeeeefemeenennmfeeemeenofener
`7
`
`CONTROLS FORFIRST REGISTER SET
`
`
`
`
`FIRST REGISTER SET
`
`
`
`
`
`
` neeeS
`
` INSTRUCTION.DECODER
` _----
`
`OPERAND MULTIPLEXER
`
` preaeeee
`eeeFF
`
`proneeeeee
`
`
`XN weekeeeeeeeeeweeeeeeewweauaesee
`
`THIRD REGISTER SET
`
`INTEL Ex. 1259.013
`
`INTEL Ex. 1259.013
`
`

`

`US 6,334,153 B2
`
`
`
`-----[------|------4-------|------}---waLsIoga[---}------4-------L------f-----4--4------,
`
`Nnaaa|AVIS)ox[ASRMISN'|Nidwaav|OVTA
`waavwdav|og|39|soa
`avoaVOT|HOLHdaOV1A
`
`srs|prs|-ops|--8esAN
`i.Tal)|TaloOAC
`YddvUddv
`INodLNod
`
`sy|some]x15|vivaVvaSva¥Eaaa|244|aqay
`0cs|-gzs|-szs|-zzs
`VSIDIA
`THLO|TALO|TaLO_/
`VOT|GVOT|WVuSJ,*-00S
`
`U.S. Patent
`
`Dec. 25, 2001
`
`Sheet 12 of 82
`
`¢ 0
`
`S
`
`TaLO
`
`aTWV
`
`'
`
`07S|06P
`
`INTEL Ex. 1259.014
`
`INTEL Ex. 1259.014
`
`
`
`

`

`U.S. Patent
`
`qdWVa
`
`UALSIOda
`
`ocOLS896!YONIYONI|
`et-,
`UdaTALOawoo|tas|tas|do|$00|sado}]XID!
`
`avol!UdaywUdav|nodLnod
`NOLLOANISNI!TULO
`SLSCNV
`g6s|vos|tos|06s|68s|48s|ses|pss|-zas|oss|-6Ls|Lis\'
`
`
`PLEEEEsor|WAXATELLIOWGNVYAdO
`JOO
`
`YACODAC
`
`dstOlt
`
`Dec. 25, 2001
`
`Sheet 13 of 82
`
`US 6,334,153 B2
`
`964
`
`INTEL Ex. 1259.015
`
`INTEL Ex. 1259.015
`
`

`

`U.S. Patent
`
`Dec. 25, 2001
`
`Sheet 14 of 82
`
`US 6,334,153 B2
`
`Tplele)elelelalelelelele
`ongad|VES)9d|og|LTovia|isa|990|aqy|aq|atsodIsa
`
`"aayTALItas|Lisasoo|rno|xu9
`TUL|—AONVHOXaATWOxnanv
`
`avolYOVISWDISL
`
`JSTOI
`
`LISY
`
`1
`
`INTEL Ex. 1259.016
`
`INTEL Ex. 1259.016
`
`

`

`U.S. Patent
`
`Dee. 25, 2001
`
`Sheet 15 of 82
`
`US 6,334,153 B2
`
`CLIENT
`
`
`
`
`
` FAST-PATH
`
`
`
`per
`as
`pMac|MAC
`
`PHYSICAL
`SLOW-PATH
`
`INIC
`
`|=
`
`Ethernet
`
`PC]
`
`FIG. 16
`
`Data buffers
`
`Data buffer descriptors
`
`Headerbuffer descriptors
`
`Header buffers
`
`Header a
`Header b .
`
`TCPSMB
`Headers
`
`buffer handle
`(slow-path)
`
`(fast-path) DATA
`
`INTEL Ex. 1259.017
`
`INTEL Ex. 1259.017
`
`

`

`U.S. Patent
`
`Dee. 25, 2001
`
`Sheet 16 of 82
`
`US 6,334,153 B2
`
`Response
`buffer queue
`Command
`buffer handle
`
`buffer handle
`
`Command
`buffer handle
`
`
`
`
`
`
`
`Command
`buffer queue
`
`
`
`
`
`identifier
`
`Command
`buffer handle
`
`identifier
`
`buffer handle
`
`identifier
`
`Command buffers
`
`
`Command
`
`buffer handle
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`FIG. 18
`
`INTEL Ex. 1259.018
`
`INTEL Ex. 1259.018
`
`

`

`U.S. Patent
`
`Dee. 25, 2001
`
`Sheet 17 of 82
`
`US 6,334,153 B2
`
`[POO0
`
`ERR
`
`XMT
`
`RMISS
`
`Error bits are sent
`RCVhasoccured.
`Commandhas been completed
`
`Rev drop occured due to no buffers
`
`FIG. 19
`
`Interrupt Status
`0x0
`ISR
`Interrupt Mask
`Ox4
`IMR
`Header Buffer Address
`0x8
`HBAR
`Data Buffer Handle
`0xC
`DBHR
`Data Buffer Address
`0x10
`DBAR
`
`CBARO=Ox14 Command Buffer Address XMT0
`CBARI 0x18|Command Buffer Address XMT1
`
`CBAR2
`0xlC
`Command Buffer Address XMT2
`CBAR3
`0x20
`Command Buffer Address XMT3
`CBAR4
`0x24
`Command Buffer Address RCV
`RBAR
`0x28
`Response Buffer Address
`
`FIG. 20
`
`INTEL Ex. 1259.019
`
`INTEL Ex. 1259.019
`
`

`

`U.S. Patent
`
`Dec. 25, 2001
`
`Sheet 18 of 82
`
`US 6,334,153 B2
`
`
`
`
`Packet Desc
`
`Iface
`
`ifaddr
`
`e---------4
`
`arpcom
`
`sockaddr_dl
`
`00:60:97:DB:9B:A6
`
`
`
`
`in_ifaddr
`
`
`
`sockaddr_in
`
`192.100.1.2
`
`INTEL Ex. 1259.020
`
`INTEL Ex. 1259.020
`
`

`

`U.S. Patent
`
`Dee. 25, 2001
`
`Sheet 19 of 82
`
`US 6,334,153 B2
`
`Filter Driver
`
`
`
`
`Microsoft
`TCP/IP
`
`Driver
`
`
`
`
`
`
`INIC
`3COM
`Miniport
`Miniport
`
`
`
`Driver
`Driver
`
`FIG, 23
`
`
`
`
`
`
`
`
`Buffer Desc
`
`Buffer Desc
`
`
`
`
`
`
`
`
`
`Buffer Desc
`
`Example of incoming TCP pkt
`FIG. 24
`
`Example of incoming ARP Frame
`FIG. 25
`
`INTEL Ex. 1259.021
`
`INTEL Ex. 1259.021
`
`

`

`U.S. Patent
`
`Dec. 25, 2001
`
`Sheet 20 of 82
`
`US 6,334,153 B2
`
`0
`
`
`
`=OSpJoye
`
`eyed
`
`rong
`
`sueydV
`
`09DI
`
`Te]
`my|
`qd9¢Did
`
`yyed-mo[sdOL
`dsapJang
`
`Beg
`
`qayyng
`
`Jopeoy]
`
`joyng
`
`[py
`
`yoyoegPPee
`
`Jojjng
`
`Joyjng
`
`yoyxor
`
`pe
`
`
`
`dsapJayng
`
`ayn
`
`Jopesy]
`
`qayyjng
`
`
`
`wyed-seq(OL
`
`V9CDid
`
`INTEL Ex. 1259.022
`
`INTEL Ex. 1259.022
`
`

`

`U.S. Patent
`
`Dee. 25, 2001
`
`Sheet 21 of 82
`
`US 6,334,153 B2
`
`
`
`
`
`
`Command
`Buffer
`
`
`
`Buffer
`
`INTEL Ex. 1259.023
`
`INTEL Ex. 1259.023
`
`

`

`U.S. Patent
`
`Dee. 25, 2001
`
`Sheet 22 of 82
`
`US 6,334,153 B2
`
`Buffer
`
`Command
`
`FIG. 29
`
`SRAM requirementsfor the Receive and Transmit engines:
`
`256 bytes* 16
`128 bytes* 16
`16 bytes* 256
`
`128 bytes* 16
`
`TCB buffers
`Headerbuffers
`TCBhash index
`Timers
`DRAMFifo queues
`
`4096
`2048
`4096
`128
`2048
`~12K bytes
`KC
`FIG. 30
`
`INTEL Ex. 1259.024
`
`INTEL Ex. 1259.024
`
`

`

`U.S. Patent
`
`Dee. 25, 2001
`
`Sheet 23 of 82
`
`US 6,334,153 B2
`
`Summary of the main loop of Receive:
`
`forever
`
`{
`
`while there are any Receive events
`if (a new event)
`{
`if (no new context available)
`ignore the event;
`
`{
`
`call appropriate event handler to service the event;
`this may make a waiting process runnable or set up
`a new process to be run (get free context, hddr buffer,
`TCB buffer, set the context up).
`
`while any process contexts are runable {
`run them by jumping to the start/resume address;
`if (process complete)
`free the context;
`
`FIG. 31
`
`INTEL Ex. 1259.025
`
`INTEL Ex. 1259.025
`
`

`

`U.S. Patent
`
`Dee. 25, 2001
`
`Sheet 24 of 82
`
`US 6,334,153 B2
`
`Format of the SMB headerof an SMBframe:
`
`l
`
`NetBIOS header
`
`SMBheader
`
`COM
`
`<—__
`
`LENGTH
`
` '
`Bkco Fe
`
`
`
`ERR|REB/FLG Reserved
`
`|Reg
`Red
`Res
`TID
`
`. .
`
`
`
`
`
`
`PID
`
`UID
`
`WCT
`
`MID
`
`VWV[
`
`BCC
`
`Notes(interesting fields):
`LENGTH
`17 bit Length of SMB message (0 - 128K)
`COM
`SMB command
`WCT
`Count (16 bit) of parameter words in VWV[ |
`VWV
`Variable number of parameter words
`BCC
`Bytesof data following
`
`INTEL Ex. 1259.026
`
`INTEL Ex. 1259.026
`
`

`

`U.S. Patent
`
`Dee. 25, 2001
`
`Sheet 25 of 82
`
`US 6,334,153 B2
`
`Summaryof the main loop of Transmit:
`
`forever
`
`{
`
`while there are any Transmit events
`if (a new event)
`{
`if (no new context available)
`ignore the event;
`
`{
`
`call appropriate event handler to service the event,
`this may make a waiting process runnable or set up
`a new process to be run (get free context, hddr buffer,
`TCB buffer, set the context up).
`
`while any process contexts are runable {
`run them by jumping to the start/resume address;
`if (process complete)
`free the context;
`
`FIG. 33
`
`INTEL Ex. 1259.027
`
`INTEL Ex. 1259.027
`
`

`

`U.S. Patent
`
`Dee. 25, 2001
`
`Sheet 26 of 82
`
`US 6,334,153 B2
`
`Bit 22-
`
`Bit 31 - 24 Byte enable 7 - 0. Only the low orderfourbits are
`valid for 32 bit addressing mode.
`Bit 23 - 0 Memory access
`1 Configuration access
`0 Read (to Host)
`1 Write (to Host)
`Bit 21-1 Data Valid
`Bit 20 - 16 Reserved
`Bit 15 - 0 Address
`Ke
`FIG. 34
`
`Configuration Space |
`00
`04
`08
`OC
`10
`3C
`
`SRAM Address Offset
`00
`04
`08
`OC
`10
`14
`
`00
`04
`08
`0C
`10
`3C
`
`00
`18
`08
`IC
`20
`24
`
`All other reads to configuration spacewill return 00.
`
`FIG. 35
`
`INTEL Ex. 1259.028
`
`INTEL Ex. 1259.028
`
`

`

`U.S. Patent
`
`Dee. 25, 2001
`
`Sheet 27 of 82
`
`US 6,334,153 B2
`
`Bit0-0 I/O accesses are not enabled
`Bit 1-1 Memory accesses are enabled
`Bit 2-1 Bus masteris enabled
`Bit3-0 Special Cycle is not enabled
`Bit 4-1 Memory Write and Invalidate is enabled
`Bit5-0 VGA palette snoopingis not enabled
`Bit6-1 Parity checking is enabled
`Bit7-0 Address data stepping is not enabled
`Bit 8 - SERR# is enabled
`Bit9-0 Fast back to back is not enabled
`
`FIG. 36
`
`Bit5-1
`
`66 MHz capable is enabled. This bit will be set if the INIC
`Detects the system running at 66 MHz onreset
`User Definable Features is not enabled
`Bit6-0
`Fast Back-to-Backslave transfers enabled
`Bit7-1
`Parity Error enabled - Thisbit is initialized to 0
`Bit8-1
`Bit 9,10 - 00 - Fast device select will be set if we are at 33 MHz
`01 - Medium device select will be set if we are at 66 MHz
`Bit 11-1 Target Abort is implemented.Initialized to 0.
`Bit 12-1 Target Abort is implemented.Initialized to 0.
`Bit 13-1 Master Abort is implemented.Initialized to 0.
`Bit 14-1
`SERR# is implemented. Initialized to 0.
`Bit 15-1
`Parity error is implemented. Initialized to 0.
`
`FIG. 37
`
`INTEL Ex. 1259.029
`
`INTEL Ex. 1259.029
`
`

`

`U.S. Patent
`
`Dee. 25, 2001
`
`Sheet 28 of 82
`
`US 6,334,153 B2
`
`MIA
`
`MIIB
`
`MIIC
`
`MID
`
`XmtA
`&
`RevA
`Seq
`
`XmtB
`&
`RcvB
`Seq
`
`XmtC
`&
`RevC
`Seq
`
`XmtD
`&
`RevD
`Seq
`
`REG FILE
`8KI WCS
`IKI ROM
`
`EXTERNAL
`MEMORY
`BUS
`
`uPROC
`
`1 KB X 128 Sram
`& DMACtrl
`
`EXTERNAL
`MEMORYCtl
`
`oOoO— mwomCT
`INTERFACE UNIT
`
`PCI BUS
`
`FIG. 38
`
`INTEL Ex. 1259.030
`
`INTEL Ex. 1259.030
`
`

`

`U.S. Patent
`
`Dee. 25, 2001
`
`Sheet 29 of 82
`
`US 6,334,153 B2
`
`SPEED
`4.37 nsnom.,
`6.40 nsnom.,
`3.50 ns nom.,
`5.00 ns nom.,
`6.10 nsnom.,
`
`DESCR
`MODULE
`IKx128sport,
`Scratch RAM,
`8Kx49 sport,
`WCS,
`128x7 sport,
`MAP,
`1Kx49 32col,
`ROM,
`512x32 tport,
`REGs,
`75 mm? x 4=
`Macs,
`5mm? =
`PLL,
`MISC LOGIC,117,260gates / (5035 gates / mm?)=
`TOTAL CORE
`
`(Core sidey
`Core side
`Dieside
`Die area
`
`Pads needed
`LSI PBGA
`
`=core side + 1.0 mm (I/O cells)
`= 8.5 mm x 8.5 mm
`
`= 220 signals x 1.25 (vss, vdd)
`
`FIG, 39
`
`AREA
`06.77 mm”
`18.29 mm?
`00.24 mm?
`00.45 mm?
`03.49 mm?
`03.30 mm?
`00.55 mm?
`23.29 mm?
`56.22 mm”
`
`56.22 mm*
`(07.50 mm
`08.50 mm
`72.25 mm?
`
`275 pins
`272 pins
`
`=
`=
`=
`=
`
`=
`=
`
`INTEL Ex. 1259.031
`
`INTEL Ex. 1259.031
`
`

`

`U.S. Patent
`
`Dee. 25, 2001
`
`Sheet 30 of 82
`
`US 6,334,153 B2
`
`=
`=
`=
`
`80 MB/s
`512B
`156,250 frames / s
`
`(10MB/s/100Base) x 2 (full duplex) x 4 connections
`Average framesize
`Frame rate = 80MB/s / 512B
`Cpuoverhead / frame = (256B context read) + (64B header read) +
`512B/ frame
`=
`(128B context write) + (128B misc.)
`|536B/ frame
`=
`Total bandwidth = (512B in) + (512B out) + ($12B Cpu)
`240MB/s
`=
`Dram Bandwidth required = (1536B/frame) x (156,250 frames/s)
`
`Dram Bandwidth @ 60MHz=(32 bytes / 167ns) = 202MB/s
`
`Dram Bandwidth @ 66MHz = (32 bytes / 150ns)
`=
`224MB/s
`PCI Bandwidth required
`=
`§80MB/s
`PCI Bandwidth available @ 30 MHz, 32b,average
`=
`46MB/s
`PCI Bandwidth available @ 33 MHz, 32b, average
`=
`50MB/s
`PCI Bandwidth available @ 60 MHz,32b,average
`=
`92MB/s
`PCI Bandwidth available @ 66 MHz, 32b,average
`=
`100MB/s
`PCI Bandwidth available @ 30 MHz,64b,average
`=
`92MB/s
`PCI Bandwidth available @ 33 MHz,64, average
`=
`{00MB/s
`PCI Bandwidth available @ 60 MHz, 64b,average
`=
`|84MB/s
`PCI Bandwidth available @ 66 MHz,64, average
`=
`00MB/s
`
`FIG. 40
`
`Receiveframe interval = 512B / 40MB/s
`Instructions / frame @ 60MHz=(12.8us/ftame) /(SOns/instruction)
`instructions/frame
`Instructions / frame @ 66MHz=(12.8us/ftame)/ (4Sns/instruction)
`instructions/frame
`250 instructions/frame
`=
`Required instructions / frame
`KY
`FIG. 41
`
`=
`=
`
`=
`
`|2.8us
`256
`
`284
`
`INTEL Ex. 1259.032
`
`INTEL Ex. 1259.032
`
`

`

`CLK ||SramcetLOAD ONfomFETCH]LOAD meLOAD
`
`! L7
`=LCt DCH
`<1 oes EET iSTAck| A
`
`
`
`nie|cme {REGS| ccs REG|Ack{REGS TARAS Ad
`
`
`
`MS
`51032
`Kx3)
`addr out
`
`U.S. Patent
`
`Dee. 25, 2001
`
`Sheet 31 of 82
`
`US 6,334,153 B2
`
`|)
`
`
`
`
`sah
`se ex
`
`‘=aeen fo
`2 EmonDECODER
`
`
`LeALULiALULbFLAG a
`van DEBUG
` ealScaeeaesc)a
`
`CTX ToT=OP|SEL|SEL ocuo | Ctrl CAEE} Addr
`
`
`dout
`
`PC
`
`|STAck
`
`SanLh
`FILE LALUsayrst [AGPLS Ls
`
`oe ocs|SEE|pour set oni ou | STAASE A
`
`
`
`
`
`
`FIG. 42
`
`INTEL Ex. 1259.033
`
`INTEL Ex. 1259.033
`
`

`

`U.S. Patent
`
`Dec. 25, 2001
`
`Sheet 32 of 82
`
`US 6,334,153 B2
`
`INSTRUCTION-WORD FORMAT
`
`
`
`
`
`
`
`TYPE [48:47] [46:42]_[41:33]_[55:49]_ [32:24] [23:16] [15:00]
`
`TstSel, Literal
`OpdASel,
`OpdBSel,
`
`Jcc
`
`0b0000000
`
`0b00, AluOp,
`
`Jmp
`
`0b0000000
`
`0b01, AluOp,
`
`OpdASel,
`
`OpdBSel,
`
`0b0000000
`
`0b10, AluOp,
`
`OpdASel,
`
`OpdBSel,
`
`FigSel, Literal
`
`FligSel, Literal
`
`0b0000000
`
`Ob11, AluOp,
`
`OpdASel,
`
`OpdBSel,
`
`Ohff,
`
`Literal
`
`Jsr
`
`Rts
`
`Nxt
`
`0b0000000
`
`Obl1, AluOp,
`
`OpdASel,
`
`OpdBSel,
`
`FlgSel, Literal
`
`Map
`
`MapAddr
`
`OBXX, OBXXXXX, OBXXXXXXXXX, OBKXXKXXXXX, OHXX, OHXXXX
`
`FIG. 43
`
`INTEL Ex. 1259.034
`
`INTEL Ex. 1259.034
`
`

`

`U.S. Patent
`
`Dee. 25, 2001
`
`Sheet 33 of 82
`
`US 6,334,153 B2
`
`SEQUENCER BEHAVIOR
`
`if (MapEn & (MapAddr!= 0b0000000)){
`Stacke = Stackc;
`StackB = StackB;
`StackA = StackA;
`InstrAddr = 0h8000 | Pe[2:0] | (MapAddr << 3);
`Pc = InstrAddr + (Execute & ~DbgMd);
`Fetch = DbgMd ? DbgAddr:InstrAddr,
`DbgAddr = DbgAddr + (Execute & DbgMd);}
`
`//re-map instr
`
`else if (PgmCtrl == Jec){
`Stacke = Stackc;
`StackB = StackB;
`StackA = StackA;
`InstrAddr = ~Tst@TstSel ? Pc:(AluDst==Pc) ? AluOut:Literal;
`Pc = InstrAddr + (Execute & ~DbgMd)
`Fetch = DbgMd ? DbgAddr:InstrAddr,
`DbgAddr = DbgAddr+ (Execute & DbgMd);}
`
`/{conditional jump
`
`else if (PgmCtrl == Jmp){
`Stacke = Stacke;
`StackB = StackB;
`StackA = StackA;
`InstrAddr = (AluDst == Pc) ? AluOut:Literal;
`Pc = InstrAddr + (Execute & ~DbgMd)
`Fetch = DbgMd ? DbgAddr:InstrAddr;
`DbgAddr = DbgAddr+ (Execute & DbgMd);}
`else if (PgmCtrl == Jsr){
`Stacke = StackB;
`StackB = StackA;
`StackA = Pc;
`InstrAddr = (AluDst == Pe) ? AluOut:Literal,;
`Pc = InstrAddr + (Execute & ~DbgMd)
`Fetch = DbgMd ? DbgAddr:InstrAddr;
`DbgAddr = DbgAddr + (Execute & DbgMd);}
`else if (FlgSel == Rts){
`InstrAddr = StackA;
`StackA = StackB;
`StackB = Stackc;
`Stacke = ErrVec;
`Pc = InstrAddr + (Execute & ~DbgMd)
`Fetch = DbgMd ? DbgAddr:InstrAddr,
`DbgAddr = DbgAddr+ (Execute & DbgMd);}
`
`else
`
`{
`InstrAddr = Pe;
`StackA = StackA;
`StackB = StackB;
`Stacke = Stacke;
`Pc = InstrAddr + (Execute & ~DbgMd)
`Fetch = DbgMd ? DbgAddr:InstrAddr,
`DbgAddr = DbgAddr+ (Execute & DbgMd);}
`
`//jump
`
`//yump subroutine
`
`/freturn subroutine
`
`//fcontinue
`
`FIG. 44
`
`INTEL Ex. 1259.035
`
`INTEL Ex. 1259.035
`
`

`

`U.S. Patent
`
`Dec. 25, 2001
`
`Sheet 34 of 82
`
`US 6,334,153 B2
`
`ALU OPERATIONS
`
`AluOp
`
`0b00000
`
`0b00001
`
`0b00010
`
`0b00011
`
`0b00100
`0b00101
`
`OPERATION
`
`A=(A & ~(1 << B));
`C = 0; V = (B >= 32) ? 1:0;
`
`A=(A & B);
`C=0; V=0;
`
`= (Literal & B);
`C=0; V=0;
`
`A = (~Literal & B);
`C=0; V=0;
`
`= (B >= 32) ? 1:0;
`
`A=avera << B));
`A=(A|B);
`C=0; V=0;
`
`//bit clear
`
`/Nogical and
`
`/Nogical and
`
`/{logical and not
`
`bit set
`
`/Nogical or
`
`
`
`/Nogical or
`0b00110 A=(Literal| B);
`C=0; V=0;
`
`0b00111
`
`0b01000
`
`0b01001
`
`0b01010
`
`0b01011
`
`0b01100
`
`0b01101
`
`0b01110
`
`0b01111
`
`A = (~Literal| B);
`C=0; V=0;
`
`for (i=31; i>=0; i--) if B[i] continue; A=i;
`C=0;V= (B) 20:1;
`
`A=(A“%B);
`C=0;
`V=0;
`
`A = ({Literal} * B);
`C=0;V=0;
`
`A = ({~Literal} * B);
`C=0; V=0;
`
`A=B;
`C=0;V=0;
`
`A = B[31:24] * B[23:16] * B[15:08] * B[07:00];
`C=0; V=0;
`
`A= {B[23:16],B[31:24],B[07:00],B[15:08]}
`C=0; V=0;
`
`A = {B[15:00], B[31:16]};
`C=0; V=0;
`
`/Nogical or not
`
`//priority enc
`
`/flogical xor
`
`/Aogical xor
`
`/Nogical xor not
`
`//move
`
`//hash
`
`//swap bytes
`
`//swap doublets
`
`FIG. 45
`
`INTEL Ex. 1259.036
`
`INTEL Ex. 1259.036
`
`

`

`U.S. Patent
`
`Dec. 25, 2001
`
`Sheet 35 of 82
`
`US 6,334,153 B2
`
`AluOp
`
`0b10000
`
`0b10001
`
`0b10010
`
`0b10011
`
`0b10100
`
`0b10101
`
`0b10110
`
`0b10111
`
`0b11000
`
`0b11001
`
`0b11010
`
`0b11100
`
`0b11101
`
`0b11110
`
`Ob11111
`
`FUNCTION
`
`A=(A+B);
`C =(A + B)[32]; V = 0;
`
`A=(A+B+O);
`C=(A+B+C©)[32]; V=0;
`
`A = (Literal + B);
`C = (Literal + B)[32]; V = 0;
`
`A = (-Literal + B);
`C = (-Literal + B)[32]; V = 0;
`
`A=(A-B);
`C=(A - B)32]; V = 0;
`
`A=(A-B--C);
`C=(A-B-~O)32]; V=0;
`C= CA + B32]: V = 0;
`A=(-A+B-~C);
`C =(-A+B-~C)[32]; V = 0;
`
`A=(A <<B);
`C= A[31];V
`
`= (B>= 32)? 0:1;
`
`A = (B << Literal);
`C= B[31]; V = (Literal >= 32) ? 0:1;
`
`A=(B<< 1);
`C= B31]; V=9;
`C=(A- B32]; V =0;
`C= ATO, Vv (B >= 32)? 1:0;
`A = (B >> Literal);
`C= A[0]; V = (Literal >= 32) ? 1:0;
`
`A=(A>>B
`
`A=(B>> 1);
`C= A[0}; V = 0;
`
`n = (B - A),
`C =(B- A)[32]; V = 0;
`
`/{compare
`n= (A-B);
`0b11011
`
`Hladd B
`
`//fadd B, carry
`
`//add constant
`
`//sub constant
`
`//sub B
`
`//sub B, borrow
`
`//sub A
`
`/{sub A, borrow
`
`(shift left A
`
`//shift left B
`
`//shift left B
`
`//shift right A
`
`shift right B
`
`shift right B
`
`/{compare
`
`FIG. 46
`
`INTEL Ex. 1259.037
`
`INTEL Ex. 1259.037
`
`

`

`U.S. Patent
`
`Dee. 25, 2001
`
`Sheet 36 of 82
`
`US 6,334,153 B2
`
`OpdSel_
`0b0000aaaaa
`
`SELECTED OPERANDS
`
`File
`
`File@(OpdSel[4:0] | FileBase);
`Allows paged access to any part ofthe registerfile.
`
`0b000 1 aaaaa
`
`CpuReg
`
`File@{2'b11, Cpuld, OpdSel[4:0]};
`Allowsdirect access to
`Cpu specific registers.
`
`Ob00IXXXXXX reserved
`
`Reserved for future expansion.
`
`0b0100000XX
`
`CpuStatus
`
`0b0000000000000BHD00000000000000CC
`This is a read-only register providing information about the Cpu executing
`(OpdSel[1:0]) cycles after the current cycle. "CC"represents a value
`indicating the Cpu. Currently, only Cpuld values of 0, 1 and 2 are returned.
`"H"represents the current state of HIt, "D" indicates DbgMdand "B"
`indicates BigMd. Writing this register has no effect.
`
`0b0100001XX
`
`reserved
`
`Reserved for future expansion.
`
`0b0100010XX
`
`Pe
`
`0b0100011XX
`
`DbgAddr
`
`Ox0000AAAA
`Writing to this address causes the program control logic to use AluOutas the
`new Pevalue in the event of a Jmp, Jee or Jsr instruction for the Cpu
`executing during the current cycle. If the current instruction is Nxt, Map, or
`Rts, the register write has no effect. Reading this register returns the value in
`Pc for the Cpu executing (OpdSel[1:0]) cycles after the current cycle.
`
`OxDO00AAAA
`Writingto this register alters the contents of the debug addressregister
`(DbgAddr) for the Cpu executing (OpdSel[1:0]) cycles after the current
`cycle. DbgAddrprovides the fetch address for the control-store when
`DbgMdhasbeenselected and the Cpu is executing. DbgAddris also used
`as the control-store address when performing a WrWes@DbgAddr or
`RdWes@DbgAddroperation. “D”represents bit 31 of the register. It is a general
`purpose
`flag that is used for event indication during simulation. Reading this
`register returns a value of 0x00000000.
`
`0b01001XXXKX
`
`reserved
`
`Reserved for future expansion.
`
`06010100000
`
`RamAddr {0b1CCC, 0x000, 0b1, AAAA}
`RamAddr = AluOut[15] ? AluQut : (AluOut | RamBase);
`PrevCC = AluOut{31]?CCC :AlCC;
`A read/write register. When readingthis register, the Alu condition codes from the previous
`instruction are returned together with RamAddr.
`
`name
`
`PrevC
`PrevV
`PrevZ
`
`bit
`description
`31
`Always1.
`30
`Previous Alu Carry.
`29
`Previous Alu Overflow.
`28
`Previous Alu Zero.
`27:16
`Always 0.
`15
`Always1.
`14:0
`RamAddr
`Contents of last Sram address used.
`Whenwritingthisregister, if alu_out[31] is set, the previous condition codeswill be overwritten with
`bits 30:28 of AluOut. If AluOut{ 15]is set, bits 14:0 will be written to the RamAddr.If AluOut[15]
`is notset, bits 14:0 will be ored with the contents of the RamBase andwritten to the RamAddr
`
`FIG. 47
`
`INTEL Ex. 1259.038
`
`INTEL Ex. 1259.038
`
`

`

`U.S. Patent
`
`Dee. 25, 2001
`
`Sheet 37 of 82
`
`US 6,334,153 B2
`
`OpdSel
`0b010100001
`
`SELECTED OPERANDs
`
`AddrRegA
`
`0x0000AAAA
`
`AddrRegA = AluOut,
`A read/write operand which loads AddrRegAusedto provide the address for read and write
`gperations: When AddrRegA[15]is set, the contents will be presented directly to the ram.
`en AddrRegA[1 >| is reset, the contents will first be ored with the contents ofthe RamBase
`ation to the ram. Writing to this register takes priority over Literal loads
`register before presen
`:
`ue of the register.
`using FlgOp.
`Readingthis register returns the current va
`AddrRegB 0x0000AAAA
`
`0b010100010
`
`AddrRegB = AluOut;
`A read/write operand which loads AddrRegB usedto provide the address for read and write
`operations.
`When AddrRegB[15]is set, the contents will be presented directly to the ram. When
`AddrRegB[15{is reset, the contents will first be ored with the contents of the RamBase
`register before presentation to the ram. Writing to this register takes priority over Literal loads
`using FigOp. Reading this register returns the current value ofthe register.
`AddrRegAb—0x0000AAAA
`06010100011
`AddrRegA = AluOut; AddrRegB = AluOut;
`A destination only operand which loads AddrRegB and AddrRegaAusedto provide the address
`for read and write operations Writingto this register takes priority over Literal loads using
`FigOp. Readingthis register returns the value 0x00000000.
`RamBase
`0x0000AAAA
`RamBase = AluOut;
`A read/write register which providesthe base address for ram read and write cycles. When
`RamAddr{15)is set, the contents will not be used. When RamAddr[15]is reset, the contents
`will first be oredwith the contents of the RamBaseregister before presentation to the ram.
`Readingthis register returns the value for the current
`Cpu.
`FileBase
`0b00000000000000000000000AAAAAAAAA
`FileBase = AluOut;
`FileAddr = OpdSei{8| ? OpdSel:(OpdSel + FileBase);
`A read/write register which provides the base address for file read and write cycles. When
`0 dSel[8| is set, the contents will not be used and OpdSel will be presented irectly to the
`addresslines ofthe file. When OpdSel(8]is reset, the contents will first be ored with the
`contents of the FileBase register before presentationto the file. Reading this register returns the
`value for the current Cpu.
`
`0b010100100
`
`0b010100101
`
`0b010100110
`
`0b010100111
`
`InstrRegL Oxi
`This is a read-only register which returns the contents of InstrReg[3 1:0}. Writing to
`this register has no effect.
`
`OxOOIINII
`InstrRegH
`This is a read-only register which returns the contents of InstrReg[55:32]. Writing to this
`register has noeffect.
`
`FIG. 48
`
`INTEL Ex. 1259.039
`
`INTEL Ex. 1259.039
`
`

`

`U.S. Patent
`
`Dec. 25, 2001
`
`Sheet 38 of 82
`
`US 6,334,153 B2
`
`OpdSel
`
`SELECTED OPERANDs
`
`06010101000
`
`Minus1
`
`Oxfffftttt
`This is a read-only register which supplies a value Oxffffffff.. Writing to this
`register has no effect.
`
`0b010101001
`
`FreeTime
`
`A free-runningtimerwitha resolution of 1.00 microseconds and amaximum count
`of 71 minutes. This timer is cleared duringreset.
`
`0b010101010
`
`LiteralL
`
`Instr[15:0]
`A read-only register. Writing to this register has no effect
`
`0b010101011
`
`LiteralH
`
`Instr[15:0]<<16;
`A read-only register. Writing to this register has no effect
`
`0b010101100
`
`MacData - Writing to this address loads the AluOutdata into the MacDataregister for use
`during Mac operations. The Macoperation,resulting from writing to the MacOpregister,
`determines the definition of the MacDataregister contents as follows.
`
`MacOp
`Mstop
`
`WrMefg
`
`MacData definition
`ObXXXXXXXXXXXXXKXXKXXXKKKKXXKXXKXKKXXX
`MacDatais not used for the StopM operation.
`
`hrstl, rsvd, rsvd, ercen, fulld, hrstl, hugen, nopre, paden, prtyl, xdl10,
`ipgr1[6:0],
`ipgr2[6:0], ipgt[6:0].
`Loads the MaeCfg register with the contents of the MacDataregister. Refer to
`LSI Logic's Ethernet-110 Core Technical Manualfordetailed definitions ofthese
`bits.
`
`WrMrng
`
`ObXXXXXXXXXXXXXXXXXXXXXSSSSSSSSSSS
`Loads seed[10:0] into the Mac's random number generator.
`
`RdPhy
`
`WrPhy
`
`ObXXXXRRRRXXXXPPPPXXXXXXXXKKXKXXKXKXK
`Readsregister[R] of phy[P].
`
`0bXXXXRRRRXXXXPPPPDDDDDDDDDDDDDDDD
`Writes register[R] of phy[P] with MacData[15:0].
`
`Readingthis register returns prsd[15:0] of Mac0 which contains phy status data returned to the
`Macat the completion of a RdPhy command. This data is invalid while MacBsy is asserted
`as a result of a RdPhy command.Refer to the appropriate phy technical manualfor a
`definition of the phy register contents.
`
`FIG. 49
`
`INTEL Ex. 1259.040
`
`INTEL Ex. 1259.040
`
`

`

`US 6,334,153 B2
`
`U.S. Patent
`
`Dee. 25, 2001
`
`Sheet 39 of 82
`
`FIG. 50A
`
`FIG. 50B
`
`FIG. 50C
`
`FIG. 50
`
`INTEL Ex. 1259.041
`
`INTEL Ex. 1259.041
`
`

`

`U.S. Patent
`
`Dee. 25, 2001
`
`Sheet 40 of 82
`
`US 6,334,153 B2
`
`OpdSel
`
`SELECTED OPERANDs
`
`0b010101101
`
`MacOp- A write only register. Writing to this address loads the MacSelregister and staRts
`execution of the specified operation as follows.
`
`AluQOut
`OxXXXXXOXM
`
`OxXXXXXIXM
`
`OxXXXXX2XM
`
`description
`Mstop - Halts execution of a MacOp for Mac[M]. The user must wait for
`MacBsyto be deasserted before issuing another