(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2004/0064578A1
`(43) Pub. Date:
`Apr. 1, 2004
`Boucher et al.
`
`US 2004OO64578A1
`
`(54) FAST-PATH APPARATUS FOR RECEIVING
`DATA CORRESPONDING TO A TCP
`CONNECTION
`(75) Inventors: Laurence B. Boucher, Saratoga, CA
`(US); Stephen E. J. Blightman, San
`Jose, CA (US); Peter K. Craft, San
`Francisco, CA (US); David A. Higgen,
`Saratoga, CA (US); Clive M. Philbrick,
`San Jose, CA (US); Daryl D. Starr,
`Milpitas, CA (US)
`Correspondence Address:
`MARKA LAUER
`66O1 KOLL CENTER PARKWAY
`SUTE 245
`PLEASANTON, CA 94566 (US)
`(73) Assignee: Alacritech, Inc.
`(21) Appl. No.:
`10/260,878
`(22) Filed:
`Sep. 27, 2002
`Publication Classification
`
`(51) Int. Cl." ..................................................... G06F 15/16
`
`(52) U.S. Cl. ............................................ 709/236; 709/238
`
`(57)
`
`ABSTRACT
`
`A System for protocol processing in a computer network has
`an intelligent network interface card (INIC) or communica
`tion processing device (CPD) associated with a host com
`puter. The INIC provides a fast-path that avoids protocol
`processing for most large multi-packet messages, greatly
`accelerating data communication. The INIC also assists the
`host for those message packets that are chosen for proceSS
`ing by host Software layers. A communication control block
`for a message is defined that allows DMA controllers of the
`INIC to move data, free of headers, directly to or from a
`destination or Source in the host. The context is Stored in the
`INIC as a communication control block (CCB) that can be
`passed back to the host for message processing by the host.
`The INIC contains specialized hardware circuits that are
`much faster at their specific tasks than a general purpose
`CPU. A preferred embodiment includes a trio of pipelined
`processors with Separate processors devoted to transmit,
`receive and management processing, with full duplex com
`munication for four fast Ethernet nodes.
`
`
`
`
`
`
`
`
`
`
`
`CONTEXT
`
`52
`
`
`
`
`
`
`
`46
`
`UPPERLAYER
`INTERFACE
`
`TRANSPORT
`
`NETWORK
`
`DATA LINK
`
`INIC/CPD
`
`STORAGE
`
`35
`
`58
`
`Alacritech, Ex. 2021 Page 1
`
`

`

`Patent Application Publication
`
`Apr. 1, 2004 Sheet 1 of 89
`
`US 2004/0064578A1
`
`
`
`46
`
`
`
`
`
`STORAGE
`
`35
`
`58
`
`CONTEXT
`
`
`
`
`
`
`
`
`
`UPPER LAYER
`INTERFACE
`
`TRANSPORT
`
`NETWORK
`
`DATA LINK
`
`INIC/CPD
`
`FIG. 2
`
`Alacritech, Ex. 2021 Page 2
`
`

`

`Patent Application Publication
`
`Apr. 1, 2004 Sheet 2 of 89
`
`US 2004/0064578A1
`
`RECEIVE PACKET
`FROM NETWORK
`BY CPD
`
`VALIDATE PACKET,
`SUMMARIZE
`HEADERS
`
`
`
`
`
`
`
`
`
`
`
`59- N
`FAST PATH
`CANDIDATE 2
`
`
`
`MATCH WITH
`CCB)
`
`SEND TO
`DESTINATION
`IN HOST VIA
`FAST-PATH
`
`
`
`
`
`
`
`FIG 3
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`61
`
`S
`
`
`
`
`
`SEND PACKET TO
`STACK FOR SLOW
`PATH PROCESSING
`
`65 c
`
`
`
`
`
`
`
`SEND PACKET TO
`STACK FOR SLOW
`PATH PROCESSING
`
`CREATE CCBFOR
`MESSAGE
`
`Alacritech, Ex. 2021 Page 3
`
`

`

`Patent Application Publication
`
`Apr. 1, 2004 Sheet 3 of 89
`
`US 2004/0064578A1
`
`
`
`REMOTE
`HOST
`
`Alacritech, Ex. 2021 Page 4
`
`

`

`Patent Application Publication
`
`Apr. 1, 2004 Sheet 4 of 89
`
`US 2004/0064578A1
`
`
`
`
`
`
`
`
`
`PROCESSOR
`
`HARDWARE LOGIC
`
`Alacritech, Ex. 2021 Page 5
`
`

`

`Patent Application Publication
`
`Apr. 1, 2004 Sheet 5 of 89
`
`US 2004/0064578A1
`
`MEDIA ACCESS
`CONTROLLER
`
`172
`
`FLY BY
`SEQUENCER
`
`
`
`176
`
`PACKET
`* CONTROL
`SEQUENCER
`
`
`
`ASSEMBLY
`REGISTER
`
`
`
`
`
`
`
`
`
`MULTIPLEXOR
`
`182
`
`
`
`
`
`
`
`FIG 7
`
`DRAM CONTROL
`
`186
`
`88
`
`UEUE
`Q
`
`Alacritech, Ex. 2021 Page 6
`
`

`

`Patent Application Publication
`
`Apr. 1, 2004 Sheet 6 of 89
`
`US 2004/0064578A1
`
`
`
`76
`
`
`
`PACKET
`CONTROL
`SEQUENCER
`
`174
`
`ASSEMBLY
`REGISTER
`
`
`
`178
`
`MAC
`SEQUENCER
`
`NETWORK
`SEQUENCER
`
`
`
`
`
`
`
`TRANSPORT
`SEQUENCER
`
`SESSION
`SEQUENCER
`
`180
`
`
`
`MULTIPLEXOR
`
`FIG. 8
`
`Alacritech, Ex. 2021 Page 7
`
`

`

`Patent Application Publication
`
`Apr. 1, 2004 Sheet 7 of 89
`
`US 2004/0064578A1
`
`
`
`
`
`
`
`
`
`
`
`
`
`242
`
`
`
`
`
`PROCESSOR
`HARDWARE LOGIC 4
`HARDWARE LOGIC 3| S
`
`
`
`SOURCE/DEST
`
`APPLICATION
`
`TRANSPORT
`
`NETWORK
`
`
`
`
`
`360
`
`
`
`370
`
`366
`
`363
`
`375
`
`TDI FILTER DRIVER
`& UPPERLAYER INTERFACE
`
`382
`
`350
`
`355
`
`353
`
`Alacritech, Ex. 2021 Page 8
`
`

`

`Patent Application Publication
`
`Apr. 1, 2004 Sheet 8 of 89
`
`US 2004/0064578A1
`
`202 /
`
`--- 1
`
`330
`325/n
`
`300
`
`318
`
`UPPER LAYER
`
`|
`
`UPPER LAYER INTERFACE
`
`TRANSPORT
`
`TRANSPORT
`
`316
`
`322/N
`
`NETWORK
`
`NETWORK
`
`320
`
`DATA LINK
`
`DATA LINK
`
`314
`
`312
`
`306
`
`INIC MINIPORT DRIVER
`
`200
`
`210
`
`INIC
`
`INIC
`MEMORY
`
`304
`
`FIG 10
`
`Alacritech, Ex. 2021 Page 9
`
`

`

`Patent Application Publication
`
`Apr. 1, 2004 Sheet 9 of 89
`
`US 2004/0064578A1
`
`º— — — — ^— — -- - - – – – – – – – – – –) _I
`
`Alacritech, Ex. 2021 Page 10
`
`

`

`Patent Application Publication
`
`Apr. 1, 2004 Sheet 10 of 89 US 2004/0064578A1
`
`
`
`EXTERNAL
`MEMORY
`
`Alacritech, Ex. 2021 Page 11
`
`

`

`Patent Application Publication
`
`Apr. 1, 2004 Sheet 11 of 89 US 2004/006,4578A1
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`CONTROLS FOR FIRST REGISTER SET
`
`FIRST REGISTER SET
`
`RAM FILE
`REGISTER
`
`INSTRUCTION DECODER
`AND
`OPERAND MULTIPLEXER
`
`SECOND REGISTER SET
`
`
`
`STACK
`EXCHANGE
`
`y
`ARTHMETIC LOGIC UNIT
`
`QUEUE
`
`
`
`THIRD REGISTER SET
`
`FIG. 14
`
`Alacritech, Ex. 2021 Page 12
`
`

`

`Apr. 1, 2004 Sheet 12 of 89
`
`US 2004/0064578 Al
`
`INOGLNOd
`
`aYddvAddV
`
`VSTDIA
`
`Patent Application Publication
`
`
`waisioayFPees|}Heeepee——----j4Tope
`
`!Isos|sts|-I1s90s|ros|,zos|,IZ6b
` wddv_NId!!|__-__---1\\
`
`YAY|vyel5gPUCav|Ose|,4|SOFx)$99seveXLO“eeayonaad
`
`
`HOLAAMLSNTayOW]ATV||ATsaay
`avoCVOTHOLAOvCVOT|AVOTINVUS|
`THILOTAL|Taro]EARSoaTHLO|THLO|THLO|
`alldWV07S106¢BPS|prs|OPS|/8eses|-gzs|Sts
`
`\
`
`00S
`
`|
`
`Alacritech, Ex. 2021 Page 13
`
`Alacritech, Ex. 2021 Page 13
`
`
`
`

`

`Patent Application Publication
`
`Apr. 1, 2004 Sheet 13 of 89
`
`US 2004/0064578 Al
`
`avo
`
`SLS
`
`ONGC
`adddv
`MAOVIS|Od
`
`
`
`ast“Ola
`
`
`CLCLeeLerle
`86SP6S6S06S68S£8
`
`
`|=|esbalalalelels|-
`WOdBHIO|OVA)LSAL|ATV|ATV|ATV|aT
`
`
`UaXATILIANANVaddO
`
`wdHdOO0ddNOLLONALSNI
`S|Ss8s}0
`
`
`Srgs|Z8S]pare|64S}
`
`30Nia’udav
`
`WdWVa
`
`UALSIOTY
`
`CNV
`
`WVuas
`
`Alacritech, Ex. 2021 Page 14
`
`Alacritech, Ex. 2021 Page 14
`
`
`
`

`

`Patent Application Publication
`
`Apr. 1, 2004 Sheet 14 of 89
`
`US 2004/0064578A1
`
`TRILOQTVÒ
`
`>{OVLS
`
`
`
`{{{DNV HOXEI
`
`- ?
`
`WVYHÒ
`
`
`
`OS I "OIH
`
`YHCICIVTRILO
`
`SOTHÒ„LSHOI
`
`(HCIGIVÒTHS | LTS?|JLTSYI
`JLITI?ovisi | isiqi | 949
`
`[QTV ] [QTV ] ©HTIIH
`SOO | Ino | XLO
`
`(((((
`No.ae,
`
`- - - - - - - - - - - - - - - - - - - - - - - - - - - -
`
`Alacritech, Ex. 2021 Page 15
`
`

`

`Patent Application Publication
`
`Apr. 1, 2004 Sheet 15 of 89 US 2004/0064578A1
`
`745
`
`
`
`746
`
`764 772 770 768
`
`766
`
`762
`
`740
`
`755
`S->
`
`776, 784 782 780
`
`778
`
`77
`
`760
`S->
`
`788 796 764 792
`790
`FIG. 17
`
`L
`
`786
`
`Alacritech, Ex. 2021 Page 16
`
`

`

`Patent Application Publication
`
`Apr. 1, 2004 Sheet 16 of 89 US 2004/0064578A1
`
`8O2 Proc
`Req
`
`Seq
`Seq | Seq || Seq
`Req/ y Req/ VReqA VReq
`
`808
`
`810
`
`804 ,
`
`8
`15
`
`ARBITER
`
`844
`
`846
`
`Addr
`Out
`
`Addr
`In
`
`DIn
`QRAM
`DOut
`
`828
`
`822 N
`
`QALU
`
`- - - - - m - - - - -
`
`
`
`
`
`- 82
`
`A. -
`
`stam Sram Body Body
`Q
`Q
`Q
`Q
`| Real Addr Write Read
`Empty || Fill." Out
`C
`Req |
`| Req
`imply
`RDY||RDY
`\830 V833 \835 N838 840
`\755 T \760 \750 \745
`FIG. 18
`
`Sram
`
`Alacritech, Ex. 2021 Page 17
`
`

`

`Patent Application Publication
`
`Apr. 1, 2004 Sheet 17 of 89 US 2004/0064578A1
`
`LRU
`900
`N R0 R1 || R2
`| 9 ||
`1
`|| 7 . .
`
`R7 R8 R9
`2 || 2 || 0 . .
`FIG. 19A
`
`MRU
`R13 R14 R15
`| f | 0
`
`900
`\
`
`LRU
`R0 R1 || R2
`1
`|| 7 || 5
`
`. .
`
`R7 R8 R9
`12 || 0 || 3 ||
`FIG. 19B
`
`LRU
`900
`NRO R1 || R2
`|
`| 7 || 5 | .
`
`.
`
`R7 R8 R9
`12 | 3 || 8 | .
`FIG. 19C
`
`MRU
`R13 R14 R5
`|| 4 || 6 || 9
`
`MRU
`R13 R14 R15
`. | 6 || 9 || 10
`
`900
`N
`
`LRU
`R0 R1 || R2
`8
`1
`7
`
`.
`
`.
`
`MRU
`R13 R14 R5
`6,
`9
`()
`
`.
`
`.
`
`R7 R8 R9
`2
`12
`3
`FIG. 9D
`
`Alacritech, Ex. 2021 Page 18
`
`

`

`Patent Application Publication
`
`Apr. 1, 2004 Sheet 18 of 89
`
`US 2004/0064578A1
`
`
`
`S$6
`
`HOSSHOOHä.
`
`0/17
`
`
`
`SJL[[]ORIO OIDOTI
`
`Alacritech, Ex. 2021 Page 19
`
`

`

`Patent Application Publication
`
`Apr. 1, 2004 Sheet 19 of 89 US 2004/0064578A1
`
`NETWORK
`210
`210
`- - -
`
`- - - - -
`
`NC 200
`- - - - - - - - - - - - - - - - - - - - - -
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`PHYSICAL
`LAYER
`INTERF.
`
`21 OO
`
`ASIC 400
`
`MEDIA
`AEss
`
`SEQUENCERS
`2102
`RXSEC)
`2105
`
`PROCESSOR
`470
`TX RX
`2231
`
`
`
`
`
`ATUS
`ST
`223
`2
`
`
`
`
`
`
`
`
`
`} BUFFER
`2114
`
`21 O7
`-'
`
`
`
`STORAGE
`35
`
`Alacritech, Ex. 2021 Page 20
`
`

`

`Patent Application Publication
`
`Apr. 1, 2004 Sheet 20 of 89 US 2004/0064578A1
`
`MAC
`
`2215
`
`8
`
`- - - - - - - - - - - we a- H - - - - - - - -
`
`T
`
`2213 2214 2227
`7
`
`2221-
`
`
`
`OUEUE
`MANAGER
`
`2210 2209
`
`- - - - - - - |- - - - - - - - - -
`
`SYNC
`BUFFER
`
`
`
`
`
`PACKET
`SYNC
`SEOUENCER
`
`MANAGER
`INTERFACE
`
`DATA
`ASSEMBLY
`REGISTER
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`PACKET
`PROCESSING SUMMARY
`SEOUENCER
`2224
`2204
`
`
`
`
`
`
`
`STATUS
`
`
`
`PROTOCOL
`ANALYZER
`22O3
`
`DMA CONTROL
`22O6
`
`2225
`
`a -----
`SRAM
`CONTROLLER
`
`STATUS
`
`2223
`
`FIG. 22
`
`si-----2226
`DRAM
`CONTROLLER
`DATA
`
`2214
`
`-
`
`Alacritech, Ex. 2021 Page 21
`
`

`

`Patent Application Publication
`
`Apr. 1, 2004 Sheet 21 of 89 US 2004/0064578A1
`
`INIC 200
`
`230
`
`2306 2307
`
`-- 2302
`
`
`
`HOST 20
`DESTINATION
`(FILE CACHE)
`231
`
`MULTI-
`PACKET
`MESSAGE
`2300.
`
`
`
`N--
`
`2315
`
`TCP/IP
`
`--
`DATA
`w
`23 13
`
`2303
`
`Top IPI DATA
`2316
`
`2304
`4
`
`
`
`--
`2305
`A
`DATA
`
`
`
`TCP/IP
`
`FIG. 23
`
`A.
`
`Alacritech, Ex. 2021 Page 22
`
`

`

`Patent Application Publication
`
`Apr. 1, 2004 Sheet 22 of 89 US 2004/0064578A1
`
`FAST PATH
`
`Ethelmet
`
`PCI
`
`
`
`Alacritech, Ex. 2021 Page 23
`
`

`

`Patent Application Publication
`
`Apr. 1, 2004 Sheet 23 of 89 US 2004/0064578A1
`
`Command
`A G.
`
`
`
`Command buffers
`
`Response
`bie
`
`Alacritech, Ex. 2021 Page 24
`
`

`

`Patent Application Publication
`
`Apr. 1, 2004 Sheet 24 of 89 US 2004/0064578A1
`
`31
`|
`
`|
`
`|
`
`|
`
`|
`
`|
`
`|
`
`|
`
`O
`
`ERR
`RCW
`XMT
`
`RMISS
`
`Error bits are sent
`RCW has occured
`Command has been completed
`
`Rcy drop occured due to no buffers
`
`FIG. 27
`
`ISR
`0x0
`Interrupt Status
`IMR
`0x4
`Interrupt Mask
`HBAR
`0x8
`Header Buffer Address
`DBHR
`OxC
`Data Buffer Handle
`DBAR
`OX10
`Data Buffer Address
`CBARO
`0x14
`Command Buffer Address XMTO
`CBAR
`0x18
`Command Buffer Address XMTl
`CBAR)
`OX1C
`Command Buffer Address XMT2
`CBAR3
`0X20
`Command Buffer Address XMT3
`CBAR4
`0x24
`Command Buffer Address RCW
`RBAR
`Ox28
`Response Buffer Address
`N-y—-
`FIG. 28
`
`Alacritech, Ex. 2021 Page 25
`
`

`

`Patent Application Publication
`
`Apr. 1, 2004 Sheet 25 of 89 US 2004/0064578A1
`
`
`
`Alacritech, Ex. 2021 Page 26
`
`

`

`Patent Application Publication
`
`Apr. 1, 2004 Sheet 26 of 89 US 2004/0064578A1
`
`
`
`Example of incoming TCP pkt
`FIG. 32
`
`Example of incoming ARP Frame
`FIG. 33
`
`Alacritech, Ex. 2021 Page 27
`
`

`

`Patent Application Publication
`
`Apr. 1, 2004 Sheet 27 of 89 US 2004/0064578A1
`
`
`
`:
`
`a
`s
`
`Alacritech, Ex. 2021 Page 28
`
`

`

`Patent Application Publication
`
`Apr. 1, 2004 Sheet 28 of 89 US 2004/0064578A1
`
`
`
`Alacritech, Ex. 2021 Page 29
`
`

`

`Patent Application Publication
`
`Apr. 1, 2004 Sheet 29 of 89 US 2004/0064578A1
`
`
`
`SRAM requirements for the Receive and Transmit engines:
`
`TCB buffers
`Header buffers
`TCBhash index
`Timers
`DRAM Fifo queues
`
`256 bytes
`128 bytes
`16 bytes
`
`* 16
`* 16
`* 256
`
`128 bytes
`
`* 16
`
`4096
`2048
`4096
`128
`2048
`~12K bytes
`
`Alacritech, Ex. 2021 Page 30
`
`

`

`Patent Application Publication
`
`Apr. 1, 2004 Sheet 30 of 89 US 2004/0064578A1
`
`Summary of the main loop of Receive:
`
`forever {
`
`while there are any Receive events {
`if (a new event) {
`if (no new context available)
`ignore the event
`
`}
`call appropriate event handler to service the event,
`this may make a waiting proceSS runnable or Set up
`a new process to be run (get fee context, hddr buffer,
`TCB buffer, set the context up).
`
`}
`while any process contexts are runable {
`run them by jumping to the startresume address,
`if (process complete)
`fee the context
`
`N-
`
`- -
`FIG. 39
`
`Alacritech, Ex. 2021 Page 31
`
`

`

`Patent Application Publication
`
`Apr. 1, 2004 Sheet 31 of 89 US 2004/0064578A1
`
`Format of the SMB header of an SMB frame:
`
`31
`
`
`
`NetBIOS header
`
`SMB header
`
`of
`
`"s"
`
`"M"
`
`|
`
`"B"
`
`Reserved
`
`O
`
`--
`
`Boc
`
`Da.
`
`Notes (interesting fields):
`LENGTH
`17 bit Length of SMB message (0-128K)
`COM
`SMB command
`WCT
`Count (16 bit) of parameter words in WWW
`WWW
`Variable number of parameter Words
`BCC
`Bytes of data following
`N- - - -
`FIG. 40
`
`Alacritech, Ex. 2021 Page 32
`
`

`

`Patent Application Publication
`Apr. 1, 2004 Sheet 32 of 89 US 2004/0064578A1
`Summary of the main loop of Transmit
`
`forever {
`
`while there are any Transmit events {
`if (a new event) {
`if (no new context available)
`ignore the event,
`
`}
`cal appropriate event handler to service the event;
`this may make a Waiting process runnable or set up
`a new process to be run (get fee context, hddr buffer,
`TCB buffer, set the contextup).
`
`V
`}
`while any process contexts are runable {
`run them by jumping to the startresume address;
`if (process complete)
`free the context
`
`N-- -
`FIG. 41
`
`Alacritech, Ex. 2021 Page 33
`
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`

`Patent Application Publication
`
`Apr. 1, 2004 Sheet 33 of 89 US 2004/0064578 A1
`
`Bit 31-24 Byte enable 7-0. Only the low order four bits are
`valid for 32bit addressing mode.
`,
`, ,
`Bit 23. O Memory access
`1 Configuration access
`Bit 22 - 0 Read (to Host)
`1 Write (to Host)
`Data Walid
`Bit 21 - 1
`Bit 20- 16 Reserved
`Bit 15 - O Address
`
`--
`FIG. 42
`
`Configuration Space 1
`00
`04
`08
`OC
`10
`3C
`
`Configuration Space 2
`OO
`04
`08
`OC
`10
`3C
`
`SRAM Address Offset
`OO
`04
`08
`OC
`10
`14
`
`00
`18
`08
`1C
`20
`24
`
`N
`
`All other reads to configuration space will return 00,
`TTTTTTT -
`FIG. 43
`
`-
`
`Alacritech, Ex. 2021 Page 34
`
`

`

`Patent Application Publication
`
`Apr. 1, 2004 Sheet 34 of 89 US 2004/0064578A1
`
`Bit 0-0 10 accesses are not enabled
`Bit 1 - 1
`Memory accesses are enabled
`Bit 2 - 1
`Bus master is enabled
`Bit 3-0 Special Cycle is not enabled
`Bit 4 - 1
`Memory Write and Invalidate is enabled
`Bit 5-0 VGA palette Snooping is not enabled
`Bit 6-1 Parity checking is enabled
`Bit 7-0 Address data stepping is not enabled
`Bit 8 - SERR is enabled
`Bit 9 - O
`Fast back to back is not enabled
`
`FIG. 44
`
`Bit 5-1
`
`66 MHz capable is enabled. This bit will be set if the INIC
`Detects the system running at 66 MHz on reset
`User Definable Features is not enabled
`Bit 6-0
`Fast Back-to-Back slave transfers enabled
`Bit 7 - 1
`Parity Error enabled. This bit is initialized to 0
`Bit 8.1
`Bit 910 - 00 - Fast device select will be set if we are at 33 MHz
`01 - Medium device Select will be set if we are at 66 MHz
`Bit 11 - 1
`Target Abort is implemented. Initialized to 0.
`Bit 12 - 1
`Target Abort is implemented. Initialized to 0.
`Bit 13 - 1
`Master Abort is implemented. Initialized to 0.
`Bit 14 - 1
`SERRIt is implemented. Initialized to 0.
`Bit 15 - 1
`Parity error is implemented initialized to 0.
`
`FIG. 45
`
`Alacritech, Ex. 2021 Page 35
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`

`

`Patent Application Publication
`
`Apr. 1, 2004 Sheet 35 of 89 US 2004/0064578A1
`
`MIA
`
`MIB
`
`MIC
`
`MID
`
`XmtA
`&
`RCWA
`Seq
`
`XmB
`&
`RCWB
`Seq
`
`XmtC
`&
`RCVC
`Seq
`
`XmtD
`&
`RCWD
`Seq
`
`REGFILE
`8KWCS
`KIROM
`
`EXTERNAL
`MEMORY
`BUS
`
`PROC
`
`1 KBX 128 Sram
`& DMA Ctrl
`
`EXTERNAL
`MEMORY Ctrl
`
`PCI BUS
`INTERFACE UNIT
`
`PCI BUS
`
`FIG. 46
`
`Alacritech, Ex. 2021 Page 36
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`

`Patent Application Publication
`
`Apr. 1, 2004 Sheet 36 of 89 US 2004/0064578A1
`
`SPEED
`437 ns nom,
`640 ns nom,
`350 ns nom,
`500 ns nom,
`6.10 ns nom,
`
`DESCR
`MODULE
`lKx128 sport,
`Scratch RAM,
`8Kx49 sport,
`WCS,
`128x7 Sport,
`MAP,
`lKx49 32col,
`ROM,
`512x32 port,
`REGs,
`75 mm x 4 =
`MaCS,
`5 m =
`PLL,
`MISCLOGIC, 117260 gales (5035 gales 1 m =
`TOTAL CORE
`
`2
`(Core side)
`Core side
`Die side
`Die area
`
`Pads needed
`LSI PBGA
`
`= core side + 1.0 mm (10 cells)
`= 8.5 mm x 8.5 mm
`
`= 220 signals X 125 (VSS, Vdd)
`
`R
`
`AREA
`O6.7 m
`1829 m
`0.24 mm
`O45mm
`O349 mm
`O330mm
`O055mm
`2329 mm.
`562 mm
`
`2
`5622 mm
`07:50 mm
`08:50 mm
`7225mm
`
`275 pins
`272 pins
`
`N--
`FIG. 47
`
`Alacritech, Ex. 2021 Page 37
`
`

`

`Patent Application Publication
`
`Apr. 1, 2004 Sheet 37 of 89 US 2004/0064578A1
`
`(IOMB's IOOBase) x 2 (fill duplex) x 4 connections
`Average frame size
`Frame rate = 8OMB's 1512B
`Cpu Overhead? frame = (256B context read) + (64B header read) +
`(128B context write) + (128B misc)
`Total bandwidth = (512B in) + (512B Out) + (512B Cpu)
`Dram Bandwidth required = (1536B/fame) X (156250 frames's)
`Dram Bandwidth (a 6OMHz = (32 bytes/ 167ns)
`Dram Bandwidth (0) 66MHz = (32 bytes | 15Ons)
`PCI Bandwidth required
`PCI Bandwidth available (030 MHz, 32b, average
`PCI Bandwidth available (0.33 MHz, 32b, average
`PCI Bandwidth available (060 MHz, 32b, average
`PCI Bandwidth available (0) 66 MHz, 32b, average
`PCI Bandwidth available (030 MHz, 64b, average
`PCI Bandwidth available (0.33 MHz, 64b, average
`PCI Bandwidth available (060 MHz, 64b, average
`PCI Bandwidth available (0) 66 MHz, 64b, average
`N
`
`= 80 MB's
`= 512 B
`= 156250 frames Is
`
`= 512B / fame
`= 1536B? fame
`= 24OMB's
`= 202MB's
`= 224MBIs
`= 8OMB's
`= 46MBs
`= 50MB's
`= 92MBls
`=
`OOMB/s
`= 92MBS
`= 100MB's
`= 184MBls
`= 20OMB's
`
`l/
`
`FIG. 48
`
`Receive fame interval = 512B | 40MB's
`Instructions / fame (06OMHz = (128us fame) / (50ns instruction)
`instructions fame
`Instructions / fame (0.66MHz = (128uslframe) / (45nsinstruction)
`instructions fame
`Required instructions 1 frame
`N
`
`FIG. 49
`
`= 128us
`= 256
`
`= 284
`
`= 250 instructions/fame
`
`/
`
`Alacritech, Ex. 2021 Page 38
`
`

`

`Patent Application Publication
`
`Apr. 1, 2004 Sheet 38 of 89 US 2004/0064578A1
`
`* -?-?-?
`Sram LOADLOAD
`Ci Cil
`Cul
`
`;
`
`(in
`DNAdFETCHILOAD
`sil C.
`Cd
`
`LOAD LOAD
`C
`Ctrl
`
`FLAG
`DEC
`
`1 <
`
`:
`
`
`
`:
`
`
`
`
`
`
`
`din
`C
`
`Addr FILE | FF ALUIFLAG accr
`&
`BASED
`C
`Da CTXIREs CSIREGs
`:-
`K3
`Satch
`Sram
`
`FILE
`its at
`
`INSTRIFETCH
`REGAdi
`
`Sam DEBUG
`PC STAck Adar
`&BASE Addr
`
`NCR
`
`NCR
`
`ISIRTPOR
`
`OPERAND MULTIPLEXER
`
`LOAD
`
`C
`
`space
`FEAA All TSIA|||PM
`CIxoD cop ELSE loo" (" is at
`
`". ... e.
`
`&
`
`EXCHANGE
`
`NCR
`
`Cl
`
`ALU
`
`MUX
`
`HEALALTT|A
`CTXOUTCCs SEL RSLTSE IQAddr
`
`||RM||
`Cil
`
`"Is ASEl Adir
`
`FIG. 50
`
`Alacritech, Ex. 2021 Page 39
`
`

`

`Patent Application Publication
`
`Apr. 1, 2004 Sheet 39 of 89 US 2004/0064578A1
`
`INSTRUCTION-WORD FORMAT
`32:24-23:16) 15:00
`TYPE I55:49L (48:47, 146:42
`(41:33
`OpdBSel,
`TstSel, Literal
`Jcc
`Ob0000000
`Ob00, Alu0p, OpdASel,
`OpdBSel,
`FigSel, Literal
`Jmp Ob0000000
`0b01, AluOp, OpdaSel,
`OpdBSel,
`FlgSel, Literal
`Jsr
`Ob0000000
`Ob10, AluOp, OpdASel,
`OpdBSel,
`Ohff,
`Literal
`Rts
`Ob0000000
`Obl 1, AuCop, OpdASel,
`OpdBSel,
`FlgSel, Literal
`Nxt
`Ob0000000
`Ob11, Alu0p, OpdASel,
`Map Map Addr
`OBXX, OBXXXXX, OBXXXXXXXXX, OBXXXXXXXXX, OHXX, OHXXXX
`
`FIG 51
`
`Alacritech, Ex. 2021 Page 40
`
`

`

`Patent Application Publication
`
`Apr. 1, 2004 Sheet 40 of 89
`
`US 2004/0064578 Al
`
`SEQUENCER BEHAVIOR
`
`//re-map instr
`
`conditional jump
`
`if (MapEn& (MapAddr!= 0b0000000)){
`Stacke = Stackc;
`StackB = StackB;
`StackA = StackA;
`InstrAddr = 0h8000 | Pe[2:0] | (MapAddr<< 3);
`Pc = InstrAddr + (Execute & ~DbgMd);
`Fetch = DbgMd ? DbgAddr:InstrAddr;
`DbgAddr = DbgAddr + (Execute & DbgMd);}
`else if (PgmCtrl == Jec){
`Stacke = Stacke;
`StackB = StackB;
`StackA = StackA;
`InstrAddr = ~Tst@TstSel ? Pc:(AluDst==Pc) ? AluOut:Literal;
`Pc = InstrAddr + (Execute & ~DbgMd)
`Fetch = DbgMd ? DbgAddr:InstrAddr;
`DbgAddr = DbgAddr + (Execute & DbgMd);}
`else if (PgmCtrl == jmp){
`Stacke = Stacke;
`StackB = StackB;
`StackA = StackA;
`InstrAddr = (AluDst == Pc) ? AluOut: Literal;
`Pc = InstrAddr + (Execute & ~DbgMd)
`Fetch = DbgMd ? DbgAddr:InstrAddr;
`DbgAddr = DbgAddr + (Execute & DbgMd);}
`else if (PgmCtrl == Jsr){
`Stacke = StackB;
`StackB = StackA;
`StackA = Pc;
`InstrAddr = (AluDst == Pc) ? AluOut:Literal;
`Pe = InstrAddr + (Execute & ~DbgMd)
`Fetch = DbgMd ? DbgAddr:InstrAddr,
`DbgAddr = DbgAdadr+ (Execute & DbgMd);}
`
`/jump
`
`//yamp subroutine
`
`else if (FlgSel == Rts){
`InstrAddr = StackA;
`StackA = StackB;
`StackB = Stackc;
`Stacke = ErrVec;
`Pc = InstrAddr + (Execute & ~DbgMd)
`Fetch = DbgMd ? DbgAddr:InstrAddr;
`DbgAddr = DbgAddr + (Execute & DbgMd);}
`
`else
`
`{
`InstrAddr = Pe;
`StackA = StackA;
`StackB = StackB;
`Stackce = Stackc;
`Pc = InstrAddr + (Execute & ~DbgMd)
`Fetch = DbgMd ? DbgAddr:InstrAddr;
`DbgAddr = DbgAddr + (Execute & DbgMd);}
`
`//return subroutine
`
`//continue
`
`FIG. 52
`
`Alacritech, Ex. 2021 Page 41
`
`Alacritech, Ex. 2021 Page 41
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`

`

`Patent Application Publication
`
`Apr. 1, 2004 Sheet 41 of 89
`
`US 2004/0064578 Al
`
`-ALU OPERATIONS
`
`AluOp
`0b00000
`0b00001
`
`0b00010
`0b00011
`
`0b00100
`
`0b00101
`
`0b00110
`
`0b00111
`
`0b01000
`0b01001
`
`0b01010
`
`0b01011
`
`.
`
`0b01100
`
`0b01101
`
`0b01110
`
`0b01111
`
`
`
`OPERATION
`=@eo << B));
`Ca=
`= (B >= 32) ? 1:0;
`A=(A & B);
`'C=0; V=0;
`
`= yer & B);
`c =
`= 0;
`A = (~Literal & B);
`C=0; V=0;
`
`A=(Ayf(1 << B));
`C= 0; V=(B >= 32) ? 1:0;
`
`A=(A|B);
`C=0; V=0;
`
`A = (Literal| B);
`C=0; V=0;
`
`A = (~Literal| B);
`C=0; V=0;
`
`for (i=31; i>=0;nO:ifB[i] continue; A=i;
`C=0; V= (B) ?
`A= AB)
`
`C=0; V=0;
`
`A = ({Literal} * B);
`C=0; V=0;
`
`A = ({~Literal} * B);
`C=0; V=0;
`
`A=B;
`C=0; V=0;
`
`A = B(31:24] * B[23:16] * B[15:08] * B[07:00]
`C=0; V=0;
`
`A = {B[23:16],B[3 1:24],B[07:00],B[15:08]};
`C=0; V=0;
`A
`Bl15:00], B[31:16]};
`Cc
`= 0;
`
`//bit clear
`
`.
`
`/Mogical and
`
`/Nogical and
`
`/Nogical and not
`
`//bit set
`
`/Nogical or
`
`/Nogical or
`
`/Nogical or not
`
`/fpriority enc
`
`/Nogical xor
`
`/Nogical xor
`
`/Nogical xor not
`
`/Imove
`
`//hash
`
`/Iswap bytes,
`
`//swap doublets
`
`FIG. 53
`
`Alacritech, Ex. 2021 Page 42
`
`Alacritech, Ex. 2021 Page 42
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`

`

`Patent Application Publication
`
`Apr. 1, 2004 Sheet 42 of 89
`
`US 2004/0064578 Al
`
`AluOp
`
`0b10000
`
`0b10001
`
`0b10010
`
`0b10011
`
`0b10100
`
`0b10101
`
`0b10110
`
`0b10111
`
`0b1 1000
`
`0b11001
`
`0b11010
`
`0b11011
`
`0b11100
`
`0b11101
`
`0b11110
`
`Ob11111
`
`FUNCTIONI
`
`Madd B
`
`//add B, carry
`
`//add constant
`
`//sub constant
`
`//sub B
`
`//sub B, borrow
`
`//sub A
`
`//sub A, borrow
`
`//shift left A
`
`//shift left B
`
`//shift left B
`
`//compare
`
`//shift right A
`
`//shift right B
`
`//shift right B
`
`//compare
`
`A=(A+B);
`C =(A + B)[32]; V=0:
`
`A=(A+B+C);
`C=(A+B+ C32]; V =0:
`‘ = (Literal + B);
`= (Literal + B)[32]; V = 0;
`A= (-Literal + B);
`C = (-Literal + B)[32]; V = 0;
`
`A= (A -B);
`C = (A - B)[32]; V = 0:
`
`A +B);
`+ B)[32]; V = 0;
`
`A=(A-B-~C);
`C=(A -B-~C)[32]; V=0;
`c (-A
`ll1 (-
`A=(-A+B-~C);
`C=(-A+B-~C)[32]; V =0:
`A= (A <<B):
`C= A[31]; V =(B>= 32) 20:1;
`
`A= (B << Literal);
`C= B[31]; V = (Literal >= 32) ? 0:1;
`
`A=(B<< 1);
`C= B31]; V=
`
`n=(A -B);
`C=(A-B)[32]; V=0:
`
`A=(A>>B);
`C= A[0]; V=(B>= 32) ? 1:0;
`
`= (B >> Literal);
`C= A[0]; V = (Literal >= 32) ? 1:0;
`
`A= (B>> 1);
`C= A[0]; V=0;
`n=(B- A);
`=(B - A)[32]; V =0;
`
`FIG. 54
`
`Alacritech, Ex. 2021 Page 43
`
`Alacritech, Ex. 2021 Page 43
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`

`

`Patent Application Publication
`
`Apr. 1, 2004 Sheet 43 of 89 US 2004/0064578A1
`
`OpdSel
`
`SELECTED OPERANDS
`
`Ob00.00aaaaa
`
`Fie
`
`Ob000 laaaaa
`
`CpuReg
`
`Ob001XXXXXX reserved
`Ob0100000XX Cpustatus
`
`OOOOOOXX reserved
`OOOOOOXX PC
`
`Ob0100011XX DbgAddr
`
`File(a)(OpdSel4:0 FileBase);
`Allows paged access to any part of the register file.
`File(a){2'bll, Cpuld, OpdSel4:0};
`Allows direct access to Cpu specific registers.
`Reserved for future expansion.
`Ob0000000000000BHOOOOOOOOOOOOOOOCC
`This is a read-only register providing information about the Cpu executing
`(OpdSell:0) cycles after the current cycle. "CC" represents a value
`indicating the Cpu. Currently, only Cpuld values of 0, and 2 are returned.
`"H" represents the current state of Hlt, "D" indicates DbgMd and "B"
`indicates Big Md. Writing this register has no effect.
`Reserved for future expansion.
`0x0000AAAA
`Writing to this address causes the program control logic to use Alu0ut as the
`new Pc value in the event of a Jmp, Jcc or Jsr instruction for the Cpu
`executing during the current cycle. If the current instruction is Nxt, Map, or
`Rts, the register write has no effect. Reading this register returns the value in
`Pc for the Cpu executing (OpdSell:0) cycles after the current cycle.
`OXOOOOAAAA
`Writing to this register alters the contents of the debug address register
`(DbgAddr) for the Cpu executing (OpdSell:0) cycles after the current
`cycle. DbgAddr provides the fetch address for the control-store when
`DbgMd has been selected and the Cpu is executing. DhgAddr is also used
`as the control-store address when performing a WrWes(a)DbgAddr or
`RdWes(adbgAddr operation. “D represents bit 31 of the register. It is a general
`purpose flag that is used for event indication during simulation. Reading this
`register returns a value of 0x00000000.
`
`Reserved for future expansion.
`Ob000 XXXX reserved
`Ob010100000
`RamAddr (Ob1CCC, 0x000, Obl, AAAA}
`RanAddr - AluOut 15? AluOut: (Au0ut RamBase);
`PrevCC = Aluout 31)? CCC : AlucC;
`A read/write register. When reading this register, the Alu condition codes from the previous
`instruction are returned together with RamAddr.
`bit
`description
`3.
`Always 1.
`30
`Previous Alu Carry.
`29
`Previous Alu Overflow.
`28
`Previous Alu Zero.
`27:6
`Always 0.
`15
`Always 1.
`Ran Addr
`14:0
`Contents of last Sram address used.
`When writing this register, if alu out 31) is set, the previous condition codes will be overwritten with
`bits 30:28 of AluOut. If Aluout 15 is set, bits 14:0 will be written to the RamAddr. If Aluout 15
`is not set, bits 14:0 will be ored with the contents of the Ram Base and written to the Ram Addr
`
`PreyC
`Prey V
`Prey,
`
`FIG 55
`
`Alacritech, Ex. 2021 Page 44
`
`

`

`Patent Application Publication
`
`Apr. 1, 2004 Sheet 44 of 89 US 2004/0064578A1
`
`OpdSel
`ObO1 010000
`
`Ob0 1 0 1 0000
`
`Ob010100011
`
`ObOOOOOO
`
`Ob01 0100101
`
`Ob010100110
`
`SELECTED OPERANDS
`AddrRegA
`0x0000AAAA
`AddrRegA = Alu0ut;
`A read/write operand which loads. AddrRegA used to provide the address for read and write
`operations. When AddrRegA15 is set the contents will be presented directly to the ram. When
`AddrregA15 is reset, the contents will first beored with the contents of the RamBase register
`before presentation to the fa). YEE to this register takes priority over Literal loads using
`FlgOp. Reading this register returns the current value of the register.
`AddrRegB 0x0000AAAA
`AddrrcgB = Alu0ut;
`A read/write operand which loads AddrRegB used to provide the address for read and write
`operations.
`RE AddrRegB15) is set, the contents will be presented directly to the ram. When
`AddrRegb(151 is reset, the contents will first be ored with the contents of the Ram Base
`register before presentation to the ram. Writing to this SS takes priority over Literal loads
`using Flg.0p. Reading this register returns the current value of the register.
`AddrRegAb
`0x0000AAAA
`AddrRegA = AluOut; Addregb = Alu0ut;
`A destination only operand which loads Addregs and AddregA used to provide the address
`for read and write, operations Writing to this registertakes priority over Literal loads using
`Flg.0p. Reading this register returns the value 0x00000000.
`Ram Base
`0x0000AAAA
`RamBase - Au0ut;
`A read/write register which provides the base address for ran read and write cycles. When
`Ram Addr15) is set, the contents will not be used. When RamAddr15 is reset, the contents
`will first be ored with the contents of the Ram Base register before presentation to the ram.
`Reading this register returns the value for the current Cpu.
`File:Base
`Ob00000000000000000000000AAAAAAAAA
`FileBase - Alu(Out:
`FileAddr = OpdSei8 ? OpdSel:(OpdSel + FileBase);
`A read/write register which provides the base address for file read and write cycles. When
`ESS is set, the contents will not be used and OpdSel will be presented directly to the
`address lines of the file. When 9p St. is reset, the contents will first beored with the
`contents of the FileBase register before presentation to the file. Reading this register returns the
`value for the current Cpu.
`Instreg
`0xIIII IIII
`This is a read-only register which returns the contents of InstrReg31:0). Writing to
`this register has no effect.
`
`Ob0 1 0 1 00111
`
`0x00IIIII
`InstrRegH
`This is a read-only register which returns the contents of InstrReg55:32). Writing to this
`register has no effect.
`
`FIG. 56
`
`Alacritech, Ex. 2021 Page 45
`
`

`

`Patent Application Publication
`OpdSel
`SELECTED OPERANDS
`
`Apr. 1, 2004 Sheet 45 of 89 US 2004/0064578A1
`
`Ob010 1 0 1 000
`
`Minus1
`
`Oxffffffff
`This is a read-only register which supplies a value 0xffffffff. Writing to this
`register has no effect.
`
`Ob010101001
`
`FreeTime
`
`Afree-running timer with a resolution of 1.00 microseconds and a maximum count
`of 71 minutes. This timer is cleared during reset.
`
`Ob010101010
`
`LiteraL
`
`Instr15:0)
`A read-only register. Writing to this register has no effect
`
`Ob01010101
`
`Literal H
`
`Instr15:0<<16;
`A read-only register. Writing to this register has no effect
`
`Ob0 01000
`
`MacData - Writing to this address loads the AluOut data into the MacData register for usc
`during Mac operations. The Mac operation, resulting from writing to the MacOp register,
`determines the definition of the MacData register contents as follows.
`MacOp.
`Mstop
`
`MacData definition
`ObXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
`MacData is not used for the StopM operation.
`hrstl, rsvd, rsvd, creen, fulld, hrstl, hugen, nopre, paden, prty, xdl10,
`ipgr16:0,
`ipgr26:0), ipgt0:0).
`Loads the MacCfg register with the contents of the MacData register. Refer to
`LSI Logic's Ethernet-1 10 Core Technical Manual for detailed definitions ofthese
`bits.
`
`WrMcfg
`
`WrMrng
`
`Rd Phy
`
`WrPhy
`
`ObXXXXXXXXXXXXXXXXXXXXXSSSSSSSSSSS
`Loads seed 10:0 into the Mac's random number generator.
`
`ObXXXXRRRRXXXXPPPPXXXXXXXXXXXXXXXX
`Reads registcrR) of phyP).
`
`ObXXXXRRRRXXXXPPPPDDDDDDDDDDDDDDDD
`Writes register R of phyP with MacData 15:0).
`
`Reading this register returns prsd15:0) of MacO which contains phy status data returned to the
`Mac at the completion of a Rd Phy command. This data is invalid while MacBsy is asserted
`as a result of a Rd Phy command. Refer to the appropriate phy technical manual for a
`definition of the phy register contents.
`
`FIG. 57
`
`Alacritech, Ex. 2021 Page 46
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`

`Patent Application Publication
`
`Apr. 1, 2004 Sheet 46 of 89 US 2004/0064578A1
`
`
`
`FIG. 58A
`
`FIG. 58
`
`Alacritech, Ex. 2021 Page 47
`
`

`

`Apr. 1, 2004 Sheet 47 of 89 US 2004/0064578A1
`Patent Application Publication
`OpdSel
`SELECTED OPERANDS
`
`Ob010101101
`
`0xXXXXX1XM
`
`MacOp - A write only register. Writing to this address loads the MacSel register and staRts
`execution of the specified operation as follows.
`AuCut
`description
`0xXXXXXOXM
`Mstop - Halts execution of a MacOp for MacM). The user must wait for
`MacBsy to be deasserted before issuing another command or changing the
`contents of MacData.
`WrMcfg - Writes the contents of MacData to the MacCfg register of MacM
`The user must wait for MacBsy to be deasserted before issuing another command
`or changing the contents of MacData.
`WrMring - Writes the contents of MacData to the seed register of MacM). The
`user must wait for MacBsy to be deasserted before issuing another command or
`changing the contents of MacData.
`Rd Phy-Reads the contents of regR) for phyP) on the MII management bus of
`MacM). The contents may be read from MacData after MacBsy has been de
`asserted.
`WrPhy - Writes the contents of MacData 15:0 to e regR) of phyP on the MII
`management bus of MacMJ. The user must wait for MacBsy to be deasserted
`bcfore issuing another command or changing the contents of MacData.
`0xXXXXX8XM
`WrAddra L - Writes the contents of MacData15:0 to MacAddra 15:0 for MacM).
`0xXXXXX9XM WraddrAH-Writes the contents of MacDatal 1:0 to MacAddra47:16 for MacM).
`OxXXXXXaXM WraddrBL - Writes thc contents of MacData 15:0 to MacAddrb (15:0) for MacM).
`0xXXXXXbXM WraddrbH - Writes the contents of MacData 11:0) to MacAddrB47:16) for MacM).
`
`0xXXXXX2XM
`
`OxXXXXX3XM
`
`0xXXXXX4XM
`
`b010101110 ChCmd
`
`A write-only register.
`
`name
`bit
`31:11 reserved
`10:8 command
`
`07:05 reserved
`04:00 Chd
`
`description -
`Data written to thcsc bits is ignored.
`0 - Stops execution of the current operation and clears the
`corresponding event flag.
`1 - Transfer data from ExtMem to ExtMem.
`2 - Transfer data from Poito ExtMem.
`3 - Transfer data from ExtMem to Poi.
`4 - Transfer data from Sram to ExtMem.
`5 - Transfer data from ExtMem to Sram.
`6 - Transfer data from Poito Sram.
`7 - Transfer data from Sram to Poi.
`Data written to these bits is ignored.
`Provides the channel number for the channel command.
`
`FIG. 58A
`
`Alacritech, Ex. 2021 Page 48
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`Patent Application Publication
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`Apr. 1, 2004 Sheet 48 of 89 US 2004/0064578A1