United States Patent [19J
`Noble, Jr et al.
`
`[54] MOSFET WITH RAISED STI ISOLATION
`SELF-ALIGNED TO THE GATE STACK
`
`[75]
`
`Inventors: Wendell P. Noble, Jr, Milton, Vt.;
`Ashwin K. Ghatalia; Badih El-Kareh,
`both of Hopewell Junction, N.Y.
`
`[73] Assignee: International Business Machines
`Corporation, Armonk, N.Y.
`
`[21] Appl. No.: 365,729
`
`[22] Filed:
`
`Dec. 28, 1994
`
`[51]
`
`Int. Cl.6
`
`........................... H01L 27/08; HOlL 29176;
`HOlL 29/00
`[52] U.S. Cl . .......................... 257/301; 257/305; 257/397;
`257/623
`[58] Field of Search ..................................... 257/301, 304,
`257/305, 395, 396, 397, 398, 383, 385,
`586,587,619,623,384
`
`[56]
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`3,936,859
`4,688,069
`5,173,439
`5,264,716
`
`211976 Dingwall ................................. 257/396
`8/1987 Joy ct a!. ................................ 257/398
`1211992 Dash ct a!. ................................ 437/67
`11/1993 Kenney ................................... 257/301
`
`1111111111111111111111111111111111111 1111111111 IIIII 11111111111 11111111 1111
`US005539229A
`[llJ Patent Number:
`[45] Date of Patent:
`
`5,539,229
`Jul. 23, 1996
`
`FOREIGN PATENT DOCUMENTS
`
`Japan ..................................... 257/396
`55-154767 12/1980
`Japan ..................................... 257/384
`811991
`3-191574
`OTHER PUBLICATIONS
`T. Furukawa et al., "Process and Device Simulation of
`Trench Isolation Comer Parasitic Device", Proceedings of
`the Electrochemical Society Meeting, Oct. 9-14, 1988.
`A. Bryant et al., "The Current-Carrying Comer Inherent to
`Trench Isolation", IEEE Electron Device Letters, vol. 14,
`No. 8, Aug. 1993.
`D. Foty et al., "Behavior of an NMOS Trench-Isolated
`Comer Parasitic Device at Low Temperature", Proceedings
`of the Electrochemical Society Meeting, Oct. 1989.
`T. Ishijima et al., "A Deep-Subrnicron Isolation Technology
`with T -shaped Oxide (TSO) Structure", Proceedings of the
`IEDM, 1990, p. 257.
`Primary Examiner-Donald L. Monin, Jr.
`Attorney, Agent, or Firm-James M. Leas
`ABSTRACT
`[57]
`
`A semiconductor structure comprising a transistor having a
`gate conductor that has first and second edges bounded by
`raised isolation structures (e.g. STI). A source diffusion is
`self-aligned to the third edge and a drain diffusion is
`self-aligned to the fourth edge of the gate electrode.
`
`19 Claims, 5 Drawing Sheets
`
`30 -
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`Global Foundaries US v. Godo Kaisha
`Global Ex. 1015
`
`Page 1 of 10
`
`

`

`U.S. Patent
`
`Jul. 23, 1996
`
`Sheet 1 of 5
`
`5,539,229
`
`Vr CHANNEL
`
`IMPLANT
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`Page 2 of 10
`
`

`

`U.S. Patent
`
`Jul. 23, 1996
`
`Sheet 2 of 5
`
`5,539,229
`
`30 -
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`Page 3 of 10
`
`

`

`U.S. Patent
`
`Jul. 23, 1996
`
`Sheet 3 of 5
`
`5,539,229
`
`42
`
`46
`
`38
`
`14
`
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`39
`
`FIG. 7
`
`14
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`
`Page 4 of 10
`
`

`

`U.S. Patent
`
`Jul. 23, 1996
`
`Sheet 4 of 5
`
`5,539,229
`
`FIG. 9
`
`Poly-implant
`
`lQ
`
`Implant medium dose source/drain
`
`~
`
`+
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`+
`150
`140
`116
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`FIG. 11
`
`Page 5 of 10
`
`

`

`U.S. Patent
`
`Jul. 23, 1996
`
`Sheet 5 of 5
`
`5,539,229
`
`FIG. 12
`
`FIG. 13
`
`Page 6 of 10
`
`

`

`5,539,229
`
`1
`MOSFET WITH RAISED STI ISOLATION
`SELF-ALIGNED TO THE GATE STACK
`
`FIELD OF THE INVENTION
`
`This invention generally relates to semiconductor isola(cid:173)
`tion techniques. More particularly, it relates to shallow
`trench isolation (STI) in which the insulating material is
`raised above the surface of the semiconductor. Even more
`particularly it relates to an isolation structure for a transistor
`in a DRAM cell that provides reduced leakage.
`
`BACKGROUND OF THE INVENTION
`
`2
`This comer leakage problem has commonly been con(cid:173)
`trolled with an increased threshold tailor implant dose, but
`this can degrade device performance. Thus, alternate
`schemes for controlling the comer are needed.
`A paper, "A Deep-Submicron Isolation Technology with
`T-shaped Oxide (TSO) Structure," by T. Ishijima et al.,
`Proceedings of the IEDM, 1990, p. 257, addresses the
`problem of trench sidewall inversion. This paper teaches the
`use of a pair of aligned photomasks to form aT-shaped oxide
`10 adjacent the comer of an isolation trench and the use of a
`channel stop boron implant along sidewalls of the trench.
`The structure moves the device away from the trench
`sidewall and provides boron to raise the Vt along that
`sidewall. However, isolation is enlarged when photomask
`15 alignment tolerances are included in this two-mask-and(cid:173)
`implant scheme, making this solution undesirable. While
`commonly assigned copending patent application, "A
`Comer Protected Shallow Trench Isolation Device," by M.
`M. Armacost eta!., provides a scheme to protect the comer
`20 while not enlarging the isolation, the root problem of comer
`sharpening and oxide thinning remains. Thus, an improved
`means to control the corner parasitic is needed and is
`provided by the following invention.
`
`SUMMARY OF THE INVENTION
`
`30
`
`Contemporary CMOS technologies employ field effect
`transistors that are adjacent or bounded by trenches. The
`trenches arc used for shallow trench isolation (STI) or they
`provide a location for trench capacitors.
`Parasitic leakage paths have been created by the proxim(cid:173)
`ity of a semiconductor device to an edge or corner of either
`type of trench. In one leakage mechanism, described in a
`paper, "Process and Device Simulation of Trench Isolation
`Corner Parasitic Device," by T. Furukawa and J. A. Man(cid:173)
`delman, Proceedings of the Electrochemical Society Meet- 25
`ing, Oct. 9-14, 1988, the parasitic leakage path results from
`an enhancement of the gate electric field near the trench
`corner. The electric field is enhanced by the corner's small
`radius of curvature and the proximity of the gate conductor.
`Processing can exacerbate the problem by sharpening the
`corner and thinning the gate dielectric near the corner. In
`addition, in a worst case scenario for corner field enhance(cid:173)
`ment, the gate conductor wraps around the trench comer.
`This happens when the oxide fill in the isolation trench is
`recessed below the silicon surface during oxide etches 35
`following its formation.
`As a result of the enhanced field, the corner has a lower
`threshold voltage (Vt) than the planar portion of the device.
`Thus, a parallel path for current conduction is formed.
`However, for device widths used in contempora W technolo(cid:173)
`gies, the top planar portion of the device carries most of the
`on-current. Trench corner conduction is a parasitic which
`usually contributes appreciably only to sub-threshold leak(cid:173)
`age. This parasitic leakage current along the corner is most 45
`easily seen as a hump in the subthreshold current curve of a
`narrow MOSFET.
`As described in a paper, "The Current-Carrying Comer
`Inherent to Trench Isolation," by Andres Bryant, W. Haen(cid:173)
`sch, S. Geissler, Jack Mandelman, D. Poindexter, and M.
`Steger, IEEE Electron Device Letters, Vol. 14, No. 8,
`August, 1993, the corner device can even dominate on(cid:173)
`currents in applications such as DRAM that require narrow
`channel widths to achieve high density. This parallel current(cid:173)
`carrying comer device becomes the dominant MOSFET
`contributor to standby current in low standby power logic
`applications and to leakage in DRAM cells. Furthermore,
`there exists concern that the enhanced electric fields due to
`field crowding at the comer impact dielectric integrity.
`A paper, "Behavior of an NMOS Trench-Isolated Comer
`Parasitic Device at Low Temperature," by D. Foty, J. Man(cid:173)
`delman, and T. Furukawa, Proceedings of the Electrochemi(cid:173)
`cal Society Meeting, October, 1989, suggests that the comer
`parasitic device does not improve with decreasing tempera(cid:173)
`ture nearly as much as the planar subthreshold slope. Thus,
`the comer parasitic device may be more of a problem at low
`temperature than the planar device.
`
`It is therefore an object of the present invention to avoid
`comer leakage without degrading device performance.
`It is another object of the present invention to prevent the
`gate conductor from wrapping around the trench comer.
`It is another object of this invention to avoid gate dielec(cid:173)
`tric thinning adjacent the corner.
`It is another object of this invention to avoid sharpening
`of the corner.
`It is a further object of the present invention to provide a
`transistor with an individual segment gate conductor and a
`spacer rail gate connector formed on a separate wiring level.
`It is a further object of this invention that the gate
`40 conductor is confined to the active device area and the
`isolation is self-aligned to the gate conductor.
`It is a further object of the present invention to provide a
`wiring level interconnecting individual gate segments of the
`transistors of an array wherein the wiring level is a sub(cid:173)
`minimum dimension conductive spacer rail.
`These and other objects of the invention are accomplished
`by a semiconductor structure comprising a transistor with a
`gate comprising an individual segment of gate conductor on
`thin dielectric. The gate conductor is substantially coexten(cid:173)
`sive with the thin dielectric. The gate conductor has a top
`surface having opposed first and second edges and opposed
`third and fourth edges. Raised isolation bounds the first and
`second edges of the gate conductor. A source is self-aligned
`to the third edge and a drain is self-aligned to the fourth
`edge. A conductive wiring level is in contact with the top
`surface.
`Another aspect of the invention provides a method of
`forming an FET comprising the steps of providing a sub-
`60 strate having a gate stack comprising a layer of gate dielec(cid:173)
`tric and a layer of gate conductor, the gate stack having a top
`surface; removing first portions of the gate stack and etching
`a trench in the substrate thereby exposed for raised isolation;
`depositing insulator and planarizing to the top surface of the
`65 gate stack; removing second portions of the gate stack for
`source/drain regions and to expose sidewalls of the gate
`stack adjacent the source/drain regions; forming spacers
`
`50
`
`55
`
`Page 7 of 10
`
`

`

`5,539,229
`
`3
`adjacent the exposed sidewalls of the gate stack; and form(cid:173)
`ing source/drain diffusions in exposed portions of the
`source/drain regions.
`These and other objects, features, and advantages of the
`invention will become apparent from the drawings and 5
`description of the invention.
`
`10
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The foregoing and other objects, features, and advantages
`of the invention will be apparent from the following detailed
`description of the invention, as illustrated in the accompa(cid:173)
`nying drawings, in which:
`FIGS. 1-8 are cross sectional views showing the structure
`at several steps in the process for making a semiconductor
`structure of a first aspect of the present invention; and
`FIGS. 9-13 are cross sectional views showing the struc(cid:173)
`ture at several steps in the process for making a semicon(cid:173)
`ductor structure of a second aspect of the present invention.
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`
`4
`thermally grown or deposited. Next a layer of gate conductor
`16 is blanket deposited. Gate conductor 16 is formed of
`polysilicon. It can be in-situ doped during the deposition or
`it can be implanted after deposition to provide the appro(cid:173)
`priate gate doping. Finally, blanket Si3N4 cap 18 is deposited
`on top of the gate conductor 16 to a thickness suitable for use
`as a planarization etch stop layer.
`In the next step, photoresist is applied, exposed, and
`developed to define areas in which the trenches will be
`formed. The trenches can be STI or storage capacitors. This
`pattern is first etched in gate cap dielectric 18. The resist may
`then be stripped, and the pattern in nitride gate cap dielectric
`18 is used to continue the etch in gate conductor 16 and
`exposed gate dielectric 14. Finally, the etch is extended into
`15 silicon substrate 10 to form raised deep trench 20 for a
`capacitor, as shown in FIG. 2, or raised shallow trench 30 for
`STI, as illustrated in FIG. 4. The term "raised trench" refers
`to the fact that the trench extends beyond the surface of
`substrate 10 to the top of the gate stack. In this process, a
`20 single masking step defines the edge between the trench and
`gate stack and provides perfect alignment therebetween.
`Thus, the gate is bounded by a raised trench on two opposite
`sides. However, since the gate dielectric and gate conductor
`were formed as blanket layers before the trench was etched,
`there is no comer sharpening, no gate dielectric thinning,
`and no gate wrap around.
`As shown in FIG. 3, storage node insulator 22 and storage
`electrode 24 are formed in raised deep trench 20 as described
`in commonly assigned U.S. Pat. No. 5,264,716 ("the '716
`patent"), issued to D. M. Kenney, entitled "Diffused Buried
`Plate Trench Dram Cell Array," incorporated herein by
`reference. In brief, storage node insulator 22 is a formed by
`growing thermal oxide, depositing silicon nitfide, and oxi(cid:173)
`dizing a surface layer of the nitfide. Raised deep trench 20
`is then filled with doped polysilicon for storage electrode 24
`of the capacitor. This polysilicon may be recessed to form
`insulating collar 26. FIG. 3 illustrates the cell at this step in
`the process.
`In a similar process to that described above for the raised
`deep trench, raised shallow trench isolation (raised STI) 30
`is formed. Referring to FIG. 4, after the photomasking and
`gate stack etching steps as described above, a silicon etch is
`used in silicon substrate 10 to form shallow trenches for
`raised STI 30. Then a passivation oxide is thermally grown
`along surfaces of the silicon thereby exposed. TEOS is then
`deposited to fill the shallow trenches (and the top of deep
`trench 20). Next, a planarization step is implemented stop(cid:173)
`ping on the nitfide cap of the gate stack. Thus, raised STI is
`provided adjacent a sidewall of the gate stack. Of course,
`raised STI 30 can intersect deep trench 20 in a manner
`similar to that shown for standard STI in the '716 patent.
`Next, source/drain regions of the active area are defined
`using a process similar to that described above for raised
`deep trench 20 and raised STI 30. Referring to FIG. 5, a
`cross section orthogonal to the cross section of FIG. 4,
`photomasking and gate stack etching steps as described
`above are used to form the desired pattern of gate segments
`32. This etch leaves polysilicon only over channel region 34,
`on which there is gate dielectric 14, and defines the channel
`length of the transistor in the process of being fabricated.
`Silicon on the two sides of the gate stack thereby exposed
`will be diffused for the source/drain. The other two sides of
`the gate stack are bounded by raised storage trench 20 or
`raised STI 30.
`In the next step, illustrated in FIG. 6 dielectric sidewall
`spacers 36 are grown or deposited on the two exposed edges
`
`25
`
`The present invention provides a transistor having a gate
`formed from an individual segment of gate conductor. The
`gate conductor is confined to the active device area, that is
`the region having thin gate dielectric. STI is self-aligned to
`the gate conductor. Gate dielectric and gate conductor are
`formed as blanket layers on the wafer before the isolation
`trench is etched, and hence sharpening of the comer and 30
`thinning of the gate dielectric are avoided. A conductive
`wiring level contacts this segment gate, and the wiring level
`can have a subminimum dimension as a result of being
`formed by a directional etch of a conductor along a sidewall.
`STI and processes for forming STI are described in 35
`commonly assigned U.S. Pat. No. 5,173,439, by Dash eta!.,
`incorporated herein by reference.
`The term "horizontal" as used in this application is
`defined as a plane parallel to the conventional planar surface 40
`of a semiconductor chip or wafer, regardless of the orien(cid:173)
`tation the chip is actually held. The term "vertical" refers to
`a direction perpendicular to the horizontal as defined above.
`Prepositions, such as "on," "side," (as in "sidewall"),
`"higher," "lower," "over," and "under" are defined with
`respect to the conventional planar surface being on the top
`surface of the chip or wafer, regardless of the orientation the
`chip is actually held.
`Single crystal semiconducting wafers used in the process
`steps illustrated in FIGS. 1-13 are formed from materials
`such as silicon, germanium, and gallium arsenide. Because
`silicon is most widely used and the most is known about its
`etch properties, silicon will be used for illustration herein(cid:173)
`below. The wafer may have had implants, diffusions, oxi(cid:173)
`dations, and other process steps completed before embark- 55
`ing on the process sequences described hereinbelow.
`FIGS. 1-8 show steps in the process of fabricating a
`transistor or a DRAM cell according to one aspect of the
`present invention. Referring now to FIG. 1, a "blanket" Vt
`channel implant is performed on substrate 10 in a region that 60
`may encompass an extended portion of the chip or substan(cid:173)
`tially the entire chip. If an array of devices is being formed,
`for example, the region of the blanket implant encompasses
`substantially the entire area of the array. Then gate stack 12
`is formed in the same region from a sequence of layers, 65
`including gate dielectric 14, gate conductor 16, and gate cap
`dielectric 18. First, a layer of blanket gate dielectric 14 is
`
`45
`
`50
`
`Page 8 of 10
`
`

`

`5,539,229
`
`25
`
`5
`of gate stack 32. Spacers 36 are typically formed of a
`thermally grown oxide along sidewalls of gate conductor 16
`and a deposited silicon nitride that is directionally etched to
`remove nitride along horizontal surfaces while leaving
`nitride spacers along sidewalls. After spacers 36 arc formed, 5
`source/drain regions 38 of transistor 39 are formed by
`difTusion or ion implant. The diffusion or implant is self(cid:173)
`aligned to spacers 36 formed along edges of gate stack 32
`and is bounded by raised STI 30 or raised storage trench 20.
`The diffusion for source/drain regions 38 may be provided 10
`by depositing a doped glass or a doped polysilicon layer. The
`doped layer is planarized, and may be masked and etched to
`define the NMOS and PMOS regions. Wafers are then
`subjected to an activation, drive-in thermal cycle. Diffused
`regions or the doped polysilicon can be silicided to lower
`resistance. The use of doped polysilicon as a doping source 15
`for source/drain regions 38 provides the advantage of allow(cid:173)
`ing the formation of shallow junctions while providing a
`large volume of material for source/drain regions 38. The
`shallow junctions reduce short channel effects. The large
`volume of material allows siliciding without danger of high 20
`junction leakage.
`The next steps provide a node strap, wordlinc connector,
`and bitline contact, and these steps are described in copend-
`ing patent application "A Five Square Folded-Bitline
`DRAM Cell," by Wendell Noble, ("the Noble patent appli(cid:173)
`cation") incorporated herein by reference. Briefly, an intrin-
`sic polysilicon mandrel is deposited and a contact opening
`formed therein. Heavily doped polysilicon is then deposited
`forming the strap between node polysilicon and the node
`diffusion. A selective etch is then used to remove the
`intrinsic polysilicon, leaving the heavily doped strap.
`Subminimum dimension wordlinc interconnect wiring 40
`is formed as a spacer along sidewall 42 of groove 44 in
`second intrinsic polysilicon mandrel 46, as illustrated in
`FIGS. 7 and 8. Alter insulator 48 is deposited and planarized,
`stopping on cap 18, intrinsic polysilicon mandrel 46 is
`deposited (FIG. 7). Groove 44 in mandrel 46 is formed
`photolithographically aligned so that sidewall 42 extends
`over a portion of gate conductor 16. The etch to form groove
`44 extends through mandrel 46 down to expose nitride cap
`18 over gate segment. A directional etch removes the portion
`of nitride cap 18 from gate conductor 16 that is exposed
`within groove 44. A conductor, such as tungsten, aluminum,
`or doped polysilicon is deposited and directional etched, 45
`leaving subminimum dimension conductive sidewall spacer
`rail 40 contacting gate conductor 16 along sidewall 42 (FIG.
`8).
`FIGS. 9-13 show steps an alternate aspect of the inven(cid:173)
`tion in which conductive wiring level140 interconnects gate
`segments 132 of transistor 139 that is isolated by raised STI
`30. Transistor 139 may be part of a logic circuit, SRAM, or
`other semiconductor circuit. In this aspect of the invention,
`conductive wiring level 140 is formed before the step
`illustrated in FIG. 5. Alter the dielectric of raised STI 30 is 55
`planarizcd (FIG. 4), planarization continues, stopping on the
`surface of gate conductor 116 as shown in FIG. 9. A second
`layer of conductor for conductive wiring level 140, such as
`doped polysilicon or tungsten, is then deposited as illus(cid:173)
`trated in FIG. 10. Conductive wiring lcvel140, is formed of 60
`a low resistivity material such as a metal or a metal silicide.
`Metals such as tungsten, molybdenum, titanium, or alumi(cid:173)
`num, arc suitable. The low resistivity material can be depos(cid:173)
`ited by methods known in the art, such as chemical vapor
`deposition. It can also be formed from heavily doped poly- 65
`silicon. A layer of insulator 150 may also then be deposited.
`The source/drain defining mask is then used as described
`
`6
`above (FIG. 5) and the two layers of conductor (gate
`conductor 116 and conductive wiring level140) are etched
`such that gate conductor 116 is substantially confined to the
`active area of each transistor and conductive wiring level
`140 extends over STI 30 to interconnect transistors or cells,
`as shown in FIG. 11. Dielectric spacers 152 formed in the
`next step (FIG. 12), coat both gate segments and conductive
`wiring level interconnects. While the interconnect wiring in
`this aspect of the invention is not subminimum dimension,
`this aspect provides a simpler manufacturing process and
`still provides the other advantages of the invention described
`below.
`In the aspect of the invention illustrated in FIGS. 9-13 a
`source/drain extension is first formed by implanting a
`medium dose (less than lxl0 14 cm-2
`) of a dopant such as
`arsenic or boron, for source/drain 138 before spacers 152 are
`formed (FIG. 11). Then, after spacers 152 are formed (FIG.
`12), intrinsic polysilicon (or intrinsic amorphous silicon) is
`deposited or selective silicon is growth for raised source/
`drain 154 as shown in FIG. 13. Dopant for the raised
`source/drain is implanted at low energy so as to avoid
`damage to the single crystal silicon below. Then the dopant
`is diffused from the polysilicon to form ultrashallow junc(cid:173)
`tions 156 without damage. A refractory metal, such as
`titanium is then deposited and annealed to form silicide 158
`in polysilicon raised source/drain 154. Thus, ultrashallow
`junctions 156 are formed that have both the low resistance
`associated with a silicide and very low leakage. The junc(cid:173)
`tions so formed can have a depth of as little as about 500 A.
`30 Of course, other methods of doping the polysilicon of raised
`source/drain 154 can be used, such as in-situ doping.
`The device and isolation structure of the invention
`described hereinabove offers several key advantages. First,
`STI and storage trench corner parasitic problems are reduced
`35 because (1) corner sharpening and gate dielectric thinning
`are eliminated (since the gate dielectric is formed on a planar
`surface before device edges are defined); and (2) gating of
`the sidewall of the channel or its comer by the gate is
`eliminated since the gate is bounded by raised isolation-the
`40 gate does not wrap around the corner.
`Second, because polysilicon gate 116 does not extend
`over field regions under STI 30, field doping under STI 30
`and STI thickness requirements can be relaxed.
`Third, as described in the Noble patent application, layout
`distance between individual device gates can be substan(cid:173)
`tially reduced when the wordline conductor interconnecting
`gate segments is a subminimum dimension spacer rail. In the
`DRAM cell described in the Noble application, for example,
`50 savings in DRAM cell area of up to 37.5% is achieved.
`While several embodiments of the invention, together
`with modifications thereof, have been described in detail
`herein and illustrated in the accompanying drawings, it will
`be evident that various further modifications are possible
`without departing from the scope of the invention. For
`example, a wide range of materials can be used for mandrel
`46, and for rail 40 or conductive wiring level 140. The
`invention can be practiced with n- or p-channel transistors
`with corresponding changes in the doping of the polysilicon
`strap and node polysilicon. Nothing in the above specifica(cid:173)
`tion is intended to limit the invention more narrowly than the
`appended claims. The examples given are intended only to
`be illustrative rather than exclusive.
`What is claimed is:
`1. A semiconductor structure, comprising
`a transistor having a gate, said gate comprising a thin
`dielectric and an individual segment of gate conductor,
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`5,539,229
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`15
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`20
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`7
`said gate conductor being substantially co-extensive
`with said thin dielectric, said gate conductor having a
`top surface having opposed first and second edges and
`opposed third and fourth edges;
`raised isolation bounding said first and second edges;
`a source self-aligned to said third edge and a drain
`self-aligned to said fourth edge, said raised isolation
`not bounding said third edge and said fourth edge; and
`a conductive wiring level in contact with said top surface. 10
`2. A semiconductor structure, as recited in claim 1,
`wherein said thin dielectric has a uniform thickness extend(cid:173)
`ing to said raised isolation.
`3. A semiconductor structure, as recited in claim 1,
`wherein said
`raised isolation comprises a raised Shallow trench for a
`shallow trench isolation.
`4. A semiconductor structure, as recited in claim 1,
`wherein said raised isolation comprises a raised deep trench
`for a trench capacitor.
`5. A semiconductor structure, as recited in claim 1, said
`source and drain located in single crystal silicon, said
`transistor further compensing a raised source and drain.
`6. A semiconductor structure, as recited in claim 5,
`wherein said raised source and drain is comprises one of
`polysilicon and deposited amorphous silicon.
`7. A semiconductor structure, as recited in claim 5,
`wherein said raised source and drain comprises selective
`silicon.
`8. A semiconductor structure, as recited in claim 5,
`wherein said raised source and drain further comprises
`silicide.
`9. A semiconductor structure, as recited in claim 8,
`wherein said raised source and drain have a junction depth
`in said single crystal substrate, said junction depth being 35
`about 500 A.
`10. A semiconductor structure, as recited in claim 1,
`wherein said conductive wiring level comprises a conduc(cid:173)
`tive spacer.
`
`25
`
`8
`11. A semiconductor structure, as recited in claim 1,
`wherein said conductive wiring level is aligned with said
`third edge and said fourth edge.
`12. A semiconductor structure, as recited in claim 11,
`wherein said conductive wiring level comprises a metal
`silicide.
`13. A semiconductor structure, comprising
`a transistor having a gate, said gate comprising a thin
`dielectric and an individual segment of gate conductor,
`said gate conductor being substantially co-extensive
`with said thin dielectric, said gate conductor having a
`top surface having opposed first and second edges, on
`isolation structures bounding said first and second edges,
`said isolation structures having substantially vertical
`sidewalls abutting said first and second edges,
`said dielectric having a substantially uniform thickness
`extending to said raised isolation structures.
`14. A semiconductor structure, as recited in claim 13, said
`isolation structures being raised trench isolation.
`15. A semiconductor structure, as recited in claim 14, said
`raised trench isolation being one of deep trench isolation and
`shallow trench isolation.
`16. A semiconductor structure, as recited in claim 13, said
`top surface further comprising opposed third and fourth
`edges, a some self-aligned to said third edge and a drain
`self-aligned to said fourth edge, said raised isolation not
`bounding said third edge and said fourth edge.
`17. A semiconductor structure, as recited in claim 16,
`30 wherein said source and said drain comprise a raised source
`and drain.
`18. A semiconductor structure, as recited in claim 17, said
`raised source and drain comprising one of polysilicon,
`amorphous silicon, and selective silicon.
`19. A semiconductor structure, as recited in claim 17, said
`raised source and drain having a junction depth in said single
`crystal substrate, said junction depth being about 500 A.
`
`* * * * *
`
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