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`Global Foundaries US v. Godo Kaisha
`Global Ex. 1006
`
`Page 1 of 7
`
`

`

`U.S. Patent
`
`
`
`Sept. 5, 1978
`
`
`
`Sheet 1 of 2
`
`
`4,110,899
`
`
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`FIG 3
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`Page 2 of 7
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`Page 2 of 7
`
`

`

`U.S. Patent
`
`
`
`Sept. 5,1978
`
`
`
`
`Sheet 2 of2
`
`
`
`
`4,110,899
`
`
`
`
`
`
`BOENON
`
`
`RANSRESN
`
`BOREARS(Ly
`
`
`
`
`
`
`Page 3 of 7
`
`Page 3 of 7
`
`

`

`1
`
`4,110,899
`
`METHOD FOR MANUFACTURING
`COMPLEMENTARY INSULATED GATE FIELD
`EFFECT TRANSISTORS
`
`BACKGROUND OF THE INVENTION
`
`15
`
`Vi,
`
`Q., + 2,
`==8
`
`qa)
`
`30
`
`.
`2
`the technique disclosed therein, particularly in the right
`column on page 20 and FIG.2 on page 21, the P-type
`well layer is formed by ion implantation technology
`after the formation of the LOCOSoxide (field oxide)
`layer. Therefore, while the parastic channel
`is not
`readily formed, a complex design of layout for the MOS
`1. Field of the Invention
`FET’s andthe wiring layers therefor is required when a
`The present invention relates to a method for manu-
`plurality of MOS FET’s are to be incorporated in the
`facturing complementary insulated gate field effect
`P-type well layer because LOCOS oxides cannot be
`10
`transistors (hereinafter referred to as CMIS FET’s)
`formed in the P-type well layer. The operating voltage
`havingafield oxide layer of LOCOS(local oxidation of
`is also limited. Thatis, according to the disclosed tech-
`silicon) structure, and moreparticularly to a method for
`nique, the operating supply voltage should be up to
`manufacturing a semiconductor integrated circuit de-
`about 10 volts because as the operating voltagerises, the
`vice comprising such transistors.
`area immediately beneath the LOCOSoxide formed in
`2. Description of the Prior Art
`the semiconductor body is more apt to form a parastic
`In prior art CMIS FET’s of the LOCOSstructure, a
`channel by a wiring layer extending over the LOCOS
`power supply voltage therefor is determined by a
`oxide layer although the above area is made more N-
`threshold voltage V,, of an active region which is a
`type conductive by sodium (+) ions present in the
`channel region immediately beneath a gate electrode
`LOCOSoxide. Furthermore, due to the threshold volt-
`and a threshold voltage V,,,of a parastic MOS FETina
`age V,, of the active region in the P-type well layer, it
`field oxide layer region. Accordingly, whenit is desired
`becomes impossible to prevent the formation of the
`to raise the powersupply voltage for the CMIS FET’s,
`parastic channel in the P-type well as the operating
`it is necessary to change the impurity concentration of a
`. voltage rises. Accordingly, the field of application of
`substrate and the impurity concentration ofa well layer
`25
`which is of opposite conductivity type to that of the
`the semiconductor integrated circuit device manufac- ,
`substrate. Namely, the threshold voltage V,, is defined
`tured by the disclosed techniqueis limited.
`by
`On the other hand, the field of application of the
`semiconductor integrated circuit device comprising
`CMIS FET’s is wide in these days and, actually, the
`operating voltage therefor varies widely depending on
`the specification of a particular product.It is, therefor,
`required to manufacture CMIS FET’s applicable to a
`variety of products of various specifications in a com-
`mon process and provide CMIS FET’s whicharesatis-
`factorily operable with a wide range of operating volt-
`ages. To this end, a method for manufacturing CMIS
`FET’s which can control the threshold voltage V,, of
`the active region of the CMIS FET’s and the threshold
`voltage Vy, of the parastic MOS FETto predetermined
`voltages is required.
`SUMMARYOF THE INVENTION
`
`where Q,is a charge in a bulk, Q,, is surface state and
`oxide charge, and C,is the capacitance of the gate. A
`simple way to control the threshold voltage V,, defined
`by the equation (1) is to control Q,. That is, Q, is related
`to the impurity concentration of the substrate and it
`increases as the impurity concentration of the substrate
`increases. Accordingly, V,,can be increased by increas-
`ing the impurity concentration of the substrate.
`Thus, whenit is desired to raise the operation volt-
`age, a voltage applied to a wiring layer extending over
`the field oxidation region also rises, resulting in a paras-
`tic channel immediately beneath the field oxide layer
`region. That is, a parastic MOS FETis formed.In order
`to avoid the formation of such a parastic MOS FET,it
`is necessary to increase the impurity concentration of
`the substrate or the impurity concentration of the well
`layer as seen from the above equation to raise the
`threshold voltage V,, of the parastic MOS FET. How-
`ever, since the impurity concentrations of the substrate
`and the well layer are determined by electrical charac-
`teristics of the CMIS FET’ssuchas the threshold volt-
`age V,, and mutual conductance gm,the range of the
`operating voltage for the CMIS FET’sis limited and
`the magnitudethereofis very small. For example, when
`the threshold voltage V,, of an N-channel MOS FET
`formed in a P-type well layer is 0.45 volts, a parastic
`channel is formed at about 4 volts because an N-type
`inversion layer is readily formed because of many so-
`dium (+) ions present in the field oxide layer. As a
`result, the operating voltage should be up to about 3
`volts.
`As a commonly used method for manufacturing the
`CMIS FET’sof the LOCOSstructure which avoids the
`formation of the parastic channel in the P-type well
`layer and which can be practiced in a simple way, a
`technique disclosed in the Philips Technical Review,
`Vol. 34, No. 1, 1974, pp. 19-23, is known. According to
`
`Page 4 of 7
`
`35
`
`40
`
`45
`
`50
`
`60
`
`65
`
`It is an object of the present invention to provide a
`method for manufacturing CMIS FET’s of LOCOS
`structure which allowsthe establishmentof the thresh-
`old voltage V,, of the parastic MOS FETin thefield
`oxide layer region independently of the threshold volt-
`age V,, ofthe active region whereby the operating volt-
`age can be raised and the range thereof can be widened.
`It is another object of the present invention to pro-
`vide a method for manufacturing CMIS FET’s of
`LOCOSstructure suited for a semiconductorintegrated
`circuit device comprising a number of CMIS FET’s of
`LOCOSstructure.
`It is another object of the present invention to pro-
`vide a method for manufacturing CMIS FET’s of
`LOCOSstructure suited for a semiconductor integrated
`circuit device operating at a high supply voltage.
`It is another object of the present invention to pro-
`vide a method for manufacturing CMIS FET’s of
`LOCOSstructure having less crystal defects.
`It is another object of the present invention to pro-
`vide a method for manufacturing CMIS FET’s of
`LOCOSstructure whichallows a high integration den-
`sity.
`It is another object of the present invention to pro-
`vide a method for manufacturing CMIS FET’s of
`
`

`

`4
`nitride (Si;N,) layer under which the P-channel MOS
`LOCOSstructure whichis less influenced by contami-
`device is to be formed as a mask, phosphorus (P) impu-
`nation.
`rity 9 is ion implanted at 45KeVin that portion of the
`In order to achieve the above objects, the method of
`surface of the substrate 1 on whichthefield oxide layer
`manufacturing the CMIS FET’s of the LOCOSstruc-
`of the P-channel MOSdevice is to be formed. (FIG.3)
`ture according to the present invention comprises the
`Theion implantation energy of 45KeV for the phospho-
`following steps of;
`rus impurity is enoughto obtain an area ofa sufficiently
`(1) forming a P(or N)-type well layer in a portion of
`high surface impurity concentration. On the other hand,
`an N(or P)-type semiconductor substrate surface and
`with the acceleration energy of below 60KeV, phos-
`then forming a thin thermal oxidation layer over the
`_0
`phorus ions can be masked only bythe Si;N,layer or the
`entire surface and then formingasilicon nitride layer
`SiO, layer. Accordingly, the photoresist layer need not
`overthe entire surface thereof,
`be maintained on the Si;N, layer 4b. This means that the
`(2) etching awaythesilicon nitride layer at areas on
`alignment of the mask used in exposing step for the
`which field oxide layers are to be formed,
`photoresist layer 8 need not be highly accurate. Thatis,
`(3) ion implanting donor (or acceptor) and acceptor
`an edge8S of the photoresist layer 8 may extend beyond
`(or donor) impurities at those areas in the N(or P)-type
`a PN junction J between the P-type well layer 2 and the
`semiconductor substrate and the P(or N)-type well
`N-type substrate 1.
`layer on whichthe field oxide layers are to be formed,
`(d) After removing the photoresist layer 8, the sub-
`(4) heat treating the substrate to selectively thermally
`strate 1 is oxidized in a wet oxygen atmosphereat 1000°
`oxidize the areas on which thefield oxide layers are to
`C. for about 7.5 hours to form selective silicon oxide
`be formed,using said silicon nitride layer as a mask, and
`(SiO,) layers 10 of a thickness of about 1.4 ym of
`(5) removing the silicon nitride layer formed in the
`LOCOSstructure (FIG.4). In this case, because of the
`step (1) and thethin thermal oxidation film beneath the
`masking action of the Si,;N, layer 4 to the oxygen,sili-
`silicon nitride layer and then forming a gate insulation
`con oxide (SiO,) layer is not formed on the areas cov-
`layer, a source region and a drain region of a MIS de-
`ered with the Si,;N, layer 4. Then, the selective oxida-
`vice in the N(or P)-type semiconductor substrate and
`tion mask of the Si,N, layer 4 and the underlying thin
`the P(or N)-type welllayer.
`SiO, layer 3 are removed (FIG.4).
`BRIEF DESCRIPTION OF THE DRAWINGS
`Through the heat treatment for forming the thick
`SiO, layers 10 of the LOCOSstructure, the impurities
`FIGS. 1 through 6 show one embodiment of the
`which have been ion implanted in the previous step are
`present invention illustrating a sequence of steps, in
`activated and diffused so that P+-type field diffusion
`partial sectional views, of manufacturing a semiconduc-
`layers 7a and N+-type field diffusion layers 9a, which
`tor integrated circuit device comprising a plurality of
`act as parastic channel stopper layers, are formed (FIG.
`CMIS FET’s of LOCOSstructure.
`4
`
`4,110,899
`
`5
`
`_ 5
`
`30
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENT
`
`(e) On the surface of the substrate 1, gate oxide layers
`11 of a thickness of about 1000 A are formed in a dry
`O, atmosphere at 1000° C. Then, on the surfaces of the
`The method for manufacturing a CMIS FET IC of
`gate oxidelayers 11, polycrystalline silicon layers 12 are
`LOCOSstructure of the present invention is now ex-
`deposited to a thickness of about 3500 A.the polycrys-
`plained in the order of manufacturing steps.
`talline silicon layers are then etched away by photo-
`(a) A portion of a surface of an N-type silicon sub-
`etching except those areas which are to act as gate
`strate is delimited, in which a P-type well layer 2 of a
`electrodes. Etching is again carried out using the re-
`thickness of about6-8 jzm is formed by ion implantation
`maining polycrystalline silicon layers 12 as a mask to
`technique. Thereafter, the surface of the substrate is
`removethe gate oxide layers 11 on the source and drain
`thermally oxidized in a dry O, atmosphere at about
`regions. The drain regions 13, 14 and the source regions
`1000° C. to formasilicon oxide (SiO) layer 3 of the
`thickness of about 700 A. Then,a silicon nitride (Si,N,)
`13a, 14a of the MOSdevices are then formed using the
`layer 4 of the thickness of about 1000 A - 1400 A is
`thick field oxide layers 10 and the polycrystalline silicon
`layers 12 as a mask (FIG.5).
`formed by vaporreaction on the layer 3. (FIG. 1)
`The formation of the drain regions 13, 14a and the
`(b) The Si;N, layer 4 and the SiO, layer 3 therebe-
`source regions 13a, 14 of the P-channel and N-channel
`neath are etched away except at areas 4a and 4b on
`MOSdevices, respectively, is explained in moredetail.
`whichfield oxide layers are to be formed, using a photo-
`A photoresist layer is formed on an area in which the
`resist layer 5 (5a and 55) as a mask. Then, that portion
`N-channel MOSdevice is to be formed. Those portions
`of the surface of the substrate 1 on which a P-channel
`of the gate oxide layer 11 which correspond to the
`MOSdevice is to be formed is covered with a photore-
`source and drain regions of the P-channel MOSdevice
`sist layer 6, and then boron (B) impurity 7 is ion im-
`are removed. Then, phosphorus impurity is diffused in
`planted at 75KeV at that area of the surface ofthe sub-
`the exposed surface of the substrate 1 using the poly-
`strate 1 on whichthefield oxide layer of the N-channel
`crystalline silicon layer 12 for the gate electrode G, and
`MOSdevice is to be formed, using, as a mask, a photo-
`portionsof the field oxide layers 10 as a diffusion mask,
`resist layer 6 and the photoresist layer 5a which has
`to form the source region 14 and the drain region 142.
`been used in etching the Si,N, layer 4 and the underly-
`In this manner, the P-channel MOSdevice is formed.
`ing SiO,layer3 so that a surface impurity concentration
`Then, the photoresist layer is removed and new photo-
`of about 2 x 10! atoms/cm? to 5 X 10% atoms/cm?is
`resist layers are formed on the source region 14 and the
`obtained at the said area. (FIG. 2)
`drain region. 14a, and the portions of the gate oxide
`(c) After removing the photoresist layers 5 and 6, a
`layer 11 which correspondto the source and drain re-
`new photoresists layer 8 is selectively formed on that
`gions of the N-channel MOS device are removed.
`portion of the surface of the substrate 1 in which the
`Thereafter, using the polycrystalline silicon layer 12 for
`N-channel MOSdevice is to be formed. Then,using the
`the gate electrode G, of the P-channel MOSdevice and
`selectively formed photoresist layer 8 and the silicon
`
`3va
`
`40
`
`50
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`60
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`Page 5 of 7
`
`

`

`4,110,899
`
`
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`5
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`10
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`20
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`5
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`the portions of the field oxide layer 10 as a diffusion
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`mask, boron impurity is diffused to form the source
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`region 13a and the drain region 43.
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`
`
`(f) To insulate the polycrystalline silicon layers 12 for
`
`
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`
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`
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`the gates G,a silicon oxide (SiO,) layer 15 is deposited
`
`
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`
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`on the surface of the substrate by thermal decomposi-
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`
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`
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`
`
`tion of silane (SiH,) (FIG. 6). A PSG (phosphosilicate
`
`
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`
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`glass) layer is preferable as an insulating layer to insulate
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`the polycrystalline silicon layers 12 for the gate elec-
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`trodes G. Then,after forming windowsfor contacts, an
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`aluminum layer of a thickness of 1 wm is formed by
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`vacuum deposition and required aluminum wiring pat-
`terns as well as source electrodes S and drain electrodes
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`D are formed by a conventional photoetching process
`
`(FIG. 6).
`
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`(g) The wafer treatment process is thus completed.
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`Thereafterit is sliced into chips in a conventional man-
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`ner, and they are assembled into devices.
`
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`
`
`The present method for manufacturing the CMIS
`FET’s of the LOCOSstructure described hereinabove
`
`
`
`
`
`
`
`
`
`has the following features.
`
`
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`
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`(1) Since the field diffusion layers 7a and 9a having
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`impurity concentrations higher than that of the sub-
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`strate 1 or the P-type well layer 2 and selected indepen-
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`dently of those impurity concentrations are formed
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`under the thick SiO, layer 10 which act as the field
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`oxide layer, the threshold voltage V,, of the parastic
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`MOStransistor in the region of the field oxide layer 10
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`can be controlled to any value by adjusting the amount
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`of ion implantation, and it can be set independently of 30
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`the threshold voltages V,, of the substrate 1 and the
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`P-type well layer 2. Therefore, according to the present
`
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`
`
`invention, it is possible to manufacture CMIS FET’s
`
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`and semiconductorintegrated circuit devices compris-
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`ing a number of CMIS FET’s having different operat-
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`ing voltages in the same manufacturing process.
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`(2) In the formation of the field diffusion layers 7a
`and 9a, the Si;N, layer 4 which serves as the mask in
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`forming the thick field silicon oxide layer 10 by the
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`thermal oxidation is used in situ. Therefore, the field
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`diffusion layers 7a and 9a areself-aligned with the field
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`silicon oxide layer 10 and the sources and drains of the
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`devices resulting in a high integration density. Thus, the
`semiconductor device of the present invention can be
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`manufactured in a very simple way.
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`(3) Because of the CMIS semiconductor device of the
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`LOCOSstructure, fine processing is possible. Further-
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`more the performance of the device is high in that it
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`provides a high operation speed and a low power con-
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`sumption. Therefore, the CMIS FET’s of the present
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`invention can be applied to various products.
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`(4) Since the P-type well layer is formed before the
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`formation ofthe field oxide layer, it is possible to form
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`the field oxide layer in the well layer. Thus, whenit is
`desired to form a plurality of MOS FET’sin the well
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`layer, the design of the layouts of the MOS FET’s and
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`the wiring layers therefor is facilitated. Furthermore,
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`the source and drain regions can be readily formed
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`using the field oxide layers in the well layer as the mask.
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`In ion implanting the impurity in the above embodi-
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`ment, the thin SiO, layer 3 under the Si;N, layer 4 is
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`removed to expose the surfaces of the N-type substrate
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`1 and the P-type well layer 2. However, the thin SiO,
`layer 3 may beleft unremoved. Inthis case, less defects
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`on the surfaces of the N-type substrate 1 and the P-type
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`well layer 2 due to the ion damage take place and the
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`affect by the contamination is minimized because the
`surfaces are not exposed. Furthermore, by the presence
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`6
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`of the thin SiO, layer 3, bird-beaks do not grow. Thatis,
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`when the thin SiO, layer 3 is etched away, the parts of
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`the SiO, layer 3 underthe Si,N, layers 4a and 4b, which
`are called overhung, are also etched away. Asa result,
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`lateral oxidation proceeds more rapidly resulting in the
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`growthof the bird-beaks. On the other hand, when the
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`thin SiO, layer 3 is left unremoved, the bird-beaks are
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`grownless slowly so that the area occupied by thefield
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`oxide layers is minimized resulting in the increase in the
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`integration density.
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`In the above embodiment, the parastic channel stop-
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`per layers (field diffusionlayers) are formed under the
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`field oxide layers formed in the P-type well layer and
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`the substrate. In this case, the operating voltage of up to
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`about 50 volts is permitted. On the other hand,if the
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`semiconductor integrated circuit device manufactured
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`by the present method is to be used at the operating
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`voltageof less than 10 volts, the phosphorusion implan-
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`tation shown in FIG. 3 may be omitted, because if the
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`V,, of the P-channel MOS FETis 0.45 volts the V,, of
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`the N-type parastic channel is as high as 12 volts or
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`higher and it is not readily inverted at the operating
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`voltage of below 10 volts.
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`It should be understood that the present inventionis
`not limited to the embodiment described above butit
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`can be applied to the CMIS FET’s of the LOCOSstruc-
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`ture having various gate electrodes or gate insulation
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`layers and the semiconductorintegrated circuit devices
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`comprising such CMIS FET’s.
`Weclaim:
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`1. A method for manufacturing complementary insu-
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`lated gate field effect transistors comprising the stepsof:
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`(a) delimiting a portion of a surface of a semiconduc-
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`tor substrate of a first conductivity type and form-
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`ing therein a well layer of a second conductivity
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`type, forming a thin insulating layer over the entire
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`surface thereof and then forminga silicon nitride
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`layer over the entire surface thereof;
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`(b) etching away said silicon nitride layer at least
`those areas on which field oxide layers are to be
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`formed;
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`(c) introducing impurity of the second conductivity
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`type at that area in said well layer of the second
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`conductivity type on which the field oxide layeris
`to be formed;
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`(d) heat treating the substrate to selectively thermally
`oxidize the areas on which thefield oxide layers are
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`to be formed, using said silicon nitride layer as a
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`mask to form a thick field oxide layer; and
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`(e) removingthesilicon nitride layer and the underly-
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`ing thin insulating layer formed in said step (a),
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`selectively forming gate insulation layers and sili-
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`con layers on the exposed substrate and well layer,
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`forming source regions and drain regions of MIS
`devices in said semiconductor substrate of the first
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`conductivity type and the well layer of the second
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`conductivity type using said silicon layers and said
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`thick field oxide layers as masks, and forming diffu-
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`sion layers of desired impurity concentrations be-
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`neath said thick field oxide layers.
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`2. A method for manufacturing complementary insu-
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`lated gate field effect transistors according to claim 1
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`wherein said step (b) includes a sub-step of etching
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`awaythe thin insulating layer underthesiliocn nitride
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`layer.
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`3. A method for manufacturing complementary insu-
`lated gate field effect transistors according to claim 2
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`15
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`25
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`35
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`45
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`350
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`35
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`65
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`Page 6 of 7
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`Page 6 of 7
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`8
`7
`(f) removingthesilicon nitride layer and the underly-
`whereinsaid thin insulating layer is a thermal oxidation
`ing thin thermal oxidation layer formed in the step
`layer.
`(a), selectively forming gate insulation layers and
`4. A method for manufacturing complementaryinsu-
`silicon layers on the exposed surface area of the
`lated gate field effect transistors according to claim 1
`substrate and well layer, forming source regions
`wherein in said step (c) said impurity of the second
`and drain regions of the respective MIS. devices
`conductivity type is introduced, by ion implantation,
`using said silicon layers and said thick field oxide
`into those areas of the well layer of the second conduc-
`layers as masks, and forming diffusion layers of
`tivity type on which the field oxide layers are to be
`desired impurity concentrations under said field
`formed.
`oxide layers.
`5. A method for manufacturing complementary insu-
`8. A method for manufacturing a semiconductorinte-
`lated gate field effect transistors comprisingthesteps of:
`grated circuit device including complementary insu-
`(a) delimiting a portion of a surface of an N-type
`lated gatefield effect transistors comprising the stepsof:
`semiconductorsubstrate and forming a P-type well
`(a) delimiting a portion of a surface of an N-type
`layer therein, forming a thin thermal oxidation
`silicon substrate and forming a P-type well layer
`layer over the surface thereof and then forming a
`therein by ion implantation, forming a silicon diox-
`silicon nitride film over the surface thereof;
`ide layer over the entire surface thereof and then
`(b) etching awaysaid silicon nitride layer at those
`formingasilicon nitride layer over the entire sur-
`areas on whichfield oxide layers are to be formed;
`face thereof;
`(c) ion implanting donorand acceptorimpurities into
`(b) selectively forming a first photoresist layer on said
`those areas in said N-type semiconductorsubstrate
`silicon nitride layer over said N-type silicon sub-
`and the P-type well layer, respectively, on which
`strate and said P-type well layer;
`the field oxide layers are to be formed, using a
`(c) etching awaysaid silicon nitride layer and the
`portion ofsaid silicon nitride layer as a mask;
`underlying silicon nitride layer using said first photore-
`(d) heattreating the substrate to selectively thermally
`sist layer as a mask to expose surfaces of said N-type
`oxidize those areas on which thefield oxide layers
`silicon substrate and said P-type well layer; .
`are to be formed,usingsaid silicon nitride layer as
`(d) covering the exposed N-type silicon substrate
`a mask for forming the field oxide layers of
`surface with a second photoresist layer;
`LOCOSstructure; and
`(e) ion implanting an acceptor impurity into the ex-
`(e) removingsaid silicon nitride layer and the under-
`posed surface area ofsaid P-type well layer usin
`lying thin thermal oxidation layer formed in said
`said first photoresist layer as a mask;
`step (a), selectively forming gate insulation layers
`(f) removingsaid first and second photoresist layers
`and semiconductor layers on the exposed N-type
`and covering the exposed surface of said P-type
`substrate and exposed P-type well layer, forming
`well layer with a third photoresist layer;
`source regions and drain regions of MIS devices in
`(g) ion implanting a donor impurity into the exposed
`said N-type semiconductor substrate and said P-
`surface area of said N-type silicon substrate using
`type well layer using said semiconductor layers
`said silicon nitride as a mask;
`and said field oxide layers as masks.
`(h) removing said third photoresist film and selec-
`6. A method for manufacturing complementary insu-
`tively thermally oxidizing the exposed surfaces of
`lated gate field effect transistors according to claim 5
`said P-type well layer and said N-type silicon sub-
`wherein in said step (c) the donor is phosphorus and the
`strate using said silicon nitride layer as a mask to
`form thick field silicon dioxide layers;
`acceptoris boron.
`7. A method for manufacturing complementary insu-
`(i) etching away said silicon nitride layer and the
`lated gate field effect transistors comprising the stepsof:
`underlying silicon dioxide layer to expose said
`(a) delimiting a portion of a surface of an N(P)-type
`P-type well layer and said N-type silicon substrate;
`(j) oxidizing the exposed surfaces ofsaid P-type well
`semiconductor substrate and forming a P(N)-type
`well layer therein, forming a thin thermal oxidation
`layer and said N-typesilicon substrate to form gate
`layer over the entire surface thereon, and then
`silicon dioxide layers;
`(k) forming silicon layers overentire surfaces of said
`formingasilicon nitride layer over the entire sur-
`field silicon dioxide layers and said gate silicon
`face thereof;
`(b) etching awaysaid silicon nitride layer and the
`dioxide layers;
`()) selectively etching away said silicon layers and
`underlying thin thermal oxidation layer at those
`said gate silicon dioxide layers to expose the sur-
`areas on whichfield oxide layers are to be formed;
`faces of said N-type silicon substrate and said P-
`(c) ion implanting acceptor (donor) or donor(accep-
`tor) impurity in the exposed surface area of the
`type well layer;
`(m) diffusing an acceptor impurity into the exposed
`substrate in the area of N(P) channel of P(N) chan-
`N-type silicon substrate and a donor impurity into
`nel device;
`the exposed P-type well layer using the remaining
`(d) ion implanting donor (acceptor) or acceptor (do-
`silicon layer and said field silicon dioxide layers as
`nor) impurity in the exposed surface area of the sub-
`masks to form source regions and drain regions,
`strate in the area of P(N) channel of N(P) channel de-
`respectively, and
`vice;
`(n) connecting aluminum layers to said source regions
`(e) heat treating the substrate to selectively thermally
`and drain regions formed in said N-type silicon
`oxidize the exposed surface areas of the substrate using
`substrate and said P-type well layer, respectively.
`said silicon nitride layer as a mask to form thick field
`*
`*+
`*
`*
`*
`oxide layers; and
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