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`Global Foundaries US v. Godo Kaisha
`Global Ex. 1002
`
`Page 1 of 10
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`

`

`U.S. Patent
`
`Oct. 6, 1992
`
`Sheet 1 of 5
`
`5,153,145
`
`FIG,
`
`| F
`
`IG, e
`
`FIG, 3
`
`c4
`
`
` ILLblLKKG]re
`
`
`
`
`SSNSONS
`
`
`
`
`FIG. 4
`
` WEES)
`
`AR
`VLLLLRINNUR
`
`Page 2 of 10
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`Page 2 of 10
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`

`

`U.S. Patent
`
`
`
`Oct. 6, 1992
`
`
`
`Sheet 2 of 5
`
`
`5,153,145
`
`
`
`
`OLSOMEE
`
`
`
`
`
`
`el
`
`
`
`
`
`STIRS
`S
`ARN
`
`ULLAL}
`
`13
`
`
`
` WY!INS
`
`VODA
`
`Page 3 of 10
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`Page 3 of 10
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`

`

`
`
`U.S. Patent
`
`
`Oct. 6, 1992
`
`
`
`Sheet 3 of 5
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`
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`5,153,145
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`
`
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`
`.
` 23
`
`SWAS
`
`
`ADSLZZIA
`
`13
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`{1
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`Page 4 of 10
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`Page 4 of 10
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`U.S. Patent
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`
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`Oct. 6, 1992
`
`
`
`Sheet 4 of 5
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`5,153,145
`
`
`r 1G,
`
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`ii
`
`LLLI GIGILLBDEA
`
`C4(ryCp.
`
`
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`IPL
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`JAMe:
`
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`cerereelcae—=
`
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`LS
`
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`VEROSC
`Ni es
`Belly
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`SAS MZess
`K—< N
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`CaN
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`Page 5 of 10
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`Page 5 of 10
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`

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`U.S. Patent
`
`Oct. 6, 1992
`
`Sheet 5 of 5
`
`5,153,145
`
`r iG. 14
`
`
`
`
`
`123 121 118
`
`
`
`ANNUING (REED
`
`KGS) USS La.NDFS SIR SARS
`
`
`
`ROALD
`
`
`SY
`
`
`Jus 115 19 HS
`na”
`
`119 115 119
`
`
`TE
`
`FIG, 15
`
`123 121 118 17 0
`170 121193 «170
`
`
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` SIF,
`bdoh RONG
`
`OY)ZC SER
`
`WPA LSI 4INGO
`
`
`
`
`WV?
`
`
`TREADS
`
`Si
`
`
`
`119
`115 119
`119
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`A113 149 fie TS 119
`
`CMCLLMN
`
`
`
`
`Page6 of 10
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`Page 6 of 10
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`

`

`
`1
`
`FET WITH GATE SPACER
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`5,153,145
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`
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`2
`are formed. The spacers simultaneouslyfacilitate the
`
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`formation of a self-aligned silicide contact over onlythe
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`deep portion of the LDD junction. The self-aligned
`silicide-over-deep junction structure has a desirably low
`
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`
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`sheet resistance.
`
`
`In another embodimentthe gate stack and runnersare
`
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`covered with a dielectric layer. At
`least one spacer
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`together with the dielectric layer serves to insulate the
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`runner so that local conductive interconnection may
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`extend over the runner without risk of shorting.
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`The spacers perform a variety of other useful func-
`tions in various embodiments. For example, one of the
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`spacers maybe chosen from a material which is imper-
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`vious to migration of metal from silicide contacts over
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`source/drain regions to the conductive portion of the
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`gate. Such migration has been observed through con-
`ventional spacer arrangements and has contributed to
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`shorting of the gate to the source/drain. Other advan-
`tages of the invention are discused below.
`
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`
`
`BRIEF DESCRIPTION OF THE DRAWING
`
`
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`
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`FIGS. 1-15 are cross-sectional views depictingillus-
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`trative processing sequences for
`fabricating various
`
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`
`
`embodiments of the present invention.
`DETAILED DESCRIPTION
`
`
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`The inventive concept maybe best understood bya
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`discussion of the various procedures which may illustra-
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`tively be utilized to fabricate the inventive device.
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`FIG. 1 generally shows a representative cross-section
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`of a portion of a wafer during initial steps of typical
`fabrication. Reference numeral 11 denotes a substrate
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`which maytypicallybe silicon or epitaxial silicon. Ref-
`erence numeral 13 denotes a portion of a field oxide,
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`while reference numeral 15 denotes a gate dielectric
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`layer which is typically an oxide. Reference numeral 17
`denotes a layer conductive material which maybe, for
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`example, polysilicon. Typical thicknesses for layers 15
`and 17, respectively, are 100-200 A and 2500-4000 A,
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`respectively.
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`Turning to FIG. 2, layers 15 and 17 have beenpat-
`terned by methods known to those skilled in the art to
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`create FET gate stack designated by reference numeral
`18. Next, another oxide layer 19 is formed, asillustrated
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`in FIG. 3. Oxide layer 19 is desirably a thermal oxide,
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`such as one grown at approximately 900° C. in oxygen.
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`However, a deposited oxide might also be used. It will
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`be noted that oxide layer 19 surroundsgate 18, covering
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`sides 20 and 22 and top 24 of gate 18. A typical thickness
`for oxide layer 19 is 150-250 A. Layer19 is desirablyas
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`thick as or thicker than gate oxide 15. Generally a ther-
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`mal oxide is preferred because of its lowinterface trap
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`density. Next, dielectric layer 21 which is typically
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`silicon nitride or silicon oxynitride is deposited. An
`exemplary thickness for layer 21 is 150-400 A.
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`Finally, layer 23 is deposited upon layer 21. Layer 23
`may desirably be a deposited oxide ofsilicon. Such an
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`oxide may be formed from silane or by decomposition
`of a variety of organometallic precursors such astetra-
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`ethoxysilane, (known by the acronym “TEOS”), or
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`diacetoxy-ditertiarybutoxysilane (known bythe acro-
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`
`
`or
` tetramethylcyclotetrasilane
`nym “DADBS”),
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`known by the acronym “TMCTS” and sold byJ. C.
`Schumacher,a unit of Air Products and Chemicals Inc.,
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`under the trademark “TOMCATS.” Layer 23 may be
`doped, if desired, with boron or phosphorous. An exem-
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`
`TECHNICAL FIELD
`
`
`This invention relates to integrated circuits and, more
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`
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`particularly to integrated circuits with field effect tran-
`sistors (FETs) and methods for making same.
`
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`
`
`BACKGROUNDOF THE INVENTION
`
`
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`
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`Those concerned with the development of integrated
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`
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`circuit technology have continually sought to develop
`structures and methods of fabrication which will
`in-
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`crease Circuit packing density, circuit performance, and
`
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`improve processyields.
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`For example. some designers of submicron MOS-
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`FETs have employed a so-called lightly-doped drain
`structure (LDD). The LDDstructure features a shal-
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`lowjunction near the device gate and a deeper junction
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`spaced more remotely from the gate. The shallowjunc-
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`tion helps to avoid punch-through and short channel
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`effects. However, the shallowjunction exhibits a high
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`sheet resistance and therefore may,
`taken alone, ad-
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`versely affect device performance.
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`Various approaches to LDD technology have been
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`investigated in the past. Among them are: Pfiester,
`
`
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`
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`“LDD MOSFETsUsing Disposable Side Wall Spacer
`
`
`
`
`
`
`
`Technology.” IEEE Electron Device Letters V. 9(4),
`
`
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`
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`p. 189-192 (1988) and Ohet al.. “Simultaneous Forma-
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`
`
`tion of Shallow-Deep Stepped Source/Drain for Sub-
`
`
`
`
`
`micron CMOS.” VLSI Technology Symposium, p.
`73-74 (1988).
`
`
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`
`
`Some of the above-mentioned publications feature
`the use ofsilicide processes in an attempt to reduce the
`
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`high sheet resistance problems mentioned above. How-
`ever. an examination of the published processes reveals
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`various practical difficulties with their implementation.
`Whetheror not an LDD structure is employed, vari-
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`ous other problems mayoccur during device processing
`
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`which may subsequently degrade integrated circuit
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`
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`performance. For example. various steps associated
`with silicide processes may cause either damageto the
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`silicon substrate surface or may contribute to shorting
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`between the source/drain and gate.
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`Another problem confronting integrated circuit de-
`signers is the need to interconnect individual transistors
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`with increasingly complex interconnection schemes.
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`Designers frequently employgate-level local intercon-
`nection schemes. However,if it
`is either necessary or
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`desirable for a local interconnection line to cross over a
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`gate runner, care must be taken to prevent electrical
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`contact between the gate runner andthe local intercon-
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`nection line. Those concerned with the developmentof
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`integrated circuits have consistently sought processes
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`which will solve the above and other problems.
`SUMMARYOF THE INVENTION
`
`
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`
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`The present invention providesfor a field effect tran-
`sistor with a gate stack formed upon a semiconductor
`
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`substrate. During fabrication, three material layers are
`formed over the gate stack and upon the substrate. At
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`least the outer two material layers are sequentially an-
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`isotropically etched, creating two spacers adjacent the
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`gate stack (and gate runners).
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`The spacers perform a variety of useful functionsin
`various alternative embodiments of the invention. For
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`
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`example, in one embodiment, the spacers mayfacilitate
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`creation of LDD junction profiles, the spacers serving
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`to mask portions of the substrate while partial junctions
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`— 0
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`40
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`45
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`.
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`50
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`35
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`60
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`65
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`Page7 of 10
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`Page 7 of 10
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`

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`5,153,145
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`3
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`plary thickness for layer 23 is 800-4000 A. Alterna-
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`tively. layer 23 maybe polysilicon.
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`In FIG. 4. layers 23. 21, and 19 have been anisotropi-
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`cally etched in sequence. The figure showsgate stack 18
`surrounded on sides 20 and 22 by the nested remnants of
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`layers 23. 21, and 19. For convenience in the following
`discussion each of the above-mentioned remnants will
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`be termed a “spacer.” However,it should be noted that
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`spacers 19 and 21 (which are nested beneath spacer 23)
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`have a generally “L-shaped” appearance (in cross-sec-
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`tion). Spacer 23 has a generally rounded outer contour
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`resembling a fillet. Of course,
`in actual practice the
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`rounded contour of spacer 23 may become somewhat
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`distorted by various processing procedures. Similarly.
`“L-shapes” of spacers 19 and 21 may become somewhat
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`distorted, producingtilted spacers with slightly irregu-
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`lar sides or other irregularities. However. in general, the
`anisotropic etching procedures in current common use
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`will produce a nested set of spacers, the inner two 19
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`and 21 having comparativelyflat sides and the outer are
`23 having a rounded or curved outer surface.
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`The presence of layer 21 between layers 23 and 19
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`makesit possible to fairly precisely control the etching
`of layer 19 to avoid over-etching and damage to sub-
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`strate surface 26. For example. if layer 23 is BPTEOS.
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`layer 21 is silicon nitride, and layer 19 is thermal oxide,
`it will be found that layer 21 serves as an etch step
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`against the etching of layer 23. Once layer 21 is reached.
`the artisan is on notice that
`the remaining two thin
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`layers must be etched with care.
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`It maybe considered desirable to protect the surface
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`26 of substrate 11. If protection for surface 26 is desired,
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`then layer 19 need not be etched at this juncture. Of
`course, if layer 19 is not etched, only two spacers 21 and
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`23 will be formed and layer 19 will overlie surface 26.
`3
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`(For convenience. FIG. 4 shows layer 19 etched to
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`form a spacer.)
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`Layer 19 is, as mentioned before, desirably a ther-
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`mally grown oxide. The oxide exhibits a lowinterface
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`trap density and servesas a stress relief buffer for over-
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`lying layer 21. (Typical silicon nitride films, such as that
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`recommended for layer 21, may exhibit considerable
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`stresses.) Thus layer 19 prevents high stressesin layer 21
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`from distorting substrate 11.
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`Nowthat formation of a nested double ortriple layer
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`spacer has been described. a variety of applications of
`the inventive structure together with alternative em-
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`bodiments and their advantages will be described.
`FIGS. 5-7 illustrate howthe inventive concept may
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`nowbeutilized to form a lightly-doped drain structure.
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`Referring first
`to FIG. 5, an ion implantation step,
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`shown schematically by species denoted by reference
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`numeral 31 is performed to form deeply-doped junc-
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`tions 25 and 27. The appropriate ion species 31 is deter-
`mined by whether an NMOS or PMOS deviceis to be
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`formed. Of course, should a CMOS pair of devices be
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`desired, photoresist 29 is deposited upon that portion of
`the structure which must be shielded from the implanta-
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`tion species 31. It will be noted, as illustrated in FIG. 5,
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`that gate 18 flanked byspacers 19, 21, and 23 effectively
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`mask portions 28 and 30 of substrate 11 from implanta-
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`tion species 31. (If layer 19 has not been etched, it may
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`serve to protect surface 26 during the implantation step.
`Spacers 21 and 23 will still serve as protective masks for
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`regions 28 and 30.)
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`A variety of other techniques maybeutilized to form
`junctions 25 and 27. In each case spacers 21, 23 (and
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`spacer 19 if formed) will mask portions 28 and 30 of
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`4
`substrate 11. For example. a varietyof gaseous and solid
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`diffusion techniques known to those skilled in the art
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`may be employed to form junctions 25 and 27.
`Next, as illustrated by FIG. 6. spacers 23 are removed
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`in anticipation of formation of the shallow portion of
`the device junctions. If spacers 23 are made from un-
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`densified TEOS or even densified TEOS or BPTEOS,
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`they maybe etched much more quicklythan field oxide
`13 or any protective oxide (such as layer 19 or another
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`regrown oxide layer) which may cover deep junction
`27. For example, using a 15:1 HF etch, the etch rate for
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`thermal oxide is approximately 200 A per minute, while
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`for undensified TEOS the etch rate is approximately
`1400 A per minute and for phosphorous doped TEOS,
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`20,000 A per minute. If spacer 23 has been made from
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`polysilicon,
`it may be removed by plasma etching.
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`(However. if materia] 17 is also polysilicon, it will also
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`be attacked by the plasma etching process. Conse-
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`quently, it is desirable that there be a protective layer
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`such as silicon nitride material 17 if spacer 23 is polysili-
`con. The use of various layers, such as silicon nitride
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`over the gate stack is discussed in greater detail in subse-
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`quent paragraphs.)
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`After spacer 23 has been removed. a second implant
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`using ion species 37 shown in FIG. 6 is performed. The
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`second implantation species must penetrate the “foot”
`of spacers 21 and 19. The foot serves to absorb some of
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`the ionic species, thus creating shallowjunction regions
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`33 and 35 in portions 28 and 30 of substrate 11. Proper .
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`tailoring of the implant energy and dosage and the
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`thickness of the feet of layers 21 and 19 permits the
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`achievement of carefully controlled shallow junctions
`33 and 35.
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`If a CMOS pair is being formed. photoresist 29 may
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`be stripped. a new photoresist may be positioned over
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`the already-formed device depicted in FIG. 6 and the
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`complementary device formed bysimilar steps.
`Next. as illustrated in FIG. 7, a thermal drive-in may
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`be performed. Other techniques such as laser heating
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`mayalso be employed to remove implant damage and
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`activate the dopant species. Next,
`if desired, a self-
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`aligned salicidation (salicide) maybe performed. FIG. 9
`illustrates the structure of FIG. 7 after a salicidation
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`step has been performed. Typically, a metal such as
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`titanium, tantalum, molybdenum. or tungsten is blanket-
`deposited over the structure depicted in FIG. 7. Then
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`the structure is heated by methods known to those
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`skilled in the art, causing the metal to react preferen-
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`tially with underlying silicon, forming silicide regions
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`51, 53, and 55, respectively, above junctions 25 and 27
`and gate 18. The unreacted metal which maycover, for
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`example, spacer 21, is subsequently easily washed away.
`this juncture,
`it
`is worthwhile to note several
`At
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`advantages of the structure depicted in FIG. 9 and
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`formed by the sequene of steps in FIGS. 1-7. Silicide
`regions 51 and 53 are self-aligned with respect to the
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`deep junctions 27 and 25, respectively. For example,
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`silicide region 51 coversall of the deep junction 27 but
`does not cover the shallow junction 35 (due, of course,
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`to the presence of layers 21 and 19). It is undesirable for
`silicide region 51 to extend over the shallow junction 35
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`because leakage from the shallow junction to the sub-
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`strate will be dramatically increased. The leakage will
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`be caused by tunneling induced byasperities in the
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`bottom of the silicide layer through the depletion region
`between the lightly doped area such as 35 and substrate
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`11. Another difficulty caused by formation of silicides
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`upon lightly doped regions such as region 35 is that
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`5
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`pny 5
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`30
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`55
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`60
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`65
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`Page 8 of 10
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`Page 8 of 10
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`

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`5,153,145
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`in
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`— wa
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`wwOQ
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`40
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`5
`specific contact resistivity is likely to increase at the
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`interface between the silicide and the dopedsilicon. The
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`increased resistivity is due to the light doping at the
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`interface between the silicide and the dopedsilicon.
`The inventive process may be contrasted with the
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`process discussed in Oh et al. mentioned above. The Oh
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`et al. process employs two layers (oxide followed by
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`nitride) after gate formation. A nitride spacer is formed
`whichserves to define the limits of an underlying oxide
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`spacer. The nitride spacer is removed. leaving only a
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`single oxide spacer prior to junction formation. The
`oxide spacer serves to screen someof the incident ion
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`species during ion implantation. thus forming a one-stop
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`LDD junction. However. the Ohet al. process does not
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`admit the use of a protective oxide layer (such as layer
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`19) over the entire silicon surface to protect against
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`implant damage. Furthermore, applicants’
`two-step
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`junction formation procedure allows moreprecisetail-
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`‘oring of the junction profiles. In the Ohet al. process. a
`subsequent additional CVD spacer must be formed
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`priorto silicide formation. However,it is not possible to
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`precisely align the CVD spacer with the initial oxide
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`spacer (which defines the edge of the deep portion of
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`the junction) and consequentlythe silicide contact can-
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`not be precisely aligned with the deep junction edge.
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`By wayof further comparison, applicants’ process
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`presents various advantages over the process mentioned
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`in the Pfiester article mentioned above. In particular the
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`Pfiester article show's a single spacer with roundedsides
`to separate two separate implantation doses, thus creat-
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`ing an LDD structure. By contrast, applicants’ inven-
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`tion permits the formation of deep and shallowjunction
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`regions by implantation through two different
`thick-
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`nesses of dielectric. Consequently. very precise tailor-
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`ing. of the final junction profile is achievable with appli-
`cants’ invention. Furthermore. the Pfiester article does
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`not mention silicidation. If silicidation were attempted
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`with the Pfiester. there is no method forself-aligning
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`the silicide with the deep junction.
`Furthermore,
`the inventive structure possesses yet
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`another set of advantages over conventional transistor
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`structures and processes. These advantages are enumer-
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`ated below:
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`invention requires less masking than
`The present
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`conventional LDD processes. Typical CMOS LDD
`fabrication requires three or four masks. However, the
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`present invention requires only two masks (one mask
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`covering the p-substrate while the n-substrate is being
`processed and vice versa) to form a CMOS LDDstruc-
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`ture.
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`The present invention helps to prevent shorting be-
`tween source/drain silicide and the gate. It has been
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`found that certain metals such as titanium (commonly
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`used in silicidation of source/drain contacts) maytend
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`to migrate through TEOS-type spacers toward the gate
`and cause shorting between the source/drain and the
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`gate. However, the present invention helps to eliminate
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`this failure mode because spacer 21 (which is typically
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`silicon nitride or silicon oxynitride) forms a protective
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`shield or barrier against metal migration.
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`Another important advantage of the present inven-
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`tion is that layer 21 may help prevent the migration of
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`other types of particles into the gate stack. In particular,
`it has been found that some devices fabricated without
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`layer 21 mayexperience variousfailures during burn-in.
`Somefailures are believed due to the migration ofsili-
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`con particles through conventional silicon oxide gate
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`spacers. The silicon particles may cause shorting of the
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`6
`gate to the source/drain. The present invention helps to
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`eliminate this failure mode when spacer 21 is a material
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`which forms a shield or barrier against silicon migra-
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`tion, such assilicon nitride or silicon oxynitride.
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`When the present invention is comparedto structures
`which utilize a single silicon oxide spacer, another ad-
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`vantage is manifested. The anisotropic etching pracess
`which is used to create a single silicon oxide spacer is
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`frequently carried out beyond nominal completion,i.e.
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`over-etching is performéd. The over-etching frequently
`creates trenchesin the field oxide. A trench mayoccur
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`at the edge wherethefield oxide contacts the source/-
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`drain junction (i.e., where the oxide bird's beak meets
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`the dopedsilicon surface). The trench exposes some of
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`the undopedsilicon substrate.
`Unfortunately, a subsequent salicidation process cre-
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`ates an electrical short circuit between the junction and
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`the exposed silicon in the trench via the salicide. The
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`present invention helps to avoid the over-etching prob-
`lem because layer 21 serves as an etch step during etch-
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`ing of layer 23. When layer 21 is reached, the artisan is
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`on notice that further etching must be done with care.
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`(Another type of over-etching which maybe avoided
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`bythe present invention is trenching which mayoccur
`in a field oxide between two runners which overlie the
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`oxide. The trenching may exaggerate the aspectratio of
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`the space between the runners and makes subsequent
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`dielectric coverage difficult. Again,
`the presence of
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`layer 21 which mayserve as an etch-stop helps to pre-
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`vent the over-etching and trenching problem.)
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`Although application of the inventive concepts has
`been discussed so far chiefly in connection with forma-
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`tion of a lightly doped drain (LDD) structure, the in-
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`ventive concept mayalso be applied to devices which
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`do not require a lightly doped drain. An example of
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`such application is provided by FIG. 8. The structure
`depicted in FIG. 8 is obtained after the structure de-
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`picted in FIG. 4 is fabricated. The structure of FIG. 8 is
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`produced by an ion implantation step and drive-in ap-
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`plied to the structure of FIG. 4. Examination of FIG. 8
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`shows source and drain regions 41 and 43 formed be-
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`neath gate stack 18 which is flanked bylayers 19, 21.
`and 23. It will be noted that layer 23 need not bere-
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`moved from the structure depicted in FIG. 8 because
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`there is no need for a lightly doped junction.
`Another application of the inventive concept is de-
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`picted in FIGS. 11-15. FIG. 11 is a cross-sectional view
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`of a portion of a semiconductor wafer during typical
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`initial steps of fabrication. Substrate 111 maybesilicon
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`or epitaxial silicon. Field oxide 113 is formed upon
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`substrate 111. Gate oxide 115 is formed overlying sub-
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`strate 111. Layer 117, which maybetypically polysili-
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`con, is formed aboved layer 115. Layer 118, which may
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`be silicon nitride or silicon oxynitride, covers layer 117.
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`‘Layers 115, 117, and 118 are formed typically during
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`initial steps of semiconductor wafer fabrication. Com-
`parison of FIG. 11 with FIG. 1 reveals that an extra
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`layer (layer 118) has been deposited in FIG. 11 and is
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`absent in FIG. 1. Typical thicknesses for layers 115, 117,
`and 118 are 100-200 A, 2500-4000 A, and 1500-3000 A,
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`respectively.
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`Turning to FIG. 12, it may be noted that layers 118,
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`117, and 115 have been patterned to produce gates 201
`and 205 together with runner 203 which extends over
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`field oxide 113. Thus, it will be noted that FIGS. 12-15
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`depict the formation of two adjacent transistors sepa-
`rated byfield oxide 113. Furthermore, gate level runner
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`203 extends along field oxide 113. Gate level runner 203
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`50
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`Page 9 of 10
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`Page 9 of 10
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`8
`7
`maybe connected (although not shownin theparticular
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`tated the formation of a sub-gate level interconnection
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`cross-section of FIG. 12} to gate 201 or 205 or to the
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`between junction regions of different transistors (i.¢.. a
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`gale. source. or drain of some other transistor (not
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`connection formed prior to passivation dielectric depo-
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`shown).
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`sition and contact windowopening) without the possi-
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`In FIG. 13 layer 119. which maybesilicon dioxide. is
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`bility of shorting to a gate runner.
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`We claim:
`formed on substrate 111. Next layer 121 is deposited.
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`Layer 121 maybesilicon nitride, or silicon oxynitride.
`1. A method of semiconductor integrated circuit
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`Layer 123 is deposited upon layer 121. Layer 123 may
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`fabrication comprising:
`be formed from TEOS, or BPTEOS,or anyofa variety
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`forming a gate stack upon a substrate:
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`of other deposited dielectrics. Typical thicknesses for
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`forming a first material layer upon said gate stack and
`layers 119, 121, and 123 are similar to the thicknesses for
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`upon said substrate:
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`aforementioned layers 19, 21, and 23 in FIGS. 1-7.
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`forming a second material] layer upon said first mate-
`Next,
`in a manner analogous to that depicted in
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`rial layer:
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`FIGS. 4-10, layers 123, 121, and (optionally) 119 are
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`forming a third material layer upon said second mate-
`anisotropically etched to create spacer layers 119, 121.
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`rial layer;
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`and 123 illustrated in FIG. 14. Source/drain regions
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`anisotropically etching said third layer to formafirst
`300, 301. and 302 maybe formed in a mannersimilar to
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`spacer and then etching said second layer to form a
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`that discussed before. Although FIG. 14 shows the
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`second spacer underlying said first spacer;
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`shapes of junctions 300, 301, and 302 to have standard
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`exposing said substrate to a first dopant species, said
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`profiles,
`lightly doped drain (LDD) profiles may be
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`first and second spacers serving to at least partially
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`created, if desired. by the process discussed in connec-
`block or absorb some ofsaid first dopant species
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`tion with FIGS. 5-7. Should salicidation be desired
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`therebycreating a deep junction: and characterized
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`over source/drain regions 300, 301, and 302 it mayalso
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`by
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`be performed in a manner analogousto that depicted in
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`removing said first spacer;
`FIG. 9. Therefore it should be apparent that although 2
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`exposing sai